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Modified Function definition for BLAS and CBLAS interfaces of ?SCALV API
Details:
-Kernel is called directly from API call to avoid framework
overhead in case of single and double precisions.
-Currently these changes are applicable only for zen2 configuration.
They will be enabled for zen family processors in future.
-These changes improve performance of BLAS and CBLAS interfaces of API.
They do not affect BLIS-specific APIs.
-setv simd kernel is added for single and double precision elements
Change-Id: I1b343aa232f2571717c2b01ada5914f869883e1a
Signed-off-by: Kiran ND <Kiran.Devrajegowda@amd.com>
AMD-Internal: [CPUPL-817]
This commit is contained in:
Devrajegowda, Kiran
committed by
dzambare
dzambare
parent
0ecc147f03
commit
013d6a2cab
@@ -39,45 +39,45 @@
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void bli_cntx_init_zen( cntx_t* cntx )
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{
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blksz_t blkszs[ BLIS_NUM_BLKSZS ];
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blksz_t thresh[ BLIS_NUM_THRESH ];
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blksz_t blkszs[ BLIS_NUM_BLKSZS ];
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blksz_t thresh[ BLIS_NUM_THRESH ];
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// Set default kernel blocksizes and functions.
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bli_cntx_init_zen_ref( cntx );
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// Set default kernel blocksizes and functions.
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bli_cntx_init_zen_ref( cntx );
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// Update the context with optimized native gemm micro-kernels and
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// their storage preferences.
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bli_cntx_set_l3_nat_ukrs
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(
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8,
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// gemm
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BLIS_GEMM_UKR, BLIS_FLOAT, bli_sgemm_haswell_asm_6x16, TRUE,
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BLIS_GEMM_UKR, BLIS_DOUBLE, bli_dgemm_haswell_asm_6x8, TRUE,
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BLIS_GEMM_UKR, BLIS_SCOMPLEX, bli_cgemm_haswell_asm_3x8, TRUE,
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BLIS_GEMM_UKR, BLIS_DCOMPLEX, bli_zgemm_haswell_asm_3x4, TRUE,
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// gemmtrsm_l
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BLIS_GEMMTRSM_L_UKR, BLIS_FLOAT, bli_sgemmtrsm_l_haswell_asm_6x16, TRUE,
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BLIS_GEMMTRSM_L_UKR, BLIS_DOUBLE, bli_dgemmtrsm_l_haswell_asm_6x8, TRUE,
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// gemmtrsm_u
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BLIS_GEMMTRSM_U_UKR, BLIS_FLOAT, bli_sgemmtrsm_u_haswell_asm_6x16, TRUE,
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BLIS_GEMMTRSM_U_UKR, BLIS_DOUBLE, bli_dgemmtrsm_u_haswell_asm_6x8, TRUE,
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cntx
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);
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// Update the context with optimized native gemm micro-kernels and
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// their storage preferences.
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bli_cntx_set_l3_nat_ukrs
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(
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8,
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// gemm
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BLIS_GEMM_UKR, BLIS_FLOAT, bli_sgemm_haswell_asm_6x16, TRUE,
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BLIS_GEMM_UKR, BLIS_DOUBLE, bli_dgemm_haswell_asm_6x8, TRUE,
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BLIS_GEMM_UKR, BLIS_SCOMPLEX, bli_cgemm_haswell_asm_3x8, TRUE,
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BLIS_GEMM_UKR, BLIS_DCOMPLEX, bli_zgemm_haswell_asm_3x4, TRUE,
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// gemmtrsm_l
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BLIS_GEMMTRSM_L_UKR, BLIS_FLOAT, bli_sgemmtrsm_l_haswell_asm_6x16, TRUE,
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BLIS_GEMMTRSM_L_UKR, BLIS_DOUBLE, bli_dgemmtrsm_l_haswell_asm_6x8, TRUE,
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// gemmtrsm_u
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BLIS_GEMMTRSM_U_UKR, BLIS_FLOAT, bli_sgemmtrsm_u_haswell_asm_6x16, TRUE,
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BLIS_GEMMTRSM_U_UKR, BLIS_DOUBLE, bli_dgemmtrsm_u_haswell_asm_6x8, TRUE,
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cntx
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);
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// Update the context with optimized level-1f kernels.
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bli_cntx_set_l1f_kers
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(
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4,
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// axpyf
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BLIS_AXPYF_KER, BLIS_FLOAT, bli_saxpyf_zen_int_8,
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BLIS_AXPYF_KER, BLIS_DOUBLE, bli_daxpyf_zen_int_8,
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// dotxf
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BLIS_DOTXF_KER, BLIS_FLOAT, bli_sdotxf_zen_int_8,
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BLIS_DOTXF_KER, BLIS_DOUBLE, bli_ddotxf_zen_int_8,
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cntx
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);
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// Update the context with optimized level-1f kernels.
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bli_cntx_set_l1f_kers
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(
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4,
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// axpyf
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BLIS_AXPYF_KER, BLIS_FLOAT, bli_saxpyf_zen_int_8,
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BLIS_AXPYF_KER, BLIS_DOUBLE, bli_daxpyf_zen_int_8,
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// dotxf
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BLIS_DOTXF_KER, BLIS_FLOAT, bli_sdotxf_zen_int_8,
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BLIS_DOTXF_KER, BLIS_DOUBLE, bli_ddotxf_zen_int_8,
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cntx
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);
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// Update the context with optimized level-1v kernels.
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bli_cntx_set_l1v_kers
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@@ -88,53 +88,55 @@ void bli_cntx_init_zen( cntx_t* cntx )
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BLIS_AMAXV_KER, BLIS_DOUBLE, bli_damaxv_zen_int,
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// axpyv
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#if 0
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int,
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int,
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#else
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int10,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int10,
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int10,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int10,
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#endif
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// dotv
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BLIS_DOTV_KER, BLIS_FLOAT, bli_sdotv_zen_int,
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BLIS_DOTV_KER, BLIS_DOUBLE, bli_ddotv_zen_int,
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// dotxv
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BLIS_DOTXV_KER, BLIS_FLOAT, bli_sdotxv_zen_int,
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BLIS_DOTXV_KER, BLIS_DOUBLE, bli_ddotxv_zen_int,
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// scalv
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// dotv
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BLIS_DOTV_KER, BLIS_FLOAT, bli_sdotv_zen_int,
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BLIS_DOTV_KER, BLIS_DOUBLE, bli_ddotv_zen_int,
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// dotxv
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BLIS_DOTXV_KER, BLIS_FLOAT, bli_sdotxv_zen_int,
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BLIS_DOTXV_KER, BLIS_DOUBLE, bli_ddotxv_zen_int,
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// scalv
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#if 0
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int,
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int,
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#else
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int10,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int10,
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int10,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int10,
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#endif
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BLIS_SWAPV_KER, BLIS_FLOAT, bli_sswapv_zen_int8,
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BLIS_SWAPV_KER, BLIS_DOUBLE, bli_dswapv_zen_int8,
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BLIS_COPYV_KER, BLIS_FLOAT, bli_scopyv_zen_int,
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BLIS_COPYV_KER, BLIS_DOUBLE, bli_dcopyv_zen_int,
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BLIS_SWAPV_KER, BLIS_FLOAT, bli_sswapv_zen_int8,
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BLIS_SWAPV_KER, BLIS_DOUBLE, bli_dswapv_zen_int8,
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cntx
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);
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BLIS_COPYV_KER, BLIS_FLOAT, bli_scopyv_zen_int,
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BLIS_COPYV_KER, BLIS_DOUBLE, bli_dcopyv_zen_int,
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//set
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BLIS_SETV_KER, BLIS_FLOAT, bli_ssetv_zen_int,
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BLIS_SETV_KER, BLIS_DOUBLE, bli_dsetv_zen_int,
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cntx
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);
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// Initialize level-3 blocksize objects with architecture-specific values.
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// s d c z
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bli_blksz_init_easy( &blkszs[ BLIS_MR ], 6, 6, 3, 3 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], 16, 8, 8, 4 );
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// Initialize level-3 blocksize objects with architecture-specific values.
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// s d c z
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bli_blksz_init_easy( &blkszs[ BLIS_MR ], 6, 6, 3, 3 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], 16, 8, 8, 4 );
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/*
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<<<<<<< HEAD
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Multi Instance performance improvement of DGEMM when binded to a CCX
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In Multi instance each thread runs a sequential DGEMM.
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a) If BLIS is run in a multi-instance mode with
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CPU freq 2.6/2.2 Ghz
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DDR4 clock frequency 2400Mhz
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mc = 240, kc = 512, and nc = 2040
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has better performance on EPYC server, over the default block sizes.
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a) If BLIS is run in a multi-instance mode with
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CPU freq 2.6/2.2 Ghz
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DDR4 clock frequency 2400Mhz
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mc = 240, kc = 512, and nc = 2040
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has better performance on EPYC server, over the default block sizes.
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b) If BLIS is run in Single Instance mode
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mc = 510, kc = 1024 and nc = 4080
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b) If BLIS is run in Single Instance mode
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mc = 510, kc = 1024 and nc = 4080
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*/
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// Zen optmized level 3 cache block sizes
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@@ -150,45 +152,43 @@ void bli_cntx_init_zen( cntx_t* cntx )
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 4080, 2040, 2040, 1528 );
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#endif
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#else
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 144, 72, 144, 72 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], 256, 256, 256, 256 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 8160, 4080, 4080, 3056 );
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 144, 72, 144, 72 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], 256, 256, 256, 256 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 8160, 4080, 4080, 3056 );
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#endif
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bli_blksz_init_easy( &blkszs[ BLIS_AF ], 8, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_DF ], 8, 8, -1, -1 );
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// Update the context with the current architecture's register and cache
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// blocksizes (and multiples) for native execution.
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bli_cntx_set_blkszs
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(
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BLIS_NAT, 7,
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// level-3
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BLIS_NC, &blkszs[ BLIS_NC ], BLIS_NR,
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BLIS_KC, &blkszs[ BLIS_KC ], BLIS_KR,
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BLIS_MC, &blkszs[ BLIS_MC ], BLIS_MR,
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BLIS_NR, &blkszs[ BLIS_NR ], BLIS_NR,
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BLIS_MR, &blkszs[ BLIS_MR ], BLIS_MR,
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// level-1f
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BLIS_AF, &blkszs[ BLIS_AF ], BLIS_AF,
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BLIS_DF, &blkszs[ BLIS_DF ], BLIS_DF,
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cntx
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);
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bli_blksz_init_easy( &blkszs[ BLIS_AF ], 8, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_DF ], 8, 8, -1, -1 );
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// Update the context with the current architecture's register and cache
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// blocksizes for level-3 TRSM execution.
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bli_cntx_set_trsm_blkszs
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(
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5,
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// level-3
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BLIS_NC, &blkszs[ BLIS_NC ],
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BLIS_KC, &blkszs[ BLIS_KC ],
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BLIS_MC, &blkszs[ BLIS_MC ],
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BLIS_NR, &blkszs[ BLIS_NR ],
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BLIS_MR, &blkszs[ BLIS_MR ],
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cntx
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);
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// blocksizes (and multiples) for native execution.
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bli_cntx_set_blkszs
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(
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BLIS_NAT, 7,
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// level-3
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BLIS_NC, &blkszs[ BLIS_NC ], BLIS_NR,
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BLIS_KC, &blkszs[ BLIS_KC ], BLIS_KR,
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BLIS_MC, &blkszs[ BLIS_MC ], BLIS_MR,
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BLIS_NR, &blkszs[ BLIS_NR ], BLIS_NR,
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BLIS_MR, &blkszs[ BLIS_MR ], BLIS_MR,
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// level-1f
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BLIS_AF, &blkszs[ BLIS_AF ], BLIS_AF,
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BLIS_DF, &blkszs[ BLIS_DF ], BLIS_DF,
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cntx
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);
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// -------------------------------------------------------------------------
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// Update the context with the current architecture's register and cache
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// blocksizes for level-3 TRSM execution.
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bli_cntx_set_trsm_blkszs
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(
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5,
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// level-3
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BLIS_NC, &blkszs[ BLIS_NC ],
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BLIS_KC, &blkszs[ BLIS_KC ],
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BLIS_MC, &blkszs[ BLIS_MC ],
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BLIS_NR, &blkszs[ BLIS_NR ],
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BLIS_MR, &blkszs[ BLIS_MR ],
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cntx
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);
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// Initialize sup thresholds with architecture-appropriate values.
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// s d c z
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@@ -196,67 +196,72 @@ void bli_cntx_init_zen( cntx_t* cntx )
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bli_blksz_init_easy( &thresh[ BLIS_NT ], -1, 256, -1, -1 );
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bli_blksz_init_easy( &thresh[ BLIS_KT ], -1, 220, -1, -1 );
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// Initialize the context with the sup thresholds.
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bli_cntx_set_l3_sup_thresh
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(
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3,
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BLIS_MT, &thresh[ BLIS_MT ],
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BLIS_NT, &thresh[ BLIS_NT ],
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BLIS_KT, &thresh[ BLIS_KT ],
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cntx
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);
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// Initialize sup thresholds with architecture-appropriate values.
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// s d c z
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bli_blksz_init_easy( &thresh[ BLIS_MT ], 512, 256, -1, -1 );
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bli_blksz_init_easy( &thresh[ BLIS_NT ], 512, 256, -1, -1 );
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bli_blksz_init_easy( &thresh[ BLIS_KT ], 440, 220, -1, -1 );
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// Initialize the context with the sup handlers.
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bli_cntx_set_l3_sup_handlers
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(
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1,
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BLIS_GEMM, bli_gemmsup_ref,
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cntx
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);
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// Initialize the context with the sup thresholds.
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bli_cntx_set_l3_sup_thresh
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(
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3,
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BLIS_MT, &thresh[ BLIS_MT ],
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BLIS_NT, &thresh[ BLIS_NT ],
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BLIS_KT, &thresh[ BLIS_KT ],
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cntx
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);
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// Update the context with optimized small/unpacked gemm kernels.
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bli_cntx_set_l3_sup_kers
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(
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14,
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//BLIS_RCR, BLIS_DOUBLE, bli_dgemmsup_r_haswell_ref,
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BLIS_RRR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
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BLIS_RRC, BLIS_DOUBLE, bli_dgemmsup_rd_haswell_asm_6x8m, TRUE,
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BLIS_RCR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
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BLIS_RCC, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
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BLIS_CRR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
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BLIS_CRC, BLIS_DOUBLE, bli_dgemmsup_rd_haswell_asm_6x8n, TRUE,
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BLIS_CCR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
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BLIS_CCC, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
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BLIS_RRR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16m, TRUE,
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BLIS_RCR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16m, TRUE,
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BLIS_RCC, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16n, TRUE,
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BLIS_CRR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16m, TRUE,
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BLIS_CCR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16n, TRUE,
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BLIS_CCC, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16n, TRUE,
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cntx
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);
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// Initialize the context with the sup handlers.
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bli_cntx_set_l3_sup_handlers
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(
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1,
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BLIS_GEMM, bli_gemmsup_ref,
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cntx
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);
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// Initialize level-3 sup blocksize objects with architecture-specific
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// values.
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// s d c z
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bli_blksz_init ( &blkszs[ BLIS_MR ], 6, 6, -1, -1,
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9, 9, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], 16, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 144, 72, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], 512, 256, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 8160, 4080, -1, -1 );
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// Update the context with optimized small/unpacked gemm kernels.
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bli_cntx_set_l3_sup_kers
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(
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14,
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//BLIS_RCR, BLIS_DOUBLE, bli_dgemmsup_r_haswell_ref,
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BLIS_RRR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
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BLIS_RRC, BLIS_DOUBLE, bli_dgemmsup_rd_haswell_asm_6x8m, TRUE,
|
||||
BLIS_RCR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
|
||||
BLIS_RCC, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
|
||||
BLIS_CRR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
|
||||
BLIS_CRC, BLIS_DOUBLE, bli_dgemmsup_rd_haswell_asm_6x8n, TRUE,
|
||||
BLIS_CCR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
|
||||
BLIS_CCC, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
|
||||
BLIS_RRR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16m, TRUE,
|
||||
BLIS_RCR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16m, TRUE,
|
||||
BLIS_RCC, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16n, TRUE,
|
||||
BLIS_CRR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16m, TRUE,
|
||||
BLIS_CCR, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16n, TRUE,
|
||||
BLIS_CCC, BLIS_FLOAT, bli_sgemmsup_rv_zen_asm_6x16n, TRUE,
|
||||
cntx
|
||||
);
|
||||
|
||||
// Update the context with the current architecture's register and cache
|
||||
// blocksizes for small/unpacked level-3 problems.
|
||||
bli_cntx_set_l3_sup_blkszs
|
||||
(
|
||||
5,
|
||||
BLIS_NC, &blkszs[ BLIS_NC ],
|
||||
BLIS_KC, &blkszs[ BLIS_KC ],
|
||||
BLIS_MC, &blkszs[ BLIS_MC ],
|
||||
BLIS_NR, &blkszs[ BLIS_NR ],
|
||||
BLIS_MR, &blkszs[ BLIS_MR ],
|
||||
cntx
|
||||
);
|
||||
}
|
||||
// Initialize level-3 sup blocksize objects with architecture-specific
|
||||
// values.
|
||||
// s d c z
|
||||
bli_blksz_init ( &blkszs[ BLIS_MR ], 6, 6, -1, -1,
|
||||
9, 9, -1, -1 );
|
||||
bli_blksz_init_easy( &blkszs[ BLIS_NR ], 16, 8, -1, -1 );
|
||||
bli_blksz_init_easy( &blkszs[ BLIS_MC ], 144, 72, -1, -1 );
|
||||
bli_blksz_init_easy( &blkszs[ BLIS_KC ], 512, 256, -1, -1 );
|
||||
bli_blksz_init_easy( &blkszs[ BLIS_NC ], 8160, 4080, -1, -1 );
|
||||
|
||||
// Update the context with the current architecture's register and cache
|
||||
// blocksizes for small/unpacked level-3 problems.
|
||||
bli_cntx_set_l3_sup_blkszs
|
||||
(
|
||||
5,
|
||||
BLIS_NC, &blkszs[ BLIS_NC ],
|
||||
BLIS_KC, &blkszs[ BLIS_KC ],
|
||||
BLIS_MC, &blkszs[ BLIS_MC ],
|
||||
BLIS_NR, &blkszs[ BLIS_NR ],
|
||||
BLIS_MR, &blkszs[ BLIS_MR ],
|
||||
cntx
|
||||
);
|
||||
}
|
||||
@@ -12,7 +12,7 @@
|
||||
*/
|
||||
#include "cblas.h"
|
||||
#include "cblas_f77.h"
|
||||
void cblas_dscal( f77_int N, double alpha, double *X,
|
||||
void cblas_dscal( f77_int N, double alpha, double *X,
|
||||
f77_int incX)
|
||||
{
|
||||
#ifdef F77_INT
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
*/
|
||||
#include "cblas.h"
|
||||
#include "cblas_f77.h"
|
||||
void cblas_sscal( f77_int N, float alpha, float *X,
|
||||
void cblas_sscal( f77_int N, float alpha, float *X,
|
||||
f77_int incX)
|
||||
{
|
||||
#ifdef F77_INT
|
||||
|
||||
Reference in New Issue
Block a user