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Evict <arm_sve.h> Requirement for SVE GEMM
For 8<= GCC < 10 compatibility.
This commit is contained in:
committed by
Devin Matthews
parent
54fa28bd84
commit
08174a2f6e
@@ -33,7 +33,6 @@
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*/
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#include "blis.h"
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#include "bli_armsve_config_utils.h"
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void bli_cntx_init_armsve( cntx_t* cntx )
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{
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@@ -35,7 +35,7 @@
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*/
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#include "blis.h"
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dim_t bli_vl_bits_armsve(void)
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dim_t bli_vl_bytes_armsve(void)
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{ \
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uint64_t vl = 0;
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__asm__ (
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@@ -43,7 +43,7 @@ dim_t bli_vl_bits_armsve(void)
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" incb x0 \n\t"
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" mov %[vl], x0 \n\t"
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: [vl] "=r" (vl)
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:
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:
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: "x0"
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);
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return vl;
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@@ -64,7 +64,7 @@ void PASTEMAC(ch, _blksz_armsve) (dim_t *m_r_, dim_t *n_r_, \
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dim_t N_L3 = bli_env_get_var("BLIS_SVE_N_L3", N_L3_SVE_DEFAULT); \
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dim_t C_L3 = bli_env_get_var("BLIS_SVE_C_L3", C_L3_SVE_DEFAULT); \
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\
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dim_t vl_b = bli_vl_bits_armsve(); \
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dim_t vl_b = bli_vl_bytes_armsve(); \
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dim_t vl = vl_b / S_Data; \
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dim_t m_r = 2 * vl; \
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dim_t n_r = 10; \
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@@ -35,7 +35,7 @@
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*/
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#include "blis.h"
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dim_t bli_vl_bits_armsve(void);
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dim_t bli_vl_bytes_armsve(void);
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void bli_s_blksz_armsve(dim_t *m_r_, dim_t *n_r_, dim_t *k_c_, dim_t *m_c_, dim_t *n_c_);
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void bli_d_blksz_armsve(dim_t *m_r_, dim_t *n_r_, dim_t *k_c_, dim_t *m_c_, dim_t *n_c_);
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@@ -42,7 +42,6 @@
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// 2vx10 microkernels.
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#include "armsve_asm_2vx10cmplx.h"
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#include "arm_sve.h"
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void bli_cgemm_armsve_asm_2vx10_unindexed
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(
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@@ -69,7 +68,7 @@ void bli_cgemm_armsve_asm_2vx10_unindexed
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uint64_t cs_c = cs_c0;
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uint64_t info = 0;
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uint64_t mr = svcntw();
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uint64_t mr = bli_vl_bytes_armsve() * 2 / 8;
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GEMM_UKR_SETUP_CT( c, mr, 10, false );
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__asm__ volatile (
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@@ -42,7 +42,6 @@
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// 2vx10 microkernels.
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#include "armsve_asm_2vx10.h"
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#include "arm_sve.h"
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void bli_dgemm_armsve_asm_2vx10_unindexed
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(
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@@ -68,7 +67,7 @@ void bli_dgemm_armsve_asm_2vx10_unindexed
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uint64_t rs_c = rs_c0;
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uint64_t cs_c = cs_c0;
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uint64_t mr = 2*svcntd();
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uint64_t mr = bli_vl_bytes_armsve() * 2 / 8;
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GEMM_UKR_SETUP_CT( d, mr, 10, false );
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__asm__ volatile (
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@@ -42,7 +42,6 @@
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// 2vx10 microkernels.
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#include "armsve_asm_2vx10.h"
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#include "arm_sve.h"
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void bli_sgemm_armsve_asm_2vx10_unindexed
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(
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@@ -68,7 +67,7 @@ void bli_sgemm_armsve_asm_2vx10_unindexed
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uint64_t rs_c = rs_c0;
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uint64_t cs_c = cs_c0;
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uint64_t mr = 2*svcntw();
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uint64_t mr = bli_vl_bytes_armsve() * 2 / 4;
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GEMM_UKR_SETUP_CT( s, mr, 10, false );
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__asm__ volatile (
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@@ -42,7 +42,6 @@
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// 2vx10 microkernels.
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#include "armsve_asm_2vx10cmplx.h"
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#include "arm_sve.h"
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void bli_zgemm_armsve_asm_2vx10_unindexed
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(
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@@ -69,7 +68,7 @@ void bli_zgemm_armsve_asm_2vx10_unindexed
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uint64_t cs_c = cs_c0;
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uint64_t info = 0;
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uint64_t mr = svcntd();
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uint64_t mr = bli_vl_bytes_armsve() * 2 / 16;
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GEMM_UKR_SETUP_CT( z, mr, 10, false );
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__asm__ volatile (
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@@ -42,7 +42,6 @@
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// 2vx7 microkernels.
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#include "armsve_asm_2vx7cmplx.h"
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#include "arm_sve.h"
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void bli_zgemm_armsve_asm_2vx7_unindexed
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(
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@@ -69,7 +68,7 @@ void bli_zgemm_armsve_asm_2vx7_unindexed
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uint64_t cs_c = cs_c0;
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uint64_t info = 0;
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uint64_t mr = svcntd();
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uint64_t mr = bli_vl_bytes_armsve() * 2 / 16;
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GEMM_UKR_SETUP_CT( z, mr, 7, false );
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__asm__ volatile (
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@@ -42,8 +42,6 @@
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// 2vx8 microkernels.
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#include "armsve_asm_2vx8cmplx.h"
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#include "arm_sve.h"
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void bli_zgemm_armsve_asm_2vx8_unindexed
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(
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dim_t m,
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@@ -69,7 +67,7 @@ void bli_zgemm_armsve_asm_2vx8_unindexed
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uint64_t cs_c = cs_c0;
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uint64_t info = 0;
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uint64_t mr = svcntd();
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uint64_t mr = bli_vl_bytes_armsve() * 2 / 16;
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GEMM_UKR_SETUP_CT( z, mr, 8, false );
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__asm__ volatile (
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@@ -31,6 +31,7 @@
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "./3/bli_armsve_utils.h"
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GEMM_UKR_PROT( double, d, gemm_armsve256_asm_8x8 )
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GEMM_UKR_PROT( double, d, gemm_armsve_asm_2vx10_unindexed )
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