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Fixed bug in bli_dgemm_avx512 8x24 native kernel.

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-  Data-type of m, n, k,ldc is dim_t which will be int32_t for LP64 case.
-  When loading 64-bit registers using "mov" instructions, mov(rax, var(m)),
   the "m" should be 64-bit otherwise incorrect values gets loaded.

Fix: We typecast these variables to int64_t before loading into registers.

AMD-Internal: [CPUPL-5819]
Change-Id: I16043ac168a79ff9358c0c1768989a81e3c6b0e0
This commit is contained in:
Shubham Sharma
2024-09-23 06:10:40 +00:00
committed by Shubham Sharma
parent 16653ed208
commit 1833ee70cd
1 changed files with 20 additions and 16 deletions
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36
kernels/zen5/3/bli_dgemm_avx512_asm_8x24.c
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@@ -1042,6 +1042,10 @@ void bli_dgemm_avx512_asm_8x24(
LEA(RCX, MEM(RCX, R10, 1)) \
#define PRE_K_LOOP() \
const int64_t n = n0; \
const int64_t m = m0; \
const int64_t k = k0; \
const int64_t ldc = ldc0; \
BEGIN_ASM() \
\
MOV(RDI, VAR(n)) /* load N into RDI */ \
@@ -1128,13 +1132,13 @@ void bli_dgemm_avx512_asm_8x24(
*/
BLIS_INLINE void bli_dgemm_avx512_asm_8x24_macro_kernel_b0
(
dim_t n,
dim_t m,
dim_t k,
dim_t n0,
dim_t m0,
dim_t k0,
double* c,
double* a,
double* b,
dim_t ldc,
dim_t ldc0,
double* beta
)
{
@@ -1159,13 +1163,13 @@ BLIS_INLINE void bli_dgemm_avx512_asm_8x24_macro_kernel_b0
*/
BLIS_INLINE void bli_dgemm_avx512_asm_8x24_macro_kernel_b1
(
dim_t n,
dim_t m,
dim_t k,
dim_t n0,
dim_t m0,
dim_t k0,
double* c,
double* a,
double* b,
dim_t ldc,
dim_t ldc0,
double* beta
)
{
@@ -1190,13 +1194,13 @@ BLIS_INLINE void bli_dgemm_avx512_asm_8x24_macro_kernel_b1
*/
BLIS_INLINE void bli_dgemm_avx512_asm_8x24_macro_kernel_bm1
(
dim_t n,
dim_t m,
dim_t k,
dim_t n0,
dim_t m0,
dim_t k0,
double* c,
double* a,
double* b,
dim_t ldc,
dim_t ldc0,
double* beta
)
{
@@ -1223,13 +1227,13 @@ BLIS_INLINE void bli_dgemm_avx512_asm_8x24_macro_kernel_bm1
*/
BLIS_INLINE void bli_dgemm_avx512_asm_8x24_macro_kernel_bn
(
dim_t n,
dim_t m,
dim_t k,
dim_t n0,
dim_t m0,
dim_t k0,
double* c,
double* a,
double* b,
dim_t ldc,
dim_t ldc0,
double* beta
)
{