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Fix parsing in vpu_count on workstation SKX (#351)
* Fix parsing in vpu_count on workstation SKX * Document Skylake-X as Haswell for single FMA * Update vpu_count for Skylake and Cascade Lake models * Support printing the configuration selected, controlled by the environment Intended particularly for diagnosing mis-selection of SKX through unknown, or incorrect, number of VPUs. * Move bli_log outside the cpp condition, and use it where intended * Add Fixme comment (Skylake D) * Mostly superficial edits to commits towards #351. Details: - Moved architecture/sub-config logging-related code from bli_cpuid.c to bli_arch.c, tweaked names, and added more set/get layering. - Tweaked log messages output from bli_cpuid_is_skx() in bli_cpuid.c. - Content, whitespace changes to new bullet in HardwareSupport.md that relates to single-VPU Skylake-Xs. * Fix comment typos Co-authored-by: Field G. Van Zee <field@cs.utexas.edu>
This commit is contained in:
Dave Love
committed by
Devrajegowda, Kiran
Devrajegowda, Kiran
parent
99da76fd64
commit
291ee5f748
@@ -15,6 +15,7 @@ A few remarks / reminders:
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* Induced complex (1m) implementations are employed in all situations where the real domain [gemm microkernel](KernelsHowTo.md#gemm-microkernel) of the corresponding precision is available, but the "native" complex domain gemm microkernel is unavailable. Note that the table below lists native kernels, so if a microarchitecture lists only `sd`, support for both `c` and `z` datatypes will be provided via the 1m method. (Note: most people cannot tell the difference between native and 1m-based performance.) Please see our [ACM TOMS article on the 1m method](https://github.com/flame/blis#citations) for more info on this topic.
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* Some microarchitectures use the same sub-configuration. *This is not a typo.* For example, Haswell and Broadwell systems as well as "desktop" (non-server) versions of Skylake, Kaby Lake, and Coffee Lake all use the `haswell` sub-configuration and the kernels registered therein. Microkernels can be recycled in this manner because the key detail that determines level-3 performance outcomes is actually the vector ISA, not the microarchitecture. In the previous example, all of the microarchitectures listed support AVX2 (but not AVX-512), and therefore they can reuse the same microkernels.
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* Remember that you (usually) don't have to choose your sub-configuration manually! Instead, you can always request configure-time hardware detection via `./configure auto`. This will defer to internal logic (based on CPUID for x86_64 systems) that will attempt to choose the appropriate sub-configuration automatically.
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* There is a difficulty in automatically choosing the ideal sub-configuration for use on Skylake-X systems, which may have one or two FMA units. The `skx` sub-configuration is only beneficial when used on hardware with two FMA units. Otherwise the hardware is treated as a "desktop" Skylake system, which uses the `haswell` sub-configuration. Furthermore, the number of units can't be queried directly; instead, we rely on a manually-maintained list of CPU models (via logic in `frame/base/bli_cpuid.c`), which may be incorrect for new processors, particularly Gold models. In that case, you can either fix the code (and please raise an issue!) or manually target the `skx` at configure-time (i.e., `./configure [options] skx`). If your performance seems low, you can set `export BLIS_ARCH_DEBUG=1`, which will cause BLIS to output some basic debugging info to `stderr` that will reveal whether your system was detected as having one or two VPUs (FMA units).
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| Vendor/Microarchitecture | BLIS sub-configuration | `gemm` | `gemmtrsm` |
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|:-------------------------------------|:-----------------------|:-------|:-----------|
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@@ -28,7 +29,8 @@ A few remarks / reminders:
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| Intel Haswell, Broadwell (AVX/FMA3) | `haswell` | `sdcz` | `sd` |
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| Intel Sky/Kaby/CoffeeLake (AVX/FMA3) | `haswell` | `sdcz` | `sd` |
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| Intel Knights Landing (AVX-512/FMA3) | `knl` | `sd` | |
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| Intel SkylakeX (AVX-512/FMA3) | `skx` | `sd` | |
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| Intel SkylakeX (AVX-512/2×FMA3) | `skx` | `sd` | |
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| Intel SkylakeX (AVX-512/1×FMA3) | `haswell` | `sdcz` | `sd` |
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| ARMv7 Cortex-A9 (NEON) | `cortex-a9` | `sd` | |
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| ARMv7 Cortex-A15 (NEON) | `cortex-a15` | `sd` | |
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| ARMv8 Cortex-A53 (NEON) | `cortex-a53` | `sd` | |
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@@ -74,6 +74,12 @@ void bli_arch_set_id_once( void )
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void bli_arch_set_id( void )
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{
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// NOTE: Change this usage of getenv() to bli_env_get_var() after
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// merging #351.
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//bool_t do_logging = bli_env_get_var( "BLIS_ARCH_DEBUG", 0 );
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bool_t do_logging = getenv( "BLIS_ARCH_DEBUG" ) != NULL;
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bli_arch_set_logging( do_logging );
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// Architecture families.
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#if defined BLIS_FAMILY_INTEL64 || \
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defined BLIS_FAMILY_AMD64 || \
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@@ -156,6 +162,10 @@ void bli_arch_set_id( void )
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id = BLIS_ARCH_GENERIC;
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#endif
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if ( bli_arch_get_logging() )
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fprintf( stderr, "libblis: selecting sub-configuration '%s'.\n",
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bli_arch_string( id ) );
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//printf( "blis_arch_query_id(): id = %u\n", id );
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//exit(1);
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}
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@@ -200,3 +210,37 @@ char* bli_arch_string( arch_t id )
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return config_name[ id ];
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}
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// -----------------------------------------------------------------------------
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static bool_t arch_dolog = 0;
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void bli_arch_set_logging( bool_t dolog )
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{
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arch_dolog = dolog;
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}
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bool_t bli_arch_get_logging( void )
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{
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return arch_dolog;
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}
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void bli_arch_log( char* fmt, ... )
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{
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char prefix[] = "libblis: ";
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int n_chars = strlen( prefix ) + strlen( fmt ) + 1;
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if ( bli_arch_get_logging() && fmt )
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{
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char* prefix_fmt = malloc( n_chars );
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snprintf( prefix_fmt, n_chars, "%s%s", prefix, fmt );
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va_list ap;
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va_start( ap, fmt );
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vfprintf( stderr, prefix_fmt, ap );
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va_end( ap );
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free( prefix_fmt );
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}
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}
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@@ -42,6 +42,9 @@ void bli_arch_set_id( void );
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BLIS_EXPORT_BLIS char* bli_arch_string( arch_t id );
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void bli_arch_set_logging( bool_t dolog );
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bool_t bli_arch_get_logging( void );
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void bli_arch_log( char*, ... );
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#endif
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@@ -6,6 +6,7 @@
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2018-2019, Advanced Micro Devices, Inc.
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Copyright (C) 2019, Dave Love, University of Manchester
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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@@ -52,6 +53,7 @@
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#include "bli_cpuid.h"
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#else
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#include "blis.h"
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#include "bli_arch.h"
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#endif
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// -----------------------------------------------------------------------------
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@@ -167,7 +169,22 @@ bool_t bli_cpuid_is_skx
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int nvpu = vpu_count();
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if ( !bli_cpuid_has_features( features, expected ) || nvpu != 2 )
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if ( bli_cpuid_has_features( features, expected ) )
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{
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switch ( nvpu )
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{
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case 1:
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bli_arch_log( "Hardware has 1 FMA unit; using 'haswell' (not 'skx') sub-config.\n" );
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return FALSE;
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case 2:
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bli_arch_log( "Hardware has 2 FMA units; using 'skx' sub-config.\n" );
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return TRUE;
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default:
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bli_arch_log( "Number of FMA units unknown; using 'haswell' (not 'skx') config.\n" );
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return FALSE;
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}
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}
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else
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return FALSE;
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return TRUE;
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@@ -893,6 +910,10 @@ void get_cpu_name( char *cpu_name )
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*( uint32_t* )&cpu_name[32+12] = edx;
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}
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// Return the number of FMA units _assuming avx512 is supported_.
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// This needs updating for new processor types, sigh.
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// See https://ark.intel.com/content/www/us/en/ark.html#@Processors
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// and also https://github.com/jeffhammond/vpu-count
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int vpu_count( void )
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{
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char cpu_name[48] = {};
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@@ -904,49 +925,59 @@ int vpu_count( void )
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if ( strstr( cpu_name, "Intel(R) Xeon(R)" ) != NULL )
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{
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loc = strstr( cpu_name, "Platinum" );
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if (( loc = strstr( cpu_name, "Platinum" ) ))
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return 2;
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if ( loc == NULL )
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loc = strstr( cpu_name, "Gold" );
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loc = strstr( cpu_name, "Gold" ); // 1 or 2, tested below
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if ( loc == NULL )
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loc = strstr( cpu_name, "Silver" );
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if (( loc = strstr( cpu_name, "Silver" ) ))
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return 1;
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if ( loc == NULL )
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loc = strstr( cpu_name, "Bronze" );
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if (( loc = strstr( cpu_name, "Bronze" ) ))
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return 1;
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if ( loc == NULL )
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loc = strstr( cpu_name, "W" );
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if ( loc == NULL )
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if (( loc = strstr( cpu_name, "D" ) ))
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// Fixme: May be wrong
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// <https://github.com/jeffhammond/vpu-count/issues/3#issuecomment-542044651>
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return 1;
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if ( loc == NULL )
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return -1;
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loc = strstr( loc+1, " " );
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// We may have W-nnnn rather than, say, Gold nnnn
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if ( 'W' == *loc && '-' == *(loc+1) )
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loc++;
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else
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loc = strstr( loc+1, " " );
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if ( loc == NULL )
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return -1;
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strncpy( model_num, loc+1, 4 );
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model_num[4] = '\0';
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model_num[4] = '\0'; // Things like i9-10900X matched above
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sku = atoi( model_num );
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// These were derived from ARK listings as of 2019-10-09, but
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// may not be complete, especially as the ARK Skylake listing
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// seems to be limited.
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if ( 8199 >= sku && sku >= 8100 ) return 2;
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else if ( 6199 >= sku && sku >= 6100 ) return 2;
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else if ( sku == 5122 ) return 2;
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else if ( 6299 >= sku && sku >= 6200 ) return 2; // Cascade Lake Gold
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else if ( 5299 >= sku && sku >= 5200 ) return 1; // Cascade Lake Gold
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else if ( 5199 >= sku && sku >= 5100 ) return 1;
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else if ( 4199 >= sku && sku >= 4100 ) return 1;
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else if ( 3199 >= sku && sku >= 3100 ) return 1;
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else if ( 3299 >= sku && sku >= 3200 ) return 2; // Cascade Lake W
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else if ( 2299 >= sku && sku >= 2200 ) return 2; // Cascade Lake W
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else if ( 2199 >= sku && sku >= 2120 ) return 2;
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else if ( 2102 == sku || sku == 2104 ) return 2; // Gold exceptions
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else if ( 2119 >= sku && sku >= 2100 ) return 1;
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else return -1;
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}
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else if ( strstr( cpu_name, "Intel(R) Core(TM) i9" ) != NULL )
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{
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return 1;
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}
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else if ( strstr( cpu_name, "Intel(R) Core(TM) i7" ) != NULL )
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{
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if ( strstr( cpu_name, "7800X" ) != NULL ||
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strstr( cpu_name, "7820X" ) != NULL )
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return 1;
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else
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return -1;
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}
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else if ( strstr( cpu_name, "Intel(R) Core(TM)" ) != NULL )
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return 2; // All i7/i9 with avx512?
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else
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{
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return -1;
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@@ -1082,3 +1113,4 @@ char* find_string_in( char* target, char* buffer, size_t buf_len, char* filepath
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}
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#endif
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