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DTL logs corrections

Browse Source 
-- Fixed issues in printing the values of
     side, uploa and diaga parameters for
     hemm, hemv, her, her2, her2k, herk,
     symm, symv, syr, syr2, syr2k, syrk,
     trmm, trmv, trsm, trsv.
  -- For above API's logging was called with MKSTR()
     for side, uploa and diaga parameters. MKSTR is
     needed only for macro arguments but not
     for function's arguments.
  -- Added space between function name and data type
     where it was missing. Bench expects logs in
     this format.

AMD-Internal: [CPUPL-1585]
Change-Id: Ib6ab66890e68cfa52860f869d6a1c34e78036a2d
This commit is contained in:
Dipal M Zambare
2021-06-04 12:48:54 +05:30
parent 849e1cee0a
commit 2f344f5df1
17 changed files with 63 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
aocl_dtl/aocldtl_blis.c
View File

@@ -67,7 +67,7 @@ void AOCL_DTL_log_gemm_sizes(int8 loglevel,
}
//{S, D, C, Z} m, n, k, lda, ldb, ldc, transa, transb, alpha_real, alpha_imag, beta_real, beta_imag
sprintf(buffer, "%c %ld %ld %ld %ld %ld %ld %c %c %lf %lf %lf %lf",
sprintf(buffer, " %c %ld %ld %ld %ld %ld %ld %c %c %lf %lf %lf %lf",
dt_type,
(dim_t)m, (dim_t)n, (dim_t)k,
(dim_t)lda, (dim_t)ldb, (dim_t)ldc,
@@ -120,7 +120,7 @@ void AOCL_DTL_log_trsm_sizes(int8 loglevel,
}
//{S, D, C, Z} side, uplo, transa, diaga, m, n, lda, ldb, alpha_real, alpha_imag
sprintf(buffer, "%c %c %c %c %c %ld %ld %ld %ld %lf %lf",dt_type,
sprintf(buffer, " %c %c %c %c %c %ld %ld %ld %ld %lf %lf",dt_type,
side, uploa, transa, diaga,
(dim_t)m, (dim_t)n, (dim_t)lda, (dim_t)ldb,
alpha_real, alpha_imag
@@ -231,7 +231,7 @@ void AOCL_DTL_log_hemm_sizes(int8 loglevel,
// {C, Z} { side, uploa, m, n, alpha_real, alpha_imag, lda, incx, beta_real, beta_imag, incy}
sprintf(buffer, "%c %c %c %ld %ld %lf %lf %ld %ld %lf %lf %ld",
sprintf(buffer, " %c %c %c %ld %ld %lf %lf %ld %ld %lf %lf %ld",
dt_type, side, uploa, (dim_t)m, (dim_t)n, alpha_real, alpha_imag,
(dim_t)lda, (dim_t)ldb, beta_real, beta_imag, (dim_t)ldc);
@@ -618,7 +618,7 @@ void AOCL_DTL_log_hemv_sizes ( int8 loglevel,
beta_imag = ((dcomplex*)beta)->imag;
}
// {S, D,C, Z} { uploa, m, alpha_real, alpha_imag, lda, incx, beta_real, beta_imag, incy}
sprintf(buffer, "%c %c %ld %lf %lf %ld %ld %lf %lf %ld",
sprintf(buffer, " %c %c %ld %lf %lf %ld %ld %lf %lf %ld",
dt_type, uploa, (dim_t)m, alpha_real, alpha_imag, (dim_t)lda, (dim_t)incx, beta_real, beta_imag, (dim_t)incy);
@@ -664,7 +664,7 @@ void AOCL_DTL_log_her2_sizes ( int8 loglevel,
}
// {S, D, C, Z} {uploa, m, alpha_real, alpha_imag, incx, incy}
sprintf(buffer, "%c %c %ld %lf %lf %ld %ld",
sprintf(buffer, " %c %c %ld %lf %lf %ld %ld",
dt_type, uploa, (dim_t)m, alpha_real, alpha_imag, (dim_t)incx, (dim_t)incy);
DTL_Trace(loglevel, TRACE_TYPE_LOG, function_name, function_name, line, buffer);
@@ -682,7 +682,7 @@ void AOCL_DTL_log_amax_sizes ( int8 loglevel,
{
char buffer[256];
// {S, D, C, Z} {n, incx}
sprintf(buffer, "%c %ld %ld", dt_type, (dim_t)n, (dim_t)incx);
sprintf(buffer, " %c %ld %ld", dt_type, (dim_t)n, (dim_t)incx);
DTL_Trace(loglevel, TRACE_TYPE_LOG, function_name, function_name, line, buffer);
@@ -698,7 +698,7 @@ void AOCL_DTL_log_asum_sizes ( int8 loglevel,
{
char buffer[256];
// {S, D, C, Z} {n, incx}
sprintf(buffer, "%c %ld %ld", dt_type, (dim_t)n, (dim_t)incx);
sprintf(buffer, " %c %ld %ld", dt_type, (dim_t)n, (dim_t)incx);
DTL_Trace(loglevel, TRACE_TYPE_LOG, function_name, function_name, line, buffer);
@@ -751,7 +751,7 @@ void AOCL_DTL_log_axpby_sizes ( int8 loglevel,
}
// {S, D, C, Z} {n, alpha_real, alpha_imag, incx, beta_real, beta_imag, incy}
sprintf(buffer, "%c %ld %lf %lf %ld %lf %lf %ld",
sprintf(buffer, " %c %ld %lf %lf %ld %lf %lf %ld",
dt_type, (dim_t)n, alpha_real, alpha_imag, (dim_t)incx,
beta_real, beta_imag, (dim_t)incy);
@@ -795,7 +795,7 @@ void AOCL_DTL_log_axpy_sizes ( int8 loglevel,
}
// {S, D, C, Z} {n, alpha_real, alpha_imag, incx, incy}
sprintf(buffer, "%c %ld %lf %lf %ld %ld",
sprintf(buffer, " %c %ld %lf %lf %ld %ld",
dt_type, (dim_t)n, alpha_real, alpha_imag, (dim_t)incx, (dim_t)incy);
DTL_Trace(loglevel, TRACE_TYPE_LOG, function_name, function_name, line, buffer);
@@ -813,7 +813,7 @@ void AOCL_DTL_log_copy_sizes( int8 loglevel,
{
char buffer[256];
// {S, D, C, Z} {n, incx, incy}
sprintf(buffer, "%c %ld %ld %ld", dt_type, (dim_t)n, (dim_t)incx, (dim_t)incy);
sprintf(buffer, " %c %ld %ld %ld", dt_type, (dim_t)n, (dim_t)incx, (dim_t)incy);
DTL_Trace(loglevel, TRACE_TYPE_LOG, function_name, function_name, line, buffer);

6
frame/compat/bla_hemm.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2019 - 2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2019 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -59,7 +59,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_HEMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(side), *MKSTR(uploa), *m, \
AOCL_DTL_LOG_HEMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *side, *uploa, *m, \
*n, (ftype*)alpha, *lda, *ldb, (ftype*)beta, *ldc) \
side_t blis_side; \
uplo_t blis_uploa; \
@@ -143,7 +143,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_HEMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(side), *MKSTR(uploa), *m, \
AOCL_DTL_LOG_HEMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *side, *uploa, *m, \
*n, (ftype*)alpha, *lda, *ldb, (ftype*)beta, *ldc) \
side_t blis_side; \
uplo_t blis_uploa; \

4
frame/compat/bla_hemv.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -54,7 +54,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_HEMV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa), *m, \
AOCL_DTL_LOG_HEMV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa, *m, \
(ftype*)alpha, *lda, *incx, (ftype*)beta, *incy) \
uplo_t blis_uploa; \
dim_t m0; \

4
frame/compat/bla_her.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -52,7 +52,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_HER_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa), *m, (void*)alpha, *incx, *lda);\
AOCL_DTL_LOG_HER_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa, *m, (void*)alpha, *incx, *lda);\
uplo_t blis_uploa; \
dim_t m0; \
ftype* x0; \

4
frame/compat/bla_her2.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -53,7 +53,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_HER2_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa), *m, \
AOCL_DTL_LOG_HER2_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa, *m, \
(ftype*)alpha, *incx, *incy, *lda) \
uplo_t blis_uploa; \
dim_t m0; \

4
frame/compat/bla_her2k.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2019-2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2019 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -59,7 +59,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_HER2K_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploc), *transa, *m, *k, (void*)alpha, *lda, *ldb, (void*)beta, *ldc);\
AOCL_DTL_LOG_HER2K_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploc, *transa, *m, *k, (void*)alpha, *lda, *ldb, (void*)beta, *ldc);\
uplo_t blis_uploc; \
trans_t blis_transa; \
dim_t m0, k0; \

4
frame/compat/bla_herk.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2019-2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2019 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -64,7 +64,7 @@ void PASTEF77(ch,blasname) \
inc_t rs_c, cs_c; \
\
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_HERK_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploc), *transa, *m, *k, (void*)alpha, *lda, (void*)beta, *ldc);\
AOCL_DTL_LOG_HERK_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploc, *transa, *m, *k, (void*)alpha, *lda, (void*)beta, *ldc);\
/* Initialize BLIS. */ \
bli_init_auto(); \
\

6
frame/compat/bla_symm.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2019-2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2019 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -59,7 +59,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(side), *MKSTR(uploa), *m, *n, (void*)alpha, *lda, *ldb, (void*)beta, *ldc);\
AOCL_DTL_LOG_SYMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *side, *uploa, *m, *n, (void*)alpha, *lda, *ldb, (void*)beta, *ldc);\
side_t blis_side; \
uplo_t blis_uploa; \
dim_t m0, n0; \
@@ -142,7 +142,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(side), *MKSTR(uploa), *m, *n, (void*)alpha, *lda, *ldb, (void*)beta, *ldc);\
AOCL_DTL_LOG_SYMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *side, *uploa, *m, *n, (void*)alpha, *lda, *ldb, (void*)beta, *ldc);\
side_t blis_side; \
uplo_t blis_uploa; \
dim_t m0, n0; \

4
frame/compat/bla_symv.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -54,7 +54,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYMV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa), *m, (void*)alpha, *lda, *incx, (void*)beta, *incy);\
AOCL_DTL_LOG_SYMV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa, *m, (void*)alpha, *lda, *incx, (void*)beta, *incy);\
uplo_t blis_uploa; \
dim_t m0; \
ftype* x0; \

4
frame/compat/bla_syr.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin.
Copyright (C) 2020, Advanced Micro Devices, Inc.All Rights Reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc.All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -52,7 +52,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYR_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa),\
AOCL_DTL_LOG_SYR_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa,\
*m, (void*)alpha, *incx, *lda) \
uplo_t blis_uploa; \
dim_t m0; \

4
frame/compat/bla_syr2.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin.
Copyright (C) 2020, Advanced Micro Devices, Inc.All Rights Reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc.All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -53,7 +53,7 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYR2_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa),\
AOCL_DTL_LOG_SYR2_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa,\
*m, (void*)alpha, *incx, *incy, *lda) \
uplo_t blis_uploa; \
dim_t m0; \

6
frame/compat/bla_syr2k.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin.
Copyright (C) 2019-2020, Advanced Micro Devices, Inc.All Rights Reserved.
Copyright (C) 2019 - 2021, Advanced Micro Devices, Inc.All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -150,8 +150,8 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYR2K_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploc),\
*MKSTR(transa), *m, *k, (void*)alpha, *lda, *ldb, (void*)beta, *ldc ) \
AOCL_DTL_LOG_SYR2K_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploc,\
*transa, *m, *k, (void*)alpha, *lda, *ldb, (void*)beta, *ldc ) \
uplo_t blis_uploc; \
trans_t blis_transa; \
dim_t m0, k0; \

10
frame/compat/bla_syrk.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin.
Copyright (C) 2019-2020, Advanced Micro Devices, Inc.All Rights Reserved.
Copyright (C) 2019 - 2021, Advanced Micro Devices, Inc.All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -58,8 +58,8 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYRK_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploc),\
*MKSTR(transa), *m, *k, *alpha, *lda, (void*)beta, *ldc) \
AOCL_DTL_LOG_SYRK_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploc,\
*transa, *m, *k, *alpha, *lda, (void*)beta, *ldc) \
uplo_t blis_uploc; \
trans_t blis_transa; \
dim_t m0, k0; \
@@ -143,8 +143,8 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_SYRK_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploc),\
*MKSTR(transa), *m, *k, (void*)alpha, *lda, (void*)beta, *ldc) \
AOCL_DTL_LOG_SYRK_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploc,\
*transa, *m, *k, (void*)alpha, *lda, (void*)beta, *ldc) \
uplo_t blis_uploc; \
trans_t blis_transa; \
dim_t m0, k0; \

10
frame/compat/bla_trmm.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin.
Copyright (C) 2019-2020, Advanced Micro Devices, Inc.All Rights Reserved.
Copyright (C) 2019 - 2021, Advanced Micro Devices, Inc.All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -59,8 +59,8 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_TRMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(side), \
*MKSTR(uploa), *MKSTR(transa), *MKSTR(diaga), *m, *n, *alpha, *lda, *ldb) \
AOCL_DTL_LOG_TRMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *side, \
*uploa, *transa, *diaga, *m, *n, *alpha, *lda, *ldb) \
side_t blis_side; \
uplo_t blis_uploa; \
trans_t blis_transa; \
@@ -143,8 +143,8 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_TRMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(side), *MKSTR(uploa),\
*MKSTR(transa), *MKSTR(diaga), *m, *n, (void*)alpha, *lda, *ldb) \
AOCL_DTL_LOG_TRMM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *side, *uploa,\
*transa, *diaga, *m, *n, (void*)alpha, *lda, *ldb) \
side_t blis_side; \
uplo_t blis_uploa; \
trans_t blis_transa; \

6
frame/compat/bla_trmv.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin.
Copyright (C) 2020, Advanced Micro Devices, Inc.All Rights Reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc.All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -53,8 +53,8 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_TRMV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa), \
*MKSTR(transa), *MKSTR(diaga), *m, *lda, *incx) \
AOCL_DTL_LOG_TRMV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa, \
*transa, *diaga, *m, *lda, *incx) \
uplo_t blis_uploa; \
trans_t blis_transa; \
diag_t blis_diaga; \

24
frame/compat/bla_trsm.c
View File

@@ -395,7 +395,7 @@ void dtrsm_
)
{
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_INFO)
AOCL_DTL_LOG_TRSM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(d),
AOCL_DTL_LOG_TRSM_INPUTS(AOCL_DTL_LEVEL_TRACE_1, 'd',
*side, *uploa,*transa, *diaga, *m, *n,
(void*)alpha,*lda, *ldb);
@@ -458,7 +458,7 @@ void dtrsm_
(double*)b, rs_b,
NULL
);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
return;
}
else if(bli_is_trans(blis_transa))
@@ -474,7 +474,7 @@ void dtrsm_
(double*)b, rs_b,
NULL
);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
return;
}
}
@@ -493,12 +493,12 @@ void dtrsm_
if(blis_diaga == BLIS_NONUNIT_DIAG)
{
double inva = 1.0/ *a;
for(int indx = 0; indx < m0; indx ++)
for(int indx = 0; indx < m0; indx ++)
{
b[indx] = ( inva * b[indx] );
}
}
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
return;
}
}
@@ -545,7 +545,7 @@ void dtrsm_
(double*)b, cs_b,
NULL
);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
return;
}
}
@@ -556,10 +556,10 @@ void dtrsm_
(
conja,
n0,
(double*)alpha,
(double*)alpha,
b, cs_b,
NULL,
NULL
NULL
);
if(blis_diaga == BLIS_NONUNIT_DIAG)
{
@@ -569,7 +569,7 @@ void dtrsm_
b[indx*cs_b] = (inva * b[indx*cs_b] );
}
}
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO);
return;
}
}
@@ -597,7 +597,7 @@ void dtrsm_
#ifdef BLIS_ENABLE_SMALL_MATRIX_TRSM
#ifdef BLIS_ENABLE_TRSM_PREINVERSION
/* Irrespective of num threads single thread bli_dtrsm_small
/* Irrespective of num threads single thread bli_dtrsm_small
* is performing better than other implementations for [m,n]<=256 */
/* ToDo: This condition will be tunned for single thread */
if(m0 <=256 && n0<=256)
@@ -633,12 +633,12 @@ void dtrsm_
NULL
);
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO)
AOCL_DTL_TRACE_EXIT(AOCL_DTL_LEVEL_INFO)
/* Finalize BLIS. */
bli_finalize_auto();
}
GENTFUNC( float, s, trsm, trsm )
GENTFUNC( float, s, trsm, trsm )
INSERT_GENTFUNC_BLAS_CZ( trsm, trsm )
#else
INSERT_GENTFUNC_BLAS( trsm, trsm )

6
frame/compat/bla_trsv.c
View File

@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin.
Copyright (C) 2020, Advanced Micro Devices, Inc.All Rights Reserved.
Copyright (C) 2020 - 2021, Advanced Micro Devices, Inc.All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -53,8 +53,8 @@ void PASTEF77(ch,blasname) \
) \
{ \
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_1) \
AOCL_DTL_LOG_TRSV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *MKSTR(uploa), \
*MKSTR(transa), *MKSTR(diaga), *m, *lda, *incx) \
AOCL_DTL_LOG_TRSV_INPUTS(AOCL_DTL_LEVEL_TRACE_1, *MKSTR(ch), *uploa, \
*transa, *diaga, *m, *lda, *incx) \
uplo_t blis_uploa; \
trans_t blis_transa; \
diag_t blis_diaga; \