GEMV support for S8S8S32O32 Symmetric Quantization

Introduced support for GEMV operations with group-level symmetric quantization for the S8S8S32032 API.

Framework Changes:
- Added macro definitions and function prototypes for GEMV with symmetric quantization in lpgemm_5loop_interface_apis.h and lpgemm_kernels.h.
  - LPGEMV_M_EQ1_KERN2 for the lpgemv_m_one_s8s8s32os32_sym_quant kernel, and
  - LPGEMV_N_EQ1_KERN2 for the lpgemv_n_one_s8s8s32os32_sym_quant kernel.
- Implemented the main GEMV framework for symmetric quantization in lpgemm_s8s8s32_sym_quant.c.

Kernel Changes:
- lpgemv_m_one_s8s8s32os32_sym_quant for handling the case where M = 1 and implemented in lpgemv_m_kernel_s8_grp_amd512vnni.c.
- lpgemv_n_one_s8s8s32os32_sym_quant for handling the case where N = 1 and implemented in lpgemv_n_kernel_s8_grp_amd512vnni.c.
- Updated the buffer reordering logic for group quantization for N=1 cases in aocl_gemm_s8s8s32os32_utils.c.

Notes
- Ensure that group_size is a factor of both K (and KC when K > KC).
- The B matrix must be provided in reordered format (mtag_b == REORDERED).

AMD-Internal: [SWLCSG-3604]
This commit is contained in:
Sharma, Arnav
2025-08-14 13:41:25 +05:30
committed by GitHub
parent 3a14417ce1
commit 76c4872718
6 changed files with 3280 additions and 142 deletions

View File

@@ -297,4 +297,33 @@ void lpgemv_rowvar_avx2_ ## LP_SFX \
LPGEMV_AVX2(bfloat16, bfloat16, float, bf16bf16f32of32);
#define LPGEMV2(A_type, B_type, C_type, LP_SFX) \
void lpgemv_rowvar_ ## LP_SFX \
( \
const dim_t m, \
const dim_t n, \
const dim_t k, \
const A_type *a, \
const dim_t rs_a, \
const dim_t cs_a, \
const AOCL_MEMORY_TAG mtag_a, \
const B_type *b, \
const dim_t rs_b, \
const dim_t cs_b, \
const AOCL_MEMORY_TAG mtag_b, \
float *c, \
const dim_t rs_c, \
const dim_t cs_c, \
const C_type alpha, \
const C_type beta, \
rntm_t *rntm, \
lpgemm_thrinfo_t *thread, \
lpgemm_cntx_t *lcntx, \
lpgemm_group_post_op *grp_post_op_list, \
lpgemm_post_op *post_op_list, \
AOCL_STORAGE_TYPE c_downscale \
) \
LPGEMV2(int8_t,int8_t,int32_t,s8s8s32os32_sym_quant);
#endif // LPGEMM_5LOOP_INTF_H