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Zen3 support, disabled IR, JR loop parallelization

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AMD-Internal: [CPUPL-1013]

Change-Id: I859152d63d1a56519c508dfa19587f25123e08b4
This commit is contained in:
Dipal M Zambare
2020-07-24 19:57:38 +05:30
parent 23a2073c39
commit 9d7978eedd
4 changed files with 9 additions and 8 deletions
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1
config/amd64_legacy/make_defs.mk
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@@ -5,6 +5,7 @@
# libraries.
#
# Copyright (C) 2014, The University of Texas at Austin
# Copyright (C) 2020, Advanced Micro Devices, Inc
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are

5
config/zen3/bli_family_zen3.h
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@@ -40,10 +40,9 @@
// Setting these macros to 1 will force JR and IR inner loops
// to be not paralleized.
//
// will be enabled later if required after block size tuning.
//#define BLIS_THREAD_MAX_IR 1
//#define BLIS_THREAD_MAX_JR 1
#define BLIS_THREAD_MAX_IR 1
#define BLIS_THREAD_MAX_JR 1
#define BLIS_ENABLE_SMALL_MATRIX

9
config_registry
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@@ -8,10 +8,11 @@
#
# Processor families.
x86_64: intel64 amd64 and64_legacy
intel64: skx knl haswell sandybridge penryn generic
amd64_legacy: excavator steamroller piledriver bulldozer generic
amd64: zen3 zen2 zen generic
x86_64: intel64 amd64 amd64_legacy
intel64: skx knl haswell sandybridge penryn generic
amd64_legacy: excavator steamroller piledriver bulldozer generic
amd64: zen3 zen2 zen generic
# NOTE: ARM families will remain disabled until runtime hardware detection
# logic is added to BLIS.
#arm64: cortexa57 generic

2
frame/include/bli_type_defs.h
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@@ -1017,7 +1017,7 @@ typedef enum
} arch_t;
#define BLIS_NUM_ARCHS 22
#define BLIS_NUM_ARCHS (BLIS_ARCH_GENERIC + 1)
//