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Armv8-A GEMMSUP-RD 6x8n
This commit is contained in:
RuQing Xu
447
kernels/armv8a/3/sup/bli_gemmsup_rd_armv8a_asm_d6x8n.c
Normal file
447
kernels/armv8a/3/sup/bli_gemmsup_rd_armv8a_asm_d6x8n.c
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@@ -0,0 +1,447 @@
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/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2021, The University of Tokyo
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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||||
- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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#include "assert.h"
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GEMMSUP_KER_PROT( double, d, gemmsup_r_armv8a_ref2 )
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// Label locality & misc.
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#include "../armv8a_asm_utils.h"
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#define DGEMM_1X4X2_NKER_SUBLOOP(C0,C1,C2,C3,A,B0,B1,B2,B3) \
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" fmla v"#C0".2d, v"#A".2d, v"#B0".2d \n\t" \
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" fmla v"#C1".2d, v"#A".2d, v"#B1".2d \n\t" \
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" fmla v"#C2".2d, v"#A".2d, v"#B2".2d \n\t" \
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" fmla v"#C3".2d, v"#A".2d, v"#B3".2d \n\t" \
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#define DGEMM_6X4X2_K_MKER_LOOP_PLAIN(C00,C01,C02,C03,C10,C11,C12,C13,C20,C21,C22,C23,C30,C31,C32,C33,C40,C41,C42,C43,C50,C51,C52,C53,A0,A1,A2,A3,B0,B1,B2,B3,AADDR,AELEMADDR,AELEMST,LOADNEXT) \
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/* Always load before forwarding to the next line. */ \
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DGEMM_1X4X2_NKER_SUBLOOP(C00,C01,C02,C03,A0,B0,B1,B2,B3) \
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DGEMM_LOAD1V_K_load(A0,AELEMADDR,AELEMST) \
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DGEMM_1X4X2_NKER_SUBLOOP(C10,C11,C12,C13,A1,B0,B1,B2,B3) \
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DGEMM_LOAD1V_K_load(A1,AELEMADDR,AELEMST) \
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" add "#AADDR", "#AADDR", #16 \n\t" \
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" mov "#AELEMADDR", "#AADDR" \n\t" \
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DGEMM_1X4X2_NKER_SUBLOOP(C20,C21,C22,C23,A2,B0,B1,B2,B3) \
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DGEMM_LOAD1V_K_load(A2,AELEMADDR,AELEMST) \
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DGEMM_1X4X2_NKER_SUBLOOP(C30,C31,C32,C33,A3,B0,B1,B2,B3) \
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DGEMM_LOAD1V_K_load(A3,AELEMADDR,AELEMST) \
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\
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DGEMM_1X4X2_NKER_SUBLOOP(C40,C41,C42,C43,A0,B0,B1,B2,B3) \
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DGEMM_LOAD1V_K_ ##LOADNEXT (A0,AELEMADDR,AELEMST) \
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DGEMM_1X4X2_NKER_SUBLOOP(C50,C51,C52,C53,A1,B0,B1,B2,B3) \
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DGEMM_LOAD1V_K_ ##LOADNEXT (A1,AELEMADDR,AELEMST)
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#define DGEMM_LOAD1V_K_noload(V,ELEMADDR,ELEMST)
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#define DGEMM_LOAD1V_K_load(V,ELEMADDR,ELEMST) \
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" ldr q"#V", [ "#ELEMADDR" ] \n\t" \
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" add "#ELEMADDR", "#ELEMADDR", "#ELEMST" \n\t"
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// For row-storage of C.
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#define DLOADC_2V_R_FWD(C0,C1,CADDR,CSHIFT,RSC) \
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DLOAD2V(C0,C1,CADDR,CSHIFT) \
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" add "#CADDR", "#CADDR", "#RSC" \n\t"
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#define DSTOREC_2V_R_FWD(C0,C1,CADDR,CSHIFT,RSC) \
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DSTORE2V(C0,C1,CADDR,CSHIFT) \
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" add "#CADDR", "#CADDR", "#RSC" \n\t"
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// For column-storage of C.
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#define DLOADC_3V_C_FWD(C0,C1,C2,CADDR,CSHIFT,CSC) \
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DLOAD2V(C0,C1,CADDR,CSHIFT) \
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DLOAD1V(C2,CADDR,CSHIFT+32) \
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" add "#CADDR", "#CADDR", "#CSC" \n\t"
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#define DSTOREC_3V_C_FWD(C0,C1,C2,CADDR,CSHIFT,CSC) \
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DSTORE2V(C0,C1,CADDR,CSHIFT) \
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DSTORE1V(C2,CADDR,CSHIFT+32) \
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" add "#CADDR", "#CADDR", "#CSC" \n\t"
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#define DSCALE12V(V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,A,IDX) \
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DSCALE4V(V0,V1,V2,V3,A,IDX) \
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DSCALE4V(V4,V5,V6,V7,A,IDX) \
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DSCALE4V(V8,V9,V10,V11,A,IDX)
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#define DSCALEA12V(D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,A,IDX) \
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DSCALEA4V(D0,D1,D2,D3,S0,S1,S2,S3,A,IDX) \
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DSCALEA4V(D4,D5,D6,D7,S4,S5,S6,S7,A,IDX) \
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DSCALEA4V(D8,D9,D10,D11,S8,S9,S10,S11,A,IDX)
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#define DPRFMC_FWD(CADDR,DLONGC) \
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" prfm PLDL1KEEP, ["#CADDR"] \n\t" \
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" add "#CADDR", "#CADDR", "#DLONGC" \n\t"
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void bli_dgemmsup_rd_armv8a_asm_6x8n
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(
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conj_t conja,
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conj_t conjb,
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dim_t m0,
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dim_t n0,
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dim_t k0,
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double* restrict alpha,
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double* restrict a, inc_t rs_a0, inc_t cs_a0,
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double* restrict b, inc_t rs_b0, inc_t cs_b0,
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double* restrict beta,
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double* restrict c, inc_t rs_c0, inc_t cs_c0,
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auxinfo_t* restrict data,
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cntx_t* restrict cntx
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)
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{
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if ( m0 != 6 )
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{
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bli_dgemmsup_r_armv8a_ref2
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(
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conja, conjb, m0, n0, k0,
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alpha, a, rs_a0, cs_a0, b, rs_b0, cs_b0,
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beta, c, rs_c0, cs_c0, data, cntx
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);
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return;
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}
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// LLVM has very bad routing ability for inline asm.
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// Limit number of registers in case of Clang compilation.
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#ifndef __clang__
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void* a_next = bli_auxinfo_next_a( data );
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void* b_next = bli_auxinfo_next_b( data );
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#endif
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// Typecast local copies of integers in case dim_t and inc_t are a
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// different size than is expected by load instructions.
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uint64_t k_mker = k0 / 4;
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uint64_t k_left = k0 % 4;
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uint64_t n_iter = n0 / 4;
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uint64_t n_left = n0 % 4;
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uint64_t rs_a = rs_a0;
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uint64_t cs_b = cs_b0;
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uint64_t rs_c = rs_c0;
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uint64_t cs_c = cs_c0;
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assert( cs_a0 == 1 );
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assert( rs_b0 == 1 );
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if ( n_iter == 0 ) goto consider_edge_cases;
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__asm__ volatile
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(
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" ldr x10, %[b] \n\t"
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" ldr x13, %[c] \n\t"
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" ldr x12, %[n_iter] \n\t"
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" ldr x2, %[rs_a] \n\t" // Row-skip of A.
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" ldr x3, %[cs_b] \n\t" // Column-skip of B.
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" \n\t"
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" ldr x6, %[rs_c] \n\t" // Row-skip of C.
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" ldr x7, %[cs_c] \n\t" // Column-skip of C.
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" \n\t"
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" \n\t" // Multiply some address skips by sizeof(double).
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" lsl x2, x2, #3 \n\t" // rs_a
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" lsl x3, x3, #3 \n\t" // cs_b
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" lsl x6, x6, #3 \n\t" // rs_c
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" lsl x7, x7, #3 \n\t" // cs_c
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" \n\t"
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" mov x1, x5 \n\t"
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" cmp x7, #8 \n\t" // Prefetch column-strided C.
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BEQ(C_PREFETCH_COLS)
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DPRFMC_FWD(x1,x6)
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DPRFMC_FWD(x1,x6)
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DPRFMC_FWD(x1,x6)
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DPRFMC_FWD(x1,x6)
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DPRFMC_FWD(x1,x6)
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DPRFMC_FWD(x1,x6)
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BRANCH(C_PREFETCH_END)
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LABEL(C_PREFETCH_COLS)
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DPRFMC_FWD(x1,x7)
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DPRFMC_FWD(x1,x7)
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DPRFMC_FWD(x1,x7)
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DPRFMC_FWD(x1,x7)
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DPRFMC_FWD(x1,x7)
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DPRFMC_FWD(x1,x7)
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DPRFMC_FWD(x1,x7)
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DPRFMC_FWD(x1,x7)
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LABEL(C_PREFETCH_END)
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//
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// Millikernel.
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LABEL(MILLIKER_MLOOP)
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" \n\t"
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" mov x1, x10 \n\t" // Parameters to be reloaded
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" mov x5, x13 \n\t" // within each millikernel loop.
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" ldr x0, %[a] \n\t"
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" ldr x4, %[k_mker] \n\t"
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" ldr x8, %[k_left] \n\t"
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" \n\t"
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// Storage scheme:
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// V[ 0:23] <- C
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// V[24:27] <- A
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// V[28:31] <- B
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// Under this scheme, the following is defined:
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#define DGEMM_6X4X2_K_MKER_LOOP_PLAIN_LOC(A0,A1,A2,A3,B0,B1,B2,B3,AADDR,AELEMADDR,AELEMST,LOADNEXT) \
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DGEMM_6X4X2_K_MKER_LOOP_PLAIN(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,A0,A1,A2,A3,B0,B1,B2,B3,AADDR,AELEMADDR,AELEMST,LOADNEXT)
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// Load from memory.
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LABEL(LOAD_ABC)
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" \n\t" // No-microkernel early return is a must
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" cmp x4, #0 \n\t" // to avoid out-of-boundary read.
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BEQ(CLEAR_CCOLS)
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" \n\t"
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" mov x11, x1 \n\t" // Load B.
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" ldr q28, [x11] \n\t"
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" add x11, x11, x3 \n\t"
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" ldr q29, [x11] \n\t"
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" add x11, x11, x3 \n\t"
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" ldr q30, [x11] \n\t"
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" add x11, x11, x3 \n\t"
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" ldr q31, [x11] \n\t"
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// " add x11, x11, x3 \n\t"
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" add x1, x1, #16 \n\t"
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" \n\t"
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" mov x14, x0 \n\t" // Load A.
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" ldr q24, [x14] \n\t"
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" add x14, x14, x2 \n\t"
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" ldr q25, [x14] \n\t"
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" add x14, x14, x2 \n\t"
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" ldr q26, [x14] \n\t"
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" add x14, x14, x2 \n\t"
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" ldr q27, [x14] \n\t"
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" add x14, x14, x2 \n\t"
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LABEL(CLEAR_CCOLS)
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CLEAR8V(0,1,2,3,4,5,6,7)
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CLEAR8V(8,9,10,11,12,13,14,15)
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CLEAR8V(16,17,18,19,20,21,22,23)
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// No-microkernel early return, once again.
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BEQ(K_LEFT_LOOP)
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//
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// Microkernel is defined here as:
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#define DGEMM_6X4X2_K_MKER_LOOP_PLAIN_LOC_FWD(A0,A1,A2,A3,B0,B1,B2,B3) \
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DGEMM_6X4X2_K_MKER_LOOP_PLAIN_LOC(A0,A1,A2,A3,B0,B1,B2,B3,x0,x14,x2,load) \
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/* A already loaded and forwarded. Process B only. */ \
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"mov x11, x1 \n\t" \
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"ldr q28, [x11] \n\t" \
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"add x11, x11, x3 \n\t" \
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"ldr q29, [x11] \n\t" \
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"add x11, x11, x3 \n\t" \
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"ldr q30, [x11] \n\t" \
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"add x11, x11, x3 \n\t" \
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"ldr q31, [x11] \n\t" \
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/*"add x11, x11, x3 \n\t"*/ \
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"add x1, x1, #16 \n\t"
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// Start microkernel loop.
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LABEL(K_MKER_LOOP)
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DGEMM_6X4X2_K_MKER_LOOP_PLAIN_LOC_FWD(24,25,26,27,28,29,30,31)
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" \n\t" // Decrease counter before final replica.
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" subs x4, x4, #1 \n\t" // Branch early to avoid reading excess mem.
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BEQ(FIN_MKER_LOOP)
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DGEMM_6X4X2_K_MKER_LOOP_PLAIN_LOC_FWD(26,27,24,25,28,29,30,31)
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BRANCH(K_MKER_LOOP)
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//
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// Final microkernel loop.
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LABEL(FIN_MKER_LOOP)
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DGEMM_6X4X2_K_MKER_LOOP_PLAIN_LOC(26,27,24,25,28,29,30,31,x0,x14,x2,noload)
|
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//
|
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// If major kernel is executed,
|
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// an additional depth-summation is required.
|
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" faddp.2d v0, v0, v1 \n\t" // Line 0.
|
||||
" faddp.2d v1, v2, v3 \n\t"
|
||||
" faddp.2d v2, v4, v5 \n\t" // Line 1.
|
||||
" faddp.2d v3, v6, v7 \n\t"
|
||||
" faddp.2d v4, v8, v9 \n\t" // Line 2.
|
||||
" faddp.2d v5, v10, v11 \n\t"
|
||||
" faddp.2d v6, v12, v13 \n\t" // Line 3.
|
||||
" faddp.2d v7, v14, v15 \n\t"
|
||||
" faddp.2d v8, v16, v17 \n\t" // Line 4.
|
||||
" faddp.2d v9, v18, v19 \n\t"
|
||||
" faddp.2d v10, v20, v21 \n\t" // Line 5.
|
||||
" faddp.2d v11, v22, v23 \n\t"
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||||
" \n\t"
|
||||
// Loops left behind microkernels.
|
||||
LABEL(K_LEFT_LOOP)
|
||||
" cmp x8, #0 \n\t" // End of exec.
|
||||
BEQ(WRITE_MEM_PREP)
|
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" mov x11, x1 \n\t" // Load B row.
|
||||
" ld1 {v28.d}[0], [x11], x3 \n\t"
|
||||
" ld1 {v28.d}[1], [x11], x3 \n\t"
|
||||
" ld1 {v29.d}[0], [x11], x3 \n\t"
|
||||
" ld1 {v29.d}[1], [x11], x3 \n\t"
|
||||
" add x1, x1, #8 \n\t"
|
||||
" mov x14, x0 \n\t" // Load A column.
|
||||
" ld1 {v24.d}[0], [x14], x2 \n\t"
|
||||
" ld1 {v24.d}[1], [x14], x2 \n\t"
|
||||
" ld1 {v25.d}[0], [x14], x2 \n\t"
|
||||
" ld1 {v25.d}[1], [x14], x2 \n\t"
|
||||
" ld1 {v26.d}[0], [x14], x2 \n\t"
|
||||
" ld1 {v26.d}[1], [x14], x2 \n\t"
|
||||
" add x0, x0, #8 \n\t"
|
||||
" fmla v0.2d, v28.2d, v24.d[0] \n\t"
|
||||
" fmla v1.2d, v29.2d, v24.d[0] \n\t"
|
||||
" fmla v2.2d, v28.2d, v24.d[1] \n\t"
|
||||
" fmla v3.2d, v29.2d, v24.d[1] \n\t"
|
||||
" fmla v4.2d, v28.2d, v25.d[0] \n\t"
|
||||
" fmla v5.2d, v29.2d, v25.d[0] \n\t"
|
||||
" fmla v6.2d, v28.2d, v25.d[1] \n\t"
|
||||
" fmla v7.2d, v29.2d, v25.d[1] \n\t"
|
||||
" fmla v8.2d, v28.2d, v26.d[0] \n\t"
|
||||
" fmla v9.2d, v29.2d, v26.d[0] \n\t"
|
||||
" fmla v10.2d, v28.2d, v26.d[1] \n\t"
|
||||
" fmla v11.2d, v29.2d, v26.d[1] \n\t"
|
||||
" sub x8, x8, #1 \n\t"
|
||||
BRANCH(K_LEFT_LOOP)
|
||||
//
|
||||
// Scale and write to memory.
|
||||
LABEL(WRITE_MEM_PREP)
|
||||
" ldr x4, %[alpha] \n\t" // Load alpha & beta (address).
|
||||
" ldr x8, %[beta] \n\t"
|
||||
" ld1r {v30.2d}, [x4] \n\t" // Load alpha & beta (value).
|
||||
" ld1r {v31.2d}, [x8] \n\t"
|
||||
" \n\t"
|
||||
" mov x1, x5 \n\t" // C address for loading.
|
||||
" \n\t" // C address for storing is x5 itself.
|
||||
" cmp x7, #8 \n\t" // Check for column-storage.
|
||||
BNE(WRITE_MEM_C)
|
||||
//
|
||||
// C storage in rows.
|
||||
LABEL(WRITE_MEM_R)
|
||||
DLOADC_2V_R_FWD(12,13,x1,0,x6)
|
||||
DLOADC_2V_R_FWD(14,15,x1,0,x6)
|
||||
DLOADC_2V_R_FWD(16,17,x1,0,x6)
|
||||
DLOADC_2V_R_FWD(18,19,x1,0,x6)
|
||||
DLOADC_2V_R_FWD(20,21,x1,0,x6)
|
||||
DLOADC_2V_R_FWD(22,23,x1,0,x6)
|
||||
DSCALE12V(12,13,14,15,16,17,18,19,20,21,22,23,31,0)
|
||||
DSCALEA12V(12,13,14,15,16,17,18,19,20,21,22,23,0,1,2,3,4,5,6,7,8,9,10,11,30,0)
|
||||
#ifndef __clang__
|
||||
" cmp x12, #1 \n\t"
|
||||
BRANCH(PRFM_END_R)
|
||||
" prfm PLDL1KEEP, [%[a_next], #16*0] \n\t"
|
||||
" prfm PLDL1KEEP, [%[a_next], #16*1] \n\t"
|
||||
" prfm PLDL1STRM, [%[b_next], #16*0] \n\t"
|
||||
" prfm PLDL1STRM, [%[b_next], #16*1] \n\t"
|
||||
LABEL(PRFM_END_R)
|
||||
#endif
|
||||
DSTOREC_2V_R_FWD(12,13,x5,0,x6)
|
||||
DSTOREC_2V_R_FWD(14,15,x5,0,x6)
|
||||
DSTOREC_2V_R_FWD(16,17,x5,0,x6)
|
||||
DSTOREC_2V_R_FWD(18,19,x5,0,x6)
|
||||
DSTOREC_2V_R_FWD(20,21,x5,0,x6)
|
||||
DSTOREC_2V_R_FWD(22,23,x5,0,x6)
|
||||
BRANCH(END_WRITE_MEM)
|
||||
//
|
||||
// C storage in columns.
|
||||
LABEL(WRITE_MEM_C)
|
||||
" trn1 v12.2d, v0.2d, v2.2d \n\t"
|
||||
" trn1 v13.2d, v4.2d, v6.2d \n\t"
|
||||
" trn1 v14.2d, v8.2d, v10.2d \n\t"
|
||||
" trn2 v15.2d, v0.2d, v2.2d \n\t"
|
||||
" trn2 v16.2d, v4.2d, v6.2d \n\t"
|
||||
" trn2 v17.2d, v8.2d, v10.2d \n\t"
|
||||
" trn1 v18.2d, v1.2d, v3.2d \n\t"
|
||||
" trn1 v19.2d, v5.2d, v7.2d \n\t"
|
||||
" trn1 v20.2d, v9.2d, v11.2d \n\t"
|
||||
" trn2 v21.2d, v1.2d, v3.2d \n\t"
|
||||
" trn2 v22.2d, v5.2d, v7.2d \n\t"
|
||||
" trn2 v23.2d, v9.2d, v11.2d \n\t"
|
||||
DLOADC_3V_C_FWD(0,1,2,x1,0,x7)
|
||||
DLOADC_3V_C_FWD(3,4,5,x1,0,x7)
|
||||
DLOADC_3V_C_FWD(6,7,8,x1,0,x7)
|
||||
DLOADC_3V_C_FWD(9,10,11,x1,0,x7)
|
||||
DSCALE12V(0,1,2,3,4,5,6,7,8,9,10,11,31,0)
|
||||
DSCALEA12V(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,30,0)
|
||||
#ifndef __clang__
|
||||
" cmp x12, #1 \n\t"
|
||||
BRANCH(PRFM_END_C)
|
||||
" prfm PLDL1KEEP, [%[a_next], #16*0] \n\t"
|
||||
" prfm PLDL1KEEP, [%[a_next], #16*1] \n\t"
|
||||
" prfm PLDL1STRM, [%[b_next], #16*0] \n\t"
|
||||
" prfm PLDL1STRM, [%[b_next], #16*1] \n\t"
|
||||
LABEL(PRFM_END_C)
|
||||
#endif
|
||||
DSTOREC_3V_C_FWD(0,1,2,x5,0,x7)
|
||||
DSTOREC_3V_C_FWD(3,4,5,x5,0,x7)
|
||||
DSTOREC_3V_C_FWD(6,7,8,x5,0,x7)
|
||||
DSTOREC_3V_C_FWD(9,10,11,x5,0,x7)
|
||||
//
|
||||
// End of this microkernel.
|
||||
LABEL(END_WRITE_MEM)
|
||||
" \n\t"
|
||||
" subs x12, x12, #1 \n\t"
|
||||
BEQ(END_EXEC)
|
||||
" \n\t"
|
||||
" mov x8, #4 \n\t"
|
||||
" madd x13, x7, x8, x13 \n\t" // Forward C's base address to the next logic panel.
|
||||
" madd x10, x3, x8, x10 \n\t" // Forward B's base address to the next logic panel.
|
||||
BRANCH(MILLIKER_MLOOP)
|
||||
//
|
||||
// End of execution.
|
||||
LABEL(END_EXEC)
|
||||
:
|
||||
: [a] "m" (a),
|
||||
[b] "m" (b),
|
||||
[c] "m" (c),
|
||||
[rs_a] "m" (rs_a),
|
||||
[cs_b] "m" (cs_b),
|
||||
[rs_c] "m" (rs_c),
|
||||
[cs_c] "m" (cs_c),
|
||||
// In Clang, even "m"-passed parameter takes 1 register.
|
||||
// Have to disable prefetching to pass compilation.
|
||||
#ifndef __clang__
|
||||
[a_next] "r" (a_next),
|
||||
[b_next] "r" (b_next),
|
||||
#endif
|
||||
[n_iter] "m" (n_iter),
|
||||
[k_mker] "m" (k_mker),
|
||||
[k_left] "m" (k_left),
|
||||
[alpha] "m" (alpha),
|
||||
[beta] "m" (beta)
|
||||
: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
|
||||
"x8", "x9", "x10","x11","x12","x13","x14",
|
||||
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
|
||||
"v8", "v9", "v10","v11","v12","v13","v14","v15",
|
||||
"v16","v17","v18","v19","v20","v21","v22","v23",
|
||||
"v24","v25","v26","v27","v28","v29","v30","v31"
|
||||
);
|
||||
|
||||
consider_edge_cases:
|
||||
// TODO: Implement optimized kernel for this.
|
||||
//
|
||||
// Forward address.
|
||||
b = b + n_iter * 4;
|
||||
c = c + n_iter * 4 * cs_c;
|
||||
if ( n_left )
|
||||
{
|
||||
bli_dgemmsup_r_armv8a_ref2
|
||||
(
|
||||
conja, conjb, 6, n_left, k0,
|
||||
alpha, a, rs_a0, cs_a0, b, rs_b0, cs_b0,
|
||||
beta, c, rs_c0, cs_c0, data, cntx
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -43,6 +43,7 @@ GEMM_UKR_PROT( double, d, gemm_armv8a_asm_6x8r )
|
||||
GEMM_UKR_PROT( double, d, gemm_armv8a_asm_8x4 )
|
||||
GEMM_UKR_PROT( double, d, gemm_armv8a_asm_4x4 )
|
||||
|
||||
GEMMSUP_KER_PROT( double, d, gemmsup_rd_armv8a_asm_6x8n )
|
||||
GEMMSUP_KER_PROT( double, d, gemmsup_rv_armv8a_asm_6x8n )
|
||||
GEMMSUP_KER_PROT( double, d, gemmsup_rv_armv8a_asm_6x8m )
|
||||
GEMMSUP_KER_PROT( double, d, gemmsup_rv_armv8a_asm_4x8n )
|
||||
|
||||
Reference in New Issue
Block a user