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Added functionality support for dzgemm
AMD-Internal: [SWLCSG-1012] Change-Id: I2eac3131d2dcd534f84491289cbd3fe7fb7de3da
This commit is contained in:
committed by
Dipal M Zambare
parent
b90420627a
commit
c11fd5a8f6
@@ -5,7 +5,7 @@
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2018 - 2019, Advanced Micro Devices, Inc.
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Copyright (C) 2018 - 2022, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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@@ -159,7 +159,8 @@ void bli_packm_blk_var1
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// Treatment of kappa (ie: packing during scaling) depends on
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// whether we are executing an induced method.
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if ( bli_is_nat_packed( schema ) )
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// For dzgemm, scale alpha during packing.
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if ( bli_is_nat_packed( schema ) && cntl && bli_cntl_family(cntl) != BLIS_GEMM_MD)
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{
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// This branch is for native execution, where we assume that
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// the micro-kernel will always apply the alpha scalar of the
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@@ -5,6 +5,7 @@
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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@@ -323,8 +324,10 @@ void bli_gemm_basic_check
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// When mixing datatypes, make sure that alpha does not have a non-zero
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// imaginary component.
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if ( bli_obj_dt( c ) != bli_obj_dt( a ) ||
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bli_obj_dt( c ) != bli_obj_dt( b ) ||
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// To support dzgemm, we continue execution when datatypes of C and A
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// do not match instead of aborting with an error message.
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// Non-zero imaginary component of alpha is handled while packing B.
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if ( bli_obj_dt( c ) != bli_obj_dt( b ) ||
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bli_obj_comp_prec( c ) != bli_obj_prec( c ) )
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if ( !bli_obj_imag_is_zero( alpha ) )
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{
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@@ -5,6 +5,7 @@
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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@@ -90,9 +91,14 @@ void bli_gemm_packb
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)
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{
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AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_5);
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obj_t b_pack;
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// BY setting family id to BLIS_GEMM_MD, we indicate packing kernels
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// to scale alpha while packing.
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if(bli_obj_dt(c) != bli_obj_dt(a))
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bli_cntl_set_family(BLIS_GEMM_MD, cntl);
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// Pack matrix B according to the control tree node.
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bli_l3_packm
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(
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@@ -103,6 +109,10 @@ void bli_gemm_packb
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cntl,
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thread
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);
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// Once packing of B matrix is done, fall back to GEMM execution.
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if(bli_obj_dt(c) != bli_obj_dt(a))
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bli_cntl_set_family(BLIS_GEMM, cntl);
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// Proceed with execution using packed matrix B.
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bli_gemm_int
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@@ -302,9 +302,7 @@ void PASTEF77(ch,blasname) \
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#ifdef BLIS_ENABLE_BLAS
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INSERT_GENTFUNC_BLAS( gemm,gemm )
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// Observed a regression in dgemm with this function addition.
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// Disabling temporarily.
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#if 0
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#if 1
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void dzgemm_
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(
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const f77_char* transa,
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@@ -381,7 +379,7 @@ void dzgemm_
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bli_obj_init_finish_1x1( dt, (dcomplex*)alpha, &alphao );
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bli_obj_init_finish_1x1( dt, (dcomplex*)beta, &betao );
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bli_obj_init_finish( dt_a, m0_a, n0_a, (dcomplex*)a, rs_a, cs_a, &ao );
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bli_obj_init_finish( dt_a, m0_a, n0_a, (double*)a, rs_a, cs_a, &ao );
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bli_obj_init_finish( dt, m0_b, n0_b, (dcomplex*)b, rs_b, cs_b, &bo );
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bli_obj_init_finish( dt, m0, n0, (dcomplex*)c, rs_c, cs_c, &co );
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@@ -5,6 +5,7 @@
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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@@ -54,8 +55,7 @@ BLIS_EXPORT_BLAS void PASTEF77(ch,blasname) \
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);
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#ifdef BLIS_ENABLE_BLAS
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// Disabling temporarily
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#if 0
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#if 1
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BLIS_EXPORT_BLAS void dzgemm_
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(
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const f77_char* transa, \
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@@ -6,7 +6,7 @@
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2016, Hewlett Packard Enterprise Development LP
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Copyright (C) 2021, Advanced Micro Devices, Inc. All rights reserved.
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Copyright (C) 2021 - 22, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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@@ -931,10 +931,11 @@ typedef enum
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BLIS_TRMM,
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BLIS_TRSM,
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BLIS_GEMMT,
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BLIS_GEMM_MD,
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BLIS_NOID
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} opid_t;
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#define BLIS_NUM_LEVEL3_OPS 11
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#define BLIS_NUM_LEVEL3_OPS 12
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// -- Blocksize ID type --
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@@ -5,7 +5,7 @@
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2019-2021, Advanced Micro Devices, Inc. All rights reserved.
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Copyright (C) 2019-2022, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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@@ -382,8 +382,7 @@ int main( int argc, char** argv )
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cp, ldc
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);
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#else
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//Disabled dzgemm function temporarily.
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#if 0
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#if 1
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if( bli_is_double( dt_a ) )
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{
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dzgemm_(
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@@ -401,7 +400,6 @@ int main( int argc, char** argv )
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}
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else
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{
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#else
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zgemm_( &f77_transa,
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&f77_transb,
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&mm,
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@@ -412,7 +410,7 @@ int main( int argc, char** argv )
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bp, (f77_int*)&ldb,
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betap,
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cp, (f77_int*)&ldc );
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// }
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}
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#endif
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#endif
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}
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