Added functionality support for dzgemm

AMD-Internal: [SWLCSG-1012]
Change-Id: I2eac3131d2dcd534f84491289cbd3fe7fb7de3da
This commit is contained in:
Meghana Vankadari
2022-01-19 09:16:41 +05:30
committed by Dipal M Zambare
parent b90420627a
commit c11fd5a8f6
7 changed files with 29 additions and 18 deletions

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@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2018 - 2019, Advanced Micro Devices, Inc.
Copyright (C) 2018 - 2022, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -159,7 +159,8 @@ void bli_packm_blk_var1
// Treatment of kappa (ie: packing during scaling) depends on
// whether we are executing an induced method.
if ( bli_is_nat_packed( schema ) )
// For dzgemm, scale alpha during packing.
if ( bli_is_nat_packed( schema ) && cntl && bli_cntl_family(cntl) != BLIS_GEMM_MD)
{
// This branch is for native execution, where we assume that
// the micro-kernel will always apply the alpha scalar of the

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@@ -5,6 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -323,8 +324,10 @@ void bli_gemm_basic_check
// When mixing datatypes, make sure that alpha does not have a non-zero
// imaginary component.
if ( bli_obj_dt( c ) != bli_obj_dt( a ) ||
bli_obj_dt( c ) != bli_obj_dt( b ) ||
// To support dzgemm, we continue execution when datatypes of C and A
// do not match instead of aborting with an error message.
// Non-zero imaginary component of alpha is handled while packing B.
if ( bli_obj_dt( c ) != bli_obj_dt( b ) ||
bli_obj_comp_prec( c ) != bli_obj_prec( c ) )
if ( !bli_obj_imag_is_zero( alpha ) )
{

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@@ -5,6 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -90,9 +91,14 @@ void bli_gemm_packb
)
{
AOCL_DTL_TRACE_ENTRY(AOCL_DTL_LEVEL_TRACE_5);
obj_t b_pack;
// BY setting family id to BLIS_GEMM_MD, we indicate packing kernels
// to scale alpha while packing.
if(bli_obj_dt(c) != bli_obj_dt(a))
bli_cntl_set_family(BLIS_GEMM_MD, cntl);
// Pack matrix B according to the control tree node.
bli_l3_packm
(
@@ -103,6 +109,10 @@ void bli_gemm_packb
cntl,
thread
);
// Once packing of B matrix is done, fall back to GEMM execution.
if(bli_obj_dt(c) != bli_obj_dt(a))
bli_cntl_set_family(BLIS_GEMM, cntl);
// Proceed with execution using packed matrix B.
bli_gemm_int

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@@ -302,9 +302,7 @@ void PASTEF77(ch,blasname) \
#ifdef BLIS_ENABLE_BLAS
INSERT_GENTFUNC_BLAS( gemm,gemm )
// Observed a regression in dgemm with this function addition.
// Disabling temporarily.
#if 0
#if 1
void dzgemm_
(
const f77_char* transa,
@@ -381,7 +379,7 @@ void dzgemm_
bli_obj_init_finish_1x1( dt, (dcomplex*)alpha, &alphao );
bli_obj_init_finish_1x1( dt, (dcomplex*)beta, &betao );
bli_obj_init_finish( dt_a, m0_a, n0_a, (dcomplex*)a, rs_a, cs_a, &ao );
bli_obj_init_finish( dt_a, m0_a, n0_a, (double*)a, rs_a, cs_a, &ao );
bli_obj_init_finish( dt, m0_b, n0_b, (dcomplex*)b, rs_b, cs_b, &bo );
bli_obj_init_finish( dt, m0, n0, (dcomplex*)c, rs_c, cs_c, &co );

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@@ -5,6 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -54,8 +55,7 @@ BLIS_EXPORT_BLAS void PASTEF77(ch,blasname) \
);
#ifdef BLIS_ENABLE_BLAS
// Disabling temporarily
#if 0
#if 1
BLIS_EXPORT_BLAS void dzgemm_
(
const f77_char* transa, \

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@@ -6,7 +6,7 @@
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2016, Hewlett Packard Enterprise Development LP
Copyright (C) 2021, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2021 - 22, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -931,10 +931,11 @@ typedef enum
BLIS_TRMM,
BLIS_TRSM,
BLIS_GEMMT,
BLIS_GEMM_MD,
BLIS_NOID
} opid_t;
#define BLIS_NUM_LEVEL3_OPS 11
#define BLIS_NUM_LEVEL3_OPS 12
// -- Blocksize ID type --

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@@ -5,7 +5,7 @@
libraries.
Copyright (C) 2014, The University of Texas at Austin
Copyright (C) 2019-2021, Advanced Micro Devices, Inc. All rights reserved.
Copyright (C) 2019-2022, Advanced Micro Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
@@ -382,8 +382,7 @@ int main( int argc, char** argv )
cp, ldc
);
#else
//Disabled dzgemm function temporarily.
#if 0
#if 1
if( bli_is_double( dt_a ) )
{
dzgemm_(
@@ -401,7 +400,6 @@ int main( int argc, char** argv )
}
else
{
#else
zgemm_( &f77_transa,
&f77_transb,
&mm,
@@ -412,7 +410,7 @@ int main( int argc, char** argv )
bp, (f77_int*)&ldb,
betap,
cp, (f77_int*)&ldc );
// }
}
#endif
#endif
}