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Arm SVE C/ZGEMM Fix FMOV 0 Mistake

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FMOV [hsd]M, #imm does not allow zero immediate.
Use wzr, xzr instead.
This commit is contained in:
RuQing Xu
2021-10-08 12:34:14 +09:00
parent 82b61283b2
commit ccf16289d2
2 changed files with 4 additions and 4 deletions
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4
kernels/armsve/3/bli_gemm_armsve_asm_c2vx10_unindexed.c
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@@ -231,7 +231,7 @@ MOV_COL2(z8 ,z9 ,z10,z11,z16,z17,z18,z19)
" b.ne WRITE_MEM_G \n\t"
" \n\t"
" WRITE_MEM_C: \n\t"
" fmov s29, #0.0 \n\t"
" fmov s29, wzr \n\t"
" fcmp s31, #0.0 \n\t" // Whether Imag(beta) == 0.
" fccmp s30, s29, 0, eq \n\t" // Whether Real(beta) == 0.
" b.eq ZERO_BETA_C_0_1_2_3 \n\t"
@@ -260,7 +260,7 @@ GEMM_CCMPLX_STORE_COL2_C(z8 ,z9 ,z10,z11,p0,%2,%4)
" add %3, %3, %3 \n\t" // Skips passed to index is multiplied by 2,
" mov x3, %3 \n\t" // s.t. 2*sizeof(float) = 2*4 = 8.
" index z28.s, wzr, w3 \n\t"
" fmov s29, #0.0 \n\t"
" fmov s29, wzr \n\t"
" fcmp s31, #0.0 \n\t" // Whether Imag(beta) == 0.
" fccmp s30, s29, 0, eq \n\t" // Whether Real(beta) == 0.
" b.eq ZERO_BETA_G_0_1_2_3 \n\t"

4
kernels/armsve/3/bli_gemm_armsve_asm_z2vx10_unindexed.c
View File

@@ -231,7 +231,7 @@ MOV_COL2(z8 ,z9 ,z10,z11,z16,z17,z18,z19)
" b.ne WRITE_MEM_G \n\t"
" \n\t"
" WRITE_MEM_C: \n\t"
" fmov d29, #0.0 \n\t"
" fmov d29, xzr \n\t"
" fcmp d31, #0.0 \n\t" // Whether Imag(beta) == 0.
" fccmp d30, d29, 0, eq \n\t" // Whether Real(beta) == 0.
" b.eq ZERO_BETA_C_0_1_2_3 \n\t"
@@ -259,7 +259,7 @@ GEMM_CCMPLX_STORE_COL2_C(z8 ,z9 ,z10,z11,p0,%2,%4)
" WRITE_MEM_G: \n\t"
" add %3, %3, %3 \n\t" // Skips passed to index is multiplied by 2,
" index z28.d, xzr, %3 \n\t" // s.t. 2*sizeof(double) = 2*8 = 16.
" fmov d29, #0.0 \n\t"
" fmov d29, xzr \n\t"
" fcmp d31, #0.0 \n\t" // Whether Imag(beta) == 0.
" fccmp d30, d29, 0, eq \n\t" // Whether Real(beta) == 0.
" b.eq ZERO_BETA_G_0_1_2_3 \n\t"