mirror of
https://github.com/amd/blis.git
synced 2026-05-11 09:39:59 +00:00
Fixed more Xeon Phi bugs, especially with scattered update
This commit is contained in:
Tyler Smith
@@ -78,7 +78,7 @@ GIT_LOG := $(GIT) log --decorate
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# --- Determine the C compiler and related flags ---
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CC := icc
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CPPROCFLAGS :=
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CMISCFLAGS := -mmic -fasm-blocks -std=c99 -openmp
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CMISCFLAGS := -mmic -fasm-blocks -std=c99
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CDBGFLAGS :=
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CWARNFLAGS := -Wall
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COPTFLAGS := -O3
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@@ -98,7 +98,7 @@ ARFLAGS := cru
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# --- Determine the linker and related flags ---
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LINKER := $(CC)
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LDFLAGS := -lm
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LDFLAGS := -mmic -lm
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@@ -275,8 +275,8 @@ void bli_dgemm_opt_30x8(
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auxinfo_t* data
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)
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{
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double * a_next = bli_auxinfo_next_a( aux );
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double * b_next = bli_auxinfo_next_b( aux );
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double * a_next = bli_auxinfo_next_a( data );
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double * b_next = bli_auxinfo_next_b( data );
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int * offsetPtr = &offsets[0];
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@@ -364,7 +364,7 @@ void bli_dgemm_opt_30x8(
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LOOPMAIN:
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ONE_ITER_MAIN_LOOP(rcx, rsi)
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jne LOOPMAIN
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//Penultimate 22 iterations.
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//Break these off from the main loop to avoid prefetching extra shit.
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mov r14, a_next
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@@ -398,20 +398,24 @@ void bli_dgemm_opt_30x8(
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POSTACCUM:
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// jmp END
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#ifdef MONITORS
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rdtsc
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mov mid2l, eax
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mov mid2h, edx
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#endif
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mov r9, c //load address of c for update
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mov r12, alpha //load address of alpha
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// Check if C is row stride. If not, jump to the slow scattered update
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mov r14, cs_c
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dec r14
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jne SCATTEREDUPDATE
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mov r14, beta
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vbroadcastsd zmm31, 0[r14]
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mov r9, c //load address of c for update
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mov r12, alpha //load address of alpha
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vmulpd zmm0, zmm0, 0[r12]{1to8}
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vmulpd zmm1, zmm1, 0[r12]{1to8}
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@@ -526,7 +530,7 @@ void bli_dgemm_opt_30x8(
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vpbroadcastd zmm30, cs_c
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mov r13, beta
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vpmulld zmm30, zmm31, zmm30
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mov ebx, 255
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UPDATE_C_ROW_SCATTERED(zmm0, 0, r9)
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UPDATE_C_ROW_SCATTERED(zmm1, 1, r9)
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@@ -45,8 +45,7 @@ void PASTEMAC(ch,varname)( \
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ctype* b, \
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ctype* beta, \
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ctype* c, inc_t rs_c, inc_t cs_c, \
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auxinfo_t* data, \
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dim_t thread_id \
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auxinfo_t* data \
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);
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INSERT_GENTPROT_BASIC( gemm_opt_30x8 )
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@@ -9,7 +9,7 @@
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#
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1 # Number of repeats per experiment (best result is reported)
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c # Matrix storage scheme(s) to test:
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r # Matrix storage scheme(s) to test:
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# 'c' = col-major storage; 'g' = general stride storage;
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# 'r' = row-major storage
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c # Vector storage scheme(s) to test:
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@@ -17,12 +17,12 @@ c # Vector storage scheme(s) to test:
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# 'r' = rowvec / unit stride; 'i' = rowvec / non-unit stride
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0 # Test all combinations of storage schemes?
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32 # General stride spacing (for cases when testing general stride)
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sdcz # Datatype(s) to test:
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d # Datatype(s) to test:
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# 's' = single real; 'c' = single complex;
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# 'd' = double real; 'z' = double complex
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100 # Problem size: first to test
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300 # Problem size: maximum to test
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100 # Problem size: increment between experiments
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120 # Problem size: first to test
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480 # Problem size: maximum to test
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120 # Problem size: increment between experiments
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1 # Error-checking level:
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# '0' = disable error checking; '1' = full error checking
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i # Reaction to test failure:
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@@ -77,12 +77,12 @@
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# --- Section overrides ----------------------------------------------------
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1 # Utility
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1 # Level-1v
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1 # Level-1m
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1 # Level-1f kernels
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1 # Level-2
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1 # Level-3 micro-kernels
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0 # Utility
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0 # Level-1v
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0 # Level-1m
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0 # Level-1f kernels
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0 # Level-2
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0 # Level-3 micro-kernels
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1 # Level-3
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@@ -293,47 +293,47 @@
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-1 -1 -2 # dimensions: m n k
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?? # parameters: transa transb
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1 # hemm
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0 # hemm
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1 # test sequential front-end
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-1 -2 # dimensions: m n
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???? # parameters: side uploa conja transb
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1 # herk
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0 # herk
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1 # test sequential front-end
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-1 -2 # dimensions: m k
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?? # parameters: uploc transa
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1 # her2k
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0 # her2k
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1 # test sequential front-end
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-1 -2 # dimensions: m k
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??? # parameters: uploc transa transb
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1 # symm
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0 # symm
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1 # test sequential front-end
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-1 -2 # dimensions: m n
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???? # parameters: side uploa conja transb
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1 # syrk
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0 # syrk
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1 # test sequential front-end
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-1 -2 # dimensions: m k
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?? # parameters: uploc transa
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1 # syr2k
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0 # syr2k
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1 # test sequential front-end
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-1 -2 # dimensions: m k
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??? # parameters: uploc transa transb
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1 # trmm
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0 # trmm
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1 # test sequential front-end
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-1 -1 # dimensions: m n
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???? # parameters: side uploa transa diaga
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1 # trmm3
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0 # trmm3
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1 # test sequential front-end
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-1 -1 # dimensions: m n
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????? # parameters: side uploa transa diaga transb
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1 # trsm
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0 # trsm
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1 # test sequential front-end
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-1 -1 # dimensions: m n
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???? # parameters: side uploa transa diaga
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