mirror of
https://github.com/amd/blis.git
synced 2026-05-05 06:51:11 +00:00
e249a00a82
Details: - Added the new bli_dgemm_skx_asm_16x14.c microkernel from the skx-redux branch, along with appropriate blocksizes in bli_cntx_init_skx.c and a prototype in bli_kernels_skx.h. (Devin has not yet written the sgemm analague, so for now we will continue using the older sgemm ukernel.) - Updated frame/include/bli_x86_asm_macros.h with a minor change that was present within the skx-redux branch.
131 lines
4.7 KiB
C
131 lines
4.7 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of The University of Texas at Austin nor the names
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of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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void bli_cntx_init_skx( cntx_t* cntx )
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{
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blksz_t blkszs[ BLIS_NUM_BLKSZS ];
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// Set default kernel blocksizes and functions.
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bli_cntx_init_skx_ref( cntx );
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// -------------------------------------------------------------------------
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// Update the context with optimized native gemm micro-kernels and
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// their storage preferences.
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bli_cntx_set_l3_nat_ukrs
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(
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2,
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// gemm
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BLIS_GEMM_UKR, BLIS_FLOAT , bli_sgemm_skx_asm_32x12_l2, FALSE,
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BLIS_GEMM_UKR, BLIS_DOUBLE, bli_dgemm_skx_asm_16x14, FALSE,
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cntx
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);
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// Update the context with optimized level-1f kernels.
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bli_cntx_set_l1f_kers
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(
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4,
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// axpyf
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BLIS_AXPYF_KER, BLIS_FLOAT, bli_saxpyf_zen_int_8,
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BLIS_AXPYF_KER, BLIS_DOUBLE, bli_daxpyf_zen_int_8,
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// dotxf
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BLIS_DOTXF_KER, BLIS_FLOAT, bli_sdotxf_zen_int_8,
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BLIS_DOTXF_KER, BLIS_DOUBLE, bli_ddotxf_zen_int_8,
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cntx
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);
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// Update the context with optimized level-1v kernels.
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bli_cntx_set_l1v_kers
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(
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10,
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// amaxv
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BLIS_AMAXV_KER, BLIS_FLOAT, bli_samaxv_zen_int,
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BLIS_AMAXV_KER, BLIS_DOUBLE, bli_damaxv_zen_int,
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// axpyv
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#if 0
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int,
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#else
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int10,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int10,
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#endif
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// dotv
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BLIS_DOTV_KER, BLIS_FLOAT, bli_sdotv_zen_int,
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BLIS_DOTV_KER, BLIS_DOUBLE, bli_ddotv_zen_int,
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// dotxv
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BLIS_DOTXV_KER, BLIS_FLOAT, bli_sdotxv_zen_int,
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BLIS_DOTXV_KER, BLIS_DOUBLE, bli_ddotxv_zen_int,
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// scalv
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#if 0
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int,
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#else
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int10,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int10,
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#endif
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cntx
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);
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// Initialize level-3 blocksize objects with architecture-specific values.
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// s d c z
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bli_blksz_init_easy( &blkszs[ BLIS_MR ], 32, 16, 3, 3 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], 12, 14, 8, 4 );
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 480, 240, 144, 72 );
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bli_blksz_init ( &blkszs[ BLIS_KC ], 384, 384, 256, 256,
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480, 480, 256, 256 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 3072, 3752, 4080, 4080 );
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bli_blksz_init_easy( &blkszs[ BLIS_AF ], 8, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_DF ], 8, 8, -1, -1 );
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// Update the context with the current architecture's register and cache
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// blocksizes (and multiples) for native execution.
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bli_cntx_set_blkszs
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(
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BLIS_NAT, 7,
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// level-3
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BLIS_NC, &blkszs[ BLIS_NC ], BLIS_NR,
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BLIS_KC, &blkszs[ BLIS_KC ], BLIS_KR,
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BLIS_MC, &blkszs[ BLIS_MC ], BLIS_MR,
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BLIS_NR, &blkszs[ BLIS_NR ], BLIS_NR,
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BLIS_MR, &blkszs[ BLIS_MR ], BLIS_MR,
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// level-1f
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BLIS_AF, &blkszs[ BLIS_AF ], BLIS_AF,
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BLIS_DF, &blkszs[ BLIS_DF ], BLIS_DF,
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cntx
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);
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}
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