Vignesh Balasubramanian 476ae9359c Functionality testing of DAXPBYV, DAXPYV and DCOPYV APIs
- Implemented a design to allow isolation of micro-kernels to
  compare against the standard reference as part of GTestSuite.
  The design requires the kernel address to be passed as one of
  the values from the instantiator. This is further sent to the
  testing interface, which makes the call to the micro-kernel
  directly.

- The testing interface is templatized with both the datatype and
  the function-pointer type. This interface makes the direct call
  to the micro-kernel(address passed as a parameter), in addition
  to the call to the reference API.

- Added unit tests to cover the functionality testing of the following
  kernels :
  - bli_daxpbyv_zen_int10( ... ) and bli_daxpbyv_zen_int( ... )
  - bli_daxpyv_zen_int10( ... ), bli_daxpyv_zen_int10( ... ) and
    bli_daxpyv_zen_int_avx512( ... ).
  - bli_dcopyvv_zen_int( ... ).
  Further added dummy tests for bli_saxpbyv_zen_int10( ... ),
  bli_saxpbyv_zen_int( ... ) and bli_zaxpbyv_zen_int( ... ) kernels
  to verify the templatized testing interface.

- Added API level test-cases, to verify the functionality
  of DAXPY and DAXPBY APIs. These tests cover unit increments,
  negative increments(BLAS/CBLAS) and non-unit positive increments.
  Furthermore, for DAXPY an instantiator tests with sizes
  corresponding to the AOCL_DYNAMIC thresholds, since it is
  multithreaded at the framework level.

- Updated the API-level tests for ZAXPBY to allow negative increment
  testing only if GTestsuite is not configured for native BLIS
  typed interface as reference.

AMD-Internal: [CPUPL-4402]
Change-Id: I86b3b52d0737075897a9e9bc5e8d9654f75072fc
2024-01-19 01:53:34 -05:00
2024-01-17 11:41:15 -05:00
2023-11-23 08:54:31 -05:00
2024-01-17 11:41:15 -05:00
2019-05-23 12:51:17 -05:00
2023-11-23 08:54:31 -05:00
2023-11-23 08:54:31 -05:00
2019-10-02 10:16:22 +01:00
2021-03-22 17:42:33 -05:00
2023-11-23 08:54:31 -05:00
2023-11-10 13:05:12 -05:00
2018-08-07 14:21:07 -05:00
2023-11-23 08:54:31 -05:00
2023-11-23 08:54:31 -05:00
2023-05-25 14:46:33 +00:00
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2023-08-08 07:27:41 -04:00

AOCL-BLAS library

AOCL-BLAS is AMD's optimized version of BLAS targeted for AMD EPYC and Ryzen CPUs. It is developed as a forked version of BLIS (https://github.com/flame/blis), which is developed by members of the Science of High-Performance Computing (SHPC) group in the Institute for Computational Engineering and Sciences at The University of Texas at Austin and other collaborators (including AMD). All known features and functionalities of BLIS are retained and supported in AOCL-BLAS library. AOCL-BLAS is regularly updated with the improvements from the upstream repository.

AOCL BLAS is optimized with SSE2, AVX2, AVX512 instruction sets which would be enabled based on the target Zen architecture using the dynamic dispatch feature. All prominent Level 3, Level 2 and Level 1 APIs are designed and optimized for specific paths targeting different size spectrums e.g., Small, Medium and Large sizes. These algorithms are designed and customized to exploit the architectural improvements of the target platform.

For detailed instructions on how to configure, build, install, and link against AOCL-BLAS on AMD CPUs, please refer to the AOCL User Guide located on AMD developer portal.

The upstream repository (https://github.com/flame/blis) contains further information on BLIS, including background information on BLIS design, usage examples, and a complete BLIS API reference.

AOCL-BLAS is developed and maintained by AMD. You can contact us on the email-id toolchainsupport@amd.com. You can also raise any issue/suggestion on the git-hub repository at https://github.com/amd/blis/issues.

Description
BLAS-like Library Instantiation Software Framework
Readme BSD-3-Clause 72 MiB
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