mirror of
https://github.com/amd/blis.git
synced 2026-05-04 22:41:11 +00:00
e94a0530e5
Details:
- Updated an incorrectly set cache blocksize NC for single real within
config/zen/bli_cntx_init_zen.c that was non a multiple of the
corresponding value of NR. This issue, which was caught by Travis CI,
was introduced in 29b0e1e.
227 lines
8.4 KiB
C
227 lines
8.4 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2018 - 2019, Advanced Micro Devices, Inc.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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//GEMMSUP_KER_PROT( double, d, gemmsup_r_haswell_ref )
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void bli_cntx_init_zen( cntx_t* cntx )
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{
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blksz_t blkszs[ BLIS_NUM_BLKSZS ];
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blksz_t thresh[ BLIS_NUM_THRESH ];
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// Set default kernel blocksizes and functions.
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bli_cntx_init_zen_ref( cntx );
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// -------------------------------------------------------------------------
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// Update the context with optimized native gemm micro-kernels and
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// their storage preferences.
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bli_cntx_set_l3_nat_ukrs
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(
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8,
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// gemm
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BLIS_GEMM_UKR, BLIS_FLOAT, bli_sgemm_haswell_asm_6x16, TRUE,
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BLIS_GEMM_UKR, BLIS_DOUBLE, bli_dgemm_haswell_asm_6x8, TRUE,
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BLIS_GEMM_UKR, BLIS_SCOMPLEX, bli_cgemm_haswell_asm_3x8, TRUE,
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BLIS_GEMM_UKR, BLIS_DCOMPLEX, bli_zgemm_haswell_asm_3x4, TRUE,
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// gemmtrsm_l
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BLIS_GEMMTRSM_L_UKR, BLIS_FLOAT, bli_sgemmtrsm_l_haswell_asm_6x16, TRUE,
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BLIS_GEMMTRSM_L_UKR, BLIS_DOUBLE, bli_dgemmtrsm_l_haswell_asm_6x8, TRUE,
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// gemmtrsm_u
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BLIS_GEMMTRSM_U_UKR, BLIS_FLOAT, bli_sgemmtrsm_u_haswell_asm_6x16, TRUE,
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BLIS_GEMMTRSM_U_UKR, BLIS_DOUBLE, bli_dgemmtrsm_u_haswell_asm_6x8, TRUE,
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cntx
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);
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// Update the context with optimized level-1f kernels.
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bli_cntx_set_l1f_kers
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(
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4,
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// axpyf
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BLIS_AXPYF_KER, BLIS_FLOAT, bli_saxpyf_zen_int_8,
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BLIS_AXPYF_KER, BLIS_DOUBLE, bli_daxpyf_zen_int_8,
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// dotxf
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BLIS_DOTXF_KER, BLIS_FLOAT, bli_sdotxf_zen_int_8,
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BLIS_DOTXF_KER, BLIS_DOUBLE, bli_ddotxf_zen_int_8,
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cntx
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);
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// Update the context with optimized level-1v kernels.
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bli_cntx_set_l1v_kers
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(
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10,
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// amaxv
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BLIS_AMAXV_KER, BLIS_FLOAT, bli_samaxv_zen_int,
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BLIS_AMAXV_KER, BLIS_DOUBLE, bli_damaxv_zen_int,
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// axpyv
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#if 0
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int,
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#else
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BLIS_AXPYV_KER, BLIS_FLOAT, bli_saxpyv_zen_int10,
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BLIS_AXPYV_KER, BLIS_DOUBLE, bli_daxpyv_zen_int10,
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#endif
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// dotv
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BLIS_DOTV_KER, BLIS_FLOAT, bli_sdotv_zen_int,
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BLIS_DOTV_KER, BLIS_DOUBLE, bli_ddotv_zen_int,
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// dotxv
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BLIS_DOTXV_KER, BLIS_FLOAT, bli_sdotxv_zen_int,
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BLIS_DOTXV_KER, BLIS_DOUBLE, bli_ddotxv_zen_int,
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// scalv
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#if 0
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int,
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#else
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BLIS_SCALV_KER, BLIS_FLOAT, bli_sscalv_zen_int10,
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BLIS_SCALV_KER, BLIS_DOUBLE, bli_dscalv_zen_int10,
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#endif
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cntx
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);
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// Initialize level-3 blocksize objects with architecture-specific values.
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// s d c z
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bli_blksz_init_easy( &blkszs[ BLIS_MR ], 6, 6, 3, 3 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], 16, 8, 8, 4 );
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/*
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Multi Instance performance improvement of DGEMM when binded to a CCX
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In Multi instance each thread runs a sequential DGEMM.
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a) If BLIS is run in a multi-instance mode with
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CPU freq 2.6/2.2 Ghz
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DDR4 clock frequency 2400Mhz
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mc = 240, kc = 512, and nc = 2040
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has better performance on EPYC server, over the default block sizes.
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b) If BLIS is run in Single Instance mode
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mc = 510, kc = 1024 and nc = 4080
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*/
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#ifdef BLIS_ENABLE_ZEN_BLOCK_SIZES
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// Zen optmized level 3 cache block sizes
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#if BLIS_ENABLE_SINGLE_INSTANCE_BLOCK_SIZES
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 1020, 510, 510, 255 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], 1024, 1024, 1024, 1024 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 8160, 4080, 4080, 3056 );
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#else
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 144, 240, 144, 72 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], 256, 512, 256, 256 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 4080, 2040, 2040, 1528 );
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#endif
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#else
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 144, 72, 144, 72 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], 256, 256, 256, 256 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 8160, 4080, 4080, 3056 );
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#endif
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bli_blksz_init_easy( &blkszs[ BLIS_AF ], 8, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_DF ], 8, 8, -1, -1 );
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// Update the context with the current architecture's register and cache
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// blocksizes (and multiples) for native execution.
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bli_cntx_set_blkszs
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(
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BLIS_NAT, 7,
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// level-3
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BLIS_NC, &blkszs[ BLIS_NC ], BLIS_NR,
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BLIS_KC, &blkszs[ BLIS_KC ], BLIS_KR,
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BLIS_MC, &blkszs[ BLIS_MC ], BLIS_MR,
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BLIS_NR, &blkszs[ BLIS_NR ], BLIS_NR,
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BLIS_MR, &blkszs[ BLIS_MR ], BLIS_MR,
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// level-1f
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BLIS_AF, &blkszs[ BLIS_AF ], BLIS_AF,
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BLIS_DF, &blkszs[ BLIS_DF ], BLIS_DF,
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cntx
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);
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// -------------------------------------------------------------------------
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// Initialize sup thresholds with architecture-appropriate values.
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// s d c z
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bli_blksz_init_easy( &thresh[ BLIS_MT ], -1, 256, -1, -1 );
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bli_blksz_init_easy( &thresh[ BLIS_NT ], -1, 100, -1, -1 );
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bli_blksz_init_easy( &thresh[ BLIS_KT ], -1, 120, -1, -1 );
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// Initialize the context with the sup thresholds.
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bli_cntx_set_l3_sup_thresh
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(
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3,
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BLIS_MT, &thresh[ BLIS_MT ],
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BLIS_NT, &thresh[ BLIS_NT ],
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BLIS_KT, &thresh[ BLIS_KT ],
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cntx
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);
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// Update the context with optimized small/unpacked gemm kernels.
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bli_cntx_set_l3_sup_kers
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(
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8,
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//BLIS_RCR, BLIS_DOUBLE, bli_dgemmsup_r_haswell_ref,
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BLIS_RRR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
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BLIS_RRC, BLIS_DOUBLE, bli_dgemmsup_rd_haswell_asm_6x8m, TRUE,
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BLIS_RCR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
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BLIS_RCC, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
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BLIS_CRR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8m, TRUE,
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BLIS_CRC, BLIS_DOUBLE, bli_dgemmsup_rd_haswell_asm_6x8n, TRUE,
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BLIS_CCR, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
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BLIS_CCC, BLIS_DOUBLE, bli_dgemmsup_rv_haswell_asm_6x8n, TRUE,
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cntx
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);
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// Initialize level-3 sup blocksize objects with architecture-specific
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// values.
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// s d c z
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bli_blksz_init ( &blkszs[ BLIS_MR ], -1, 6, -1, -1,
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-1, 9, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], -1, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], -1, 72, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], -1, 256, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], -1, 4080, -1, -1 );
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// Update the context with the current architecture's register and cache
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// blocksizes for small/unpacked level-3 problems.
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bli_cntx_set_l3_sup_blkszs
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(
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5,
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BLIS_NC, &blkszs[ BLIS_NC ],
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BLIS_KC, &blkszs[ BLIS_KC ],
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BLIS_MC, &blkszs[ BLIS_MC ],
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BLIS_NR, &blkszs[ BLIS_NR ],
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BLIS_MR, &blkszs[ BLIS_MR ],
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cntx
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);
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}
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