edbbfd9a86
- For edge kernels which handles the corner cases and specially for cases where there is really small amount of computation to be done, executing FMA efficiently becomes very crucial. - In previous implementation, edge kernels were using same, limited number of vector register to hold FMA result, which indirectly creates dependency on previous FMA to complete before CPU can issue new FMA. - This commit address this issue by using different vector registers that are available at disposal to hold FMA result. - That way we hold FMA results in two sets of vector registers, so that sub-sequent FMA won't have to wait for previous FMA to complete. - At the end of un-rolled K loop these two sets of vector registers are added together to store correct result in intended vector registers. - Following kernels are modified: bli_dgemmsup_rv_zen4_asm_24x4m, bli_dgemmsup_rv_zen4_asm_24x3m, bli_dgemmsup_rv_zen4_asm_24x2m, bli_dgemmsup_rv_zen4_asm_24x1m, bli_dgemmsup_rv_zen4_asm_24x1, bli_dgemmsup_rv_zen4_asm_16x1, bli_dgemmsup_rv_zen4_asm_8x1, bli_dgemmsup_rv_zen4_asm_24x2, bli_dgemmsup_rv_zen4_asm_16x2, bli_dgemmsup_rv_zen4_asm_8x2, bli_dgemmsup_rv_zen4_asm_24x3, bli_dgemmsup_rv_zen4_asm_16x3, bli_dgemmsup_rv_zen4_asm_8x3, bli_dgemmsup_rv_zen4_asm_16x4, bli_dgemmsup_rv_zen4_asm_8x4, bli_dgemmsup_rv_zen4_asm_16x5, bli_dgemmsup_rv_zen4_asm_8x5, bli_dgemmsup_rv_zen4_asm_16x6, bli_dgemmsup_rv_zen4_asm_8x6, bli_dgemmsup_rv_zen4_asm_8x7, bli_dgemmsup_rv_zen4_asm_8x8 AMD-Internal: [CPUPL-3574] Change-Id: I318ff8e2f075820bcc0505aa1c13d0679f73af44
AOCL-BLAS library
AOCL-BLAS is AMD's optimized version of BLAS targeted for AMD EPYC and Ryzen CPUs. It is developed as a forked version of BLIS (https://github.com/flame/blis), which is developed by members of the Science of High-Performance Computing (SHPC) group in the Institute for Computational Engineering and Sciences at The University of Texas at Austin and other collaborators (including AMD). All known features and functionalities of BLIS are retained and supported in AOCL-BLAS library. AOCL-BLAS is regularly updated with the improvements from the upstream repository.
AOCL BLAS is optimized with SSE2, AVX2, AVX512 instruction sets which would be enabled based on the target Zen architecture using the dynamic dispatch feature. All prominent Level 3, Level 2 and Level 1 APIs are designed and optimized for specific paths targeting different size spectrums e.g., Small, Medium and Large sizes. These algorithms are designed and customized to exploit the architectural improvements of the target platform.
For detailed instructions on how to configure, build, install, and link against AOCL-BLAS on AMD CPUs, please refer to the AOCL User Guide located on AMD developer portal.
The upstream repository (https://github.com/flame/blis) contains further information on BLIS, including background information on BLIS design, usage examples, and a complete BLIS API reference.
AOCL-BLAS is developed and maintained by AMD. You can contact us on the email-id toolchainsupport@amd.com. You can also raise any issue/suggestion on the git-hub repository at https://github.com/amd/blis/issues.