mirror of
https://github.com/amd/blis.git
synced 2026-05-11 09:39:59 +00:00
1. Implemented efficient AVX-512, AVX-2 and SSE-2 version of the error function - ERF 2. Added error function based GeLU activation post-ops for the S32, S16 and BF16 (LPGEMM) and SGEMM APIs. 3. Changes for this includes frame and micro-kernel level changes in addition to adding the marco based function definations of the ERF function in the math-utils and gelu headerfiles. AMD-Internal: [CPUPL-3036] Change-Id: Ie50f6dcabf8896b7a6d30bbc16aa44392cc512be