mirror of
https://github.com/ikawrakow/ik_llama.cpp.git
synced 2026-02-24 07:04:11 +00:00
iq3_ks: mmq
This commit is contained in:
@@ -94,6 +94,9 @@ void ggml_cuda_op_mul_mat_q(
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case GGML_TYPE_IQ4_NL:
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mul_mat_q_case<GGML_TYPE_IQ4_NL>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_KS:
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mul_mat_q_case<GGML_TYPE_IQ3_KS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_KS:
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mul_mat_q_case<GGML_TYPE_IQ4_KS>(ctx, args, stream);
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break;
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@@ -196,6 +199,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) {
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case GGML_TYPE_IQ1_S_R4:
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case GGML_TYPE_IQ4_XS:
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case GGML_TYPE_IQ4_NL:
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case GGML_TYPE_IQ3_KS:
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case GGML_TYPE_IQ4_KS:
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case GGML_TYPE_IQ4_KS_R4:
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case GGML_TYPE_IQ5_KS:
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@@ -87,6 +87,7 @@ static mmq_q8_1_ds_layout mmq_get_q8_1_ds_layout(const ggml_type type_x) {
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case GGML_TYPE_IQ2_K:
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case GGML_TYPE_IQ2_K_R4:
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case GGML_TYPE_IQ3_K:
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case GGML_TYPE_IQ3_KS:
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case GGML_TYPE_IQ3_K_R4:
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case GGML_TYPE_IQ4_KS:
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case GGML_TYPE_IQ4_KS_R4:
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@@ -199,6 +200,7 @@ static constexpr __host__ __device__ tile_x_sizes mmq_get_dp4a_tile_x_sizes(ggml
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case GGML_TYPE_IQ1_S_R4: return MMQ_DP4A_TXS_Q8_0;
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case GGML_TYPE_IQ4_XS : return MMQ_DP4A_TXS_Q8_0;
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case GGML_TYPE_IQ4_NL : return MMQ_DP4A_TXS_Q8_0;
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case GGML_TYPE_IQ3_KS : return MMQ_DP4A_TXS_Q8_0;
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case GGML_TYPE_IQ4_KS : return MMQ_DP4A_TXS_Q8_0;
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case GGML_TYPE_IQ4_KS_R4 : return MMQ_DP4A_TXS_Q8_0;
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case GGML_TYPE_IQ5_KS : return MMQ_DP4A_TXS_Q8_0;
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@@ -254,6 +256,7 @@ static constexpr __host__ __device__ int mmq_get_mma_tile_x_k(ggml_type type) {
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case GGML_TYPE_IQ1_S_R4: return MMQ_MMA_TILE_X_K_Q8_0;
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case GGML_TYPE_IQ4_XS : return MMQ_MMA_TILE_X_K_Q8_0;
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case GGML_TYPE_IQ4_NL : return MMQ_MMA_TILE_X_K_Q8_0;
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case GGML_TYPE_IQ3_KS : return MMQ_MMA_TILE_X_K_Q8_0;
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case GGML_TYPE_IQ4_KS : return MMQ_MMA_TILE_X_K_Q8_0;
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case GGML_TYPE_IQ4_KS_R4 : return MMQ_MMA_TILE_X_K_Q8_0;
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case GGML_TYPE_IQ5_KS : return MMQ_MMA_TILE_X_K_Q8_0;
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@@ -2700,63 +2703,76 @@ template <int mmq_y, int nwarps, bool need_check> static __device__ __forceinlin
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}
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}
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//template <int mmq_y, int nwarps, bool need_check> static __device__ __forceinline__ void load_tiles_iq4_ks(
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// const char * __restrict__ x, int * __restrict__ x_tile, const int & kbx0, const int & i_max, const int & stride) {
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//
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//#ifdef INT8_MMA_AVAILABLE
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// int * x_qs = (int *) x_tile;
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// float * x_df = (float *) (x_qs + WARP_SIZE*2);
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//#else
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// constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ4_XS, mmq_y);
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// int * x_qs = (int *) x_tile;
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// float * x_df = (float *) (x_qs + txs.qs);
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//#endif // INT8_MMA_AVAILABLE
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//
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// const int kbx = 0; // threadIdx.x / QI4_XS
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// const int kqsx = threadIdx.x; // threadIdx.x % QI4_XS
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//
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//#pragma unroll
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// for (int i0 = 0; i0 < mmq_y; i0 += nwarps) {
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// int i = i0 + threadIdx.y;
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//
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// if (need_check) {
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// i = min(i, i_max);
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// }
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//
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// const block_iq4_ks * bxi = (const block_iq4_ks *)(x + i*stride + sizeof(float)) + kbx0 + kbx;
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//
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// auto values = iq4k_values + ((bxi->scales[kqsx/4] & 1) << 4);
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// const int aux_q4 = get_int_b4(bxi->qs, kqsx);
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// const int2 v = get_int_from_table_16(aux_q4, values);
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// const int k0 = 8 * (threadIdx.x / 4) + threadIdx.x % 4;
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//#ifdef INT8_MMA_AVAILABLE
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// x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 0] = v.x;
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// x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 4] = v.y;
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//#else
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// x_qs[i*(2*WARP_SIZE + 1) + k0 + 0] = v.x;
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// x_qs[i*(2*WARP_SIZE + 1) + k0 + 4] = v.y;
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//#endif // INT8_MMA_AVAILABLE
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// }
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//
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//#pragma unroll
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// for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 4) {
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// int i = i0 + threadIdx.y * 4 + threadIdx.x / (WARP_SIZE/4);
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//
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// if (need_check) {
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// i = min(i, i_max);
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// }
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//
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// const float * dptr = (const float *)(x + i*stride);
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// const block_iq4_ks * bxi = (const block_iq4_ks *)(dptr + 1) + kbx0;
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// const int ls = (bxi->scales[threadIdx.x % 8] & 254) - 127;
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//
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//#ifdef INT8_MMA_AVAILABLE
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// x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + threadIdx.x % 8] = dptr[0] * ls;
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//#else
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// x_df[i*(WARP_SIZE/4) + i/4 + threadIdx.x % 8] = dptr[0] * ls;
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//#endif // INT8_MMA_AVAILABLE
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// }
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//}
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template <int mmq_y, int nwarps, bool need_check> static __device__ __forceinline__ void load_tiles_iq3_ks(
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const char * __restrict__ x, int * __restrict__ x_tile, const int & kbx0, const int & i_max, const int & stride) {
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#ifdef INT8_MMA_AVAILABLE
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int * x_qs = (int *) x_tile;
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float * x_df = (float *) (x_qs + WARP_SIZE*2);
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#else
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constexpr tile_x_sizes txs = MMQ_DP4A_TXS_Q8_0_16;
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int * x_qs = (int *) x_tile;
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float * x_df = (float *) (x_qs + txs.qs);
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#endif // INT8_MMA_AVAILABLE
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constexpr int qstep = 8;
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const int kqsx = threadIdx.x % qstep;
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auto values = iq3nl_values;
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uint32_t aux32[4];
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const uint8_t * aux8 = (const uint8_t *)aux32;
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#pragma unroll
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for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/qstep) {
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int i = i0 + threadIdx.y*(WARP_SIZE/qstep) + threadIdx.x/qstep;
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if (need_check) {
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i = min(i, i_max);
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}
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const half * dptr = (const half *)(x + i*stride);
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const float d = __half2float(dptr[0]);
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const block_iq3_ks * bxi = (const block_iq3_ks *)(dptr + 1) + kbx0;
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uint16_t extra = bxi->extra >> 8;
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int qh = get_int_b2(bxi->qh, kqsx);
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#pragma unroll
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for (int l = 0; l < qstep/4; ++l) {
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const int ql = get_int_b2(bxi->qs, kqsx + qstep*l);
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aux32[0] = ((ql >> 0) & 0x03030303) | ((qh << 2) & 0x04040404) | (((extra << 3) & 8) * 0x01010101);
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aux32[1] = ((ql >> 2) & 0x03030303) | ((qh << 1) & 0x04040404) | (((extra << 2) & 8) * 0x01010101);
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aux32[2] = ((ql >> 4) & 0x03030303) | ((qh >> 0) & 0x04040404) | (((extra << 1) & 8) * 0x01010101);
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aux32[3] = ((ql >> 6) & 0x03030303) | ((qh >> 1) & 0x04040404) | (((extra << 0) & 8) * 0x01010101);
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extra >>= 4;
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qh >>= 4;
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const char4 val0 = make_char4(values[aux8[ 0]], values[aux8[ 1]], values[aux8[ 2]], values[aux8[ 3]]);
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const char4 val1 = make_char4(values[aux8[ 4]], values[aux8[ 5]], values[aux8[ 6]], values[aux8[ 7]]);
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const char4 val2 = make_char4(values[aux8[ 8]], values[aux8[ 9]], values[aux8[10]], values[aux8[11]]);
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const char4 val3 = make_char4(values[aux8[12]], values[aux8[13]], values[aux8[14]], values[aux8[15]]);
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#ifdef INT8_MMA_AVAILABLE
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x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx + 32*l + 0] = *(const int *)&val0;
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x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx + 32*l + 8] = *(const int *)&val1;
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x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx + 32*l + 16] = *(const int *)&val2;
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x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx + 32*l + 24] = *(const int *)&val3;
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#else
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x_qs[i*(2*WARP_SIZE + 1) + kqsx + 32*l + 0] = *(const int *)&val0;
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x_qs[i*(2*WARP_SIZE + 1) + kqsx + 32*l + 8] = *(const int *)&val1;
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x_qs[i*(2*WARP_SIZE + 1) + kqsx + 32*l + 16] = *(const int *)&val2;
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x_qs[i*(2*WARP_SIZE + 1) + kqsx + 32*l + 24] = *(const int *)&val3;
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#endif // INT8_MMA_AVAILABLE
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}
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#ifdef INT8_MMA_AVAILABLE
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x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = d * (int(((bxi->scales[kqsx%4] >> 4*(kqsx/4)) & 0xf) | (((bxi->extra >> kqsx) & 1) << 4)) - 16);
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#else
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x_df[i*(WARP_SIZE/4) + i/4 + kqsx] = d * (int(((bxi->scales[kqsx%4] >> 4*(kqsx/4)) & 0xf) | (((bxi->extra >> kqsx) & 1) << 4)) - 16);
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#endif // INT8_MMA_AVAILABLE
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}
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}
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template <int mmq_y, int nwarps, bool need_check> static __device__ __forceinline__ void load_tiles_iq4_ks(
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const char * __restrict__ x, int * __restrict__ x_tile, const int & kbx0, const int & i_max, const int & stride) {
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@@ -3657,6 +3673,13 @@ struct mmq_type_traits<mmq_x, mmq_y, nwarps, need_check, GGML_TYPE_IQ2_KS> {
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static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a<mmq_x, mmq_y, nwarps>;
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};
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template <int mmq_x, int mmq_y, int nwarps, bool need_check>
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struct mmq_type_traits<mmq_x, mmq_y, nwarps, need_check, GGML_TYPE_IQ3_KS> {
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static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_ks<mmq_y, nwarps, need_check>;
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static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma<mmq_x, mmq_y, nwarps, MMQ_Q8_1_DS_LAYOUT_D4>;
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static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a<mmq_x, mmq_y, nwarps>;
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};
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template <int mmq_x, int mmq_y, int nwarps, bool need_check>
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struct mmq_type_traits<mmq_x, mmq_y, nwarps, need_check, GGML_TYPE_IQ4_KS> {
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static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_ks<mmq_y, nwarps, need_check>;
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@@ -4142,6 +4165,7 @@ extern DECL_MMQ_CASE(GGML_TYPE_IQ3_S);
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extern DECL_MMQ_CASE(GGML_TYPE_IQ1_S);
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extern DECL_MMQ_CASE(GGML_TYPE_IQ4_NL);
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extern DECL_MMQ_CASE(GGML_TYPE_IQ4_XS);
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extern DECL_MMQ_CASE(GGML_TYPE_IQ3_KS);
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extern DECL_MMQ_CASE(GGML_TYPE_IQ4_KS);
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extern DECL_MMQ_CASE(GGML_TYPE_IQ4_KS_R4);
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extern DECL_MMQ_CASE(GGML_TYPE_IQ5_KS_R4);
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@@ -0,0 +1,5 @@
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// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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#include "../mmq.cuh"
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DECL_MMQ_CASE(GGML_TYPE_IQ3_KS);
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