ikawrakow/ik_llama.cpp
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iqk_mul_mat: slightly better fp16 with 16 vector registers

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2x6 (Nx x Ny) tiles instead of 3x4. We get 142.7 t/s on the Ryzen-5975WX
up from 138 t/s. We use Nx registers to preload the fp16 weights,
so total registers required is Nx * (Ny + 1), so 15 in the case
of of 3 x 4 tiles and 14 for 2 x 6 tiles. I guess, the one spare
register helps. But maybe it is just a matter of how things get
loaded into the cache. On the 7950X I did try 3 x 8 and it did
not perform as well as 5 x 5.
This commit is contained in:
Kawrakow
2024-06-10 11:40:32 +03:00
parent 9dba81ddf2
commit dfcb8bebc5
1 changed files with 6 additions and 3 deletions
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iqk_mul_mat.cpp
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@@ -2224,7 +2224,7 @@ void mul_mat_f16_f32_T(int n, const void * vx, size_t bx, const DataInfo& info,
#ifdef __AVX512F__
constexpr int k_nx = 5;
#else
constexpr int k_nx = 3;
constexpr int k_nx = 2;
#endif
const char * cx = (const char *)vx;
for (int ix = 0; ix < nrc_x/k_nx; ++ix) {
@@ -2236,9 +2236,10 @@ void mul_mat_f16_f32_T(int n, const void * vx, size_t bx, const DataInfo& info,
switch (nx) {
case 1: mul_mat_f16_f32_NxN<nrc_y, 1>(n, cx, bx, last_x, info); break;
case 2: mul_mat_f16_f32_NxN<nrc_y, 2>(n, cx, bx, last_x, info); break;
#ifdef __AVX512F__
case 3: mul_mat_f16_f32_NxN<nrc_y, 3>(n, cx, bx, last_x, info); break;
case 4: mul_mat_f16_f32_NxN<nrc_y, 4>(n, cx, bx, last_x, info); break;
#ifndef __AVX512F__
case 5: mul_mat_f16_f32_NxN<nrc_y, 5>(n, cx, bx, last_x, info); break;
#endif
}
}
@@ -2392,8 +2393,10 @@ bool MulMat::set_mul_mat(int typeA, int ne00, MulMat& mm, int& row_size_q8, int
mm.funcs[1] = mul_mat_f16_f32_T<2>;
mm.funcs[2] = mul_mat_f16_f32_T<3>;
mm.funcs[3] = mul_mat_f16_f32_T<4>;
#ifdef __AVX512F__
mm.funcs[4] = mul_mat_f16_f32_T<5>;
mm.funcs[4] = mul_mat_f16_f32_T<5>;
#ifndef __AVX512F__
mm.funcs[5] = mul_mat_f16_f32_T<6>;
#endif
row_size_q8 = ggml_row_size(GGML_TYPE_F32, ne00);
return true;