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43 lines
2.1 KiB
Markdown
43 lines
2.1 KiB
Markdown
### 🔀 [#152](https://github.com/ikawrakow/ik_llama.cpp/pull/152) - IQ3_XXS_R4
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| **Author** | `ikawrakow` |
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| :--- | :--- |
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| **State** | ❌ **Closed** |
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| **Created** | 2024-12-20 |
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| **Updated** | 2024-12-20 |
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#### Description
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Sub-4 bpw i-quants have a terrible CPU performance, so I was curious to see if we can improve by interleaving rows.
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This PR adds `IQ3_XXS_R4`, a 4-row interleaved version of `IQ3_XXS`.
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We get decent performance gains, but still remain much slower than k- or legacy quants. I think there is still potential for optimization, but I was getting constantly confused about shuffling signs and scales, so at the end gave up with this result.
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Here is `PP-512` for LLaMA-3.1-8B on `Zen4` (Ryzen-7950X), `ARM_NEON` (M2-Max) and `AVX2` (Ryzen-5975WX)
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| Platform | Threads | IQ3_XXS | IQ3_XXS_R4 | Speedup |
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| ---: | ---: | ---: | ---: | ---: |
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| ARM_NEON | 8 | 48.18 ± 0.69 | 67.45 ± 0.78 | 1.400 |
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| Zen4 | 16 | 107.42 ± 0.33 | 141.62 ± 0.30 | 1.318 |
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| AVX2 | 32 | 142.38 ± 0.48 | 184.42 ± 0.26 | 1.295 |
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We get decent performance gains for TG as well, especially on `AVX2`.
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Here results for TG-128 on LLaMA-3.1-8B with different numbers of threads:
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| Platform | Threads | IQ4_KS | IQ4_KS_R4 | Speedup |
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| ---: | ---: | ---: | ---: | ---: |
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| ARM_NEON | 2 | 3.46 ± 0.02 | 4.79 ± 0.00 | 1.384 |
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| | 4 | 6.65 ± 0.01 | 8.78 ± 0.04 | 1.320 |
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| | 8 | 10.83 ± 0.18 | 15.95 ± 0.25 | 1.473 |
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| Zen4 | 2 | 5.18 ± 0.00 | 6.53 ± 0.00 | 1.261 |
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| | 4 | 9.70 ± 0.0 | 12.15 ± 0.00 | 1.253 |
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| | 8 | 17.19 ± 0.18 | 17.93 ± 0.00 | 1.044 |
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| AVX2 | 2 | 2.04 ± 0.0 | 4.07 ± 0.00 | 1.995 |
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| | 4 | 4.04 ± 0.00 | 7.94 ± 0.00 | 1.965 |
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| | 8 | 7.40 ± 0.01 | 14.16 ± 0.06 | 1.914 |
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| | 16 | 13.64 ± 0.00 | 17.92 ± 0.01 | 1.314 |
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We now manage to saturate the available memory bandwidth on the Ryzen CPUs at 8 (Ryzen-7950X) or 16 (Ryzen-5975WX) threads, but are far from being memory bound on the M2-Max. |