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43 lines
2.2 KiB
Markdown
43 lines
2.2 KiB
Markdown
### 🔀 [#154](https://github.com/ikawrakow/ik_llama.cpp/pull/154) - IQ2_XXS_R4
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| **Author** | `ikawrakow` |
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| :--- | :--- |
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| **State** | ❌ **Closed** |
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| **Created** | 2024-12-20 |
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| **Updated** | 2024-12-20 |
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#### Description
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Sub-4 bpw i-quants have a terrible CPU performance, so I was curious to see if we can improve by interleaving rows.
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This PR adds `IQ2_XXS_R4`, a 4-row interleaved version of `IQ2_XXS`.
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We get decent performance gains, but still remain much slower than k- or legacy quants. I think there is still potential for optimization, but I was getting constantly confused about shuffling signs and scales, so at the end gave up with this result.
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Here is `PP-512` for LLaMA-3.1-8B on `Zen4` (Ryzen-7950X), `ARM_NEON` (M2-Max) and `AVX2` (Ryzen-5975WX)
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| Platform | Threads | IQ2_XXS | IQ2_XXS_R4 | Speedup |
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| ---: | ---: | ---: | ---: | ---: |
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| ARM_NEON | 8 | 56.40 ± 0.99 | 76.34 ± 0.58 | 1.354 |
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| Zen4 | 16 | 134.68 ± 0.31 | 153.60 ± 0.23 | 1.140 |
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| AVX2 | 32 | 155.48 ± 0.17 | 195.72 ± 0.20 | 1.259 |
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We get very decent performance gains for TG as well, especially on `AVX2`.
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Here results for TG-128 on LLaMA-3.1-8B with different numbers of threads:
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| Platform | Threads | IQ2_XXS | IQ2_XXS_R4 | Speedup |
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| ---: | ---: | ---: | ---: | ---: |
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| ARM_NEON | 2 | 4.40 ± 0.03 | 6.65 ± 0.00 | 1.511 |
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| | 4 | 8.61 ± 0.01 | 12.20 ± 0.02 | 1.417 |
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| | 8 | 15.84 ± 0.34 | 21.76 ± 0.31 | 1.374 |
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| Zen4 | 2 | 6.59 ± 0.00 | 8.66 ± 0.00 | 1.314 |
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| | 4 | 11.62 ± 0.81 | 15.49 ± 0.36 | 1.333 |
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| | 8 | 20.40 ± 0.70 | 23.37 ± 0.03 | 1.146 |
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| AVX2 | 2 | 2.62 ± 0.00 | 5.54 ± 0.00 | 2.115 |
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| | 4 | 5.17 ± 0.00 | 10.81 ± 0.00 | 2.091 |
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| | 8 | 9.49 ± 0.02 | 18.93 ± 0.08 | 1.995 |
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| | 16 | 16.97 ± 0.00 | 25.70 ± 0.01 | 1.514 |
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We now manage to saturate the available memory bandwidth on the Ryzen CPUs at 8 (Ryzen-7950X) or 16 (Ryzen-5975WX) threads, but are far from being memory bound on the M2-Max. |