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580.65.06

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This commit is contained in:
Maneet Singh
2025-08-04 11:15:02 -07:00
parent d890313300
commit 307159f262
1315 changed files with 477791 additions and 279973 deletions
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31
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -30,6 +30,7 @@ extern "C" {
#include "nvmisc.h"
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080ecc.h"
#define RM_USER_SHARED_DATA (0x000000de)
@@ -87,16 +88,6 @@ do {
(((timestamp) >= (RUSD_SEQ_START)) && /* Non-Polled Data */ \
(((timestamp) & (0x1LLU)) == 1LLU)))
enum {
RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0,
RUSD_CLK_PUBLIC_DOMAIN_MEMORY,
RUSD_CLK_PUBLIC_DOMAIN_VIDEO,
// Put at the end. See bug 1000230 NVML doesn't report SM frequency on Kepler
RUSD_CLK_PUBLIC_DOMAIN_SM,
RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE,
};
enum {
RUSD_CLK_THROTTLE_REASON_GPU_IDLE = NVBIT(0),
RUSD_CLK_THROTTLE_REASON_APPLICATION_CLOCK_SETTING = NVBIT(1),
@@ -129,6 +120,16 @@ typedef struct RUSD_PMA_MEMORY_INFO {
NvU64 freePmaMemory;
} RUSD_PMA_MEMORY_INFO;
enum {
RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0,
RUSD_CLK_PUBLIC_DOMAIN_MEMORY,
RUSD_CLK_PUBLIC_DOMAIN_VIDEO,
// Put at the end. See bug 1000230 NVML doesn't report SM frequency on Kepler
RUSD_CLK_PUBLIC_DOMAIN_SM,
RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE,
};
typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFO {
NvU32 targetClkMHz;
} RUSD_CLK_PUBLIC_DOMAIN_INFO;
@@ -205,10 +206,18 @@ typedef struct RUSD_MEM_ERROR_COUNTS {
#define RUSD_MEMORY_ERROR_TYPE_SRAM 2
#define RUSD_MEMORY_ERROR_TYPE_COUNT 3
typedef struct RUSD_ECC_COUNTS {
NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS volatileCounts;
NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS clientExposedCounts;
} RUSD_ECC_INFO;
typedef struct RUSD_MEM_ECC {
volatile NvU64 lastModifiedTimestamp;
// Provided from NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS
RUSD_MEM_ERROR_COUNTS count[RUSD_MEMORY_ERROR_TYPE_COUNT];
// TODO: Due to incapability of getting voteup for X driver update with
// existing RM APIs, need to resolve bug 5138911 before fully updating
// RUSD_MEM_ECC and removing deprecated RUSD_MEM_ERROR_COUNTS.
RUSD_ECC_INFO info;
} RUSD_MEM_ECC;
typedef struct RUSD_POWER_LIMIT_INFO {

6
src/common/sdk/nvidia/inc/class/cl2080_notification.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -221,7 +221,6 @@ extern "C" {
#define NV2080_NOTIFIERS_OFA1 (180)
#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182)
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_NOTIFIERS_NVENC3 (183)
#define NV2080_NOTIFIERS_GSP_PERF_TRACE (184)
#define NV2080_NOTIFIERS_INBAND_RESPONSE (185)
@@ -251,7 +250,6 @@ extern "C" {
(((x) >= NV2080_NOTIFIERS_CE10) && ((x) <= NV2080_NOTIFIERS_CE19)))
// Indexed MSENC notifier reference
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_NOTIFIERS_NVENC(x) (((x) < 3) ? (NV2080_NOTIFIERS_NVENC0 + (x)) : (NV2080_NOTIFIERS_NVENC3 + (x) - 3))
#define NV2080_NOTIFIERS_NVENC_IDX(x) (((x) <= NV2080_NOTIFIERS_NVENC2) ? ((x) - NV2080_NOTIFIERS_NVENC0) : ((x) - NV2080_NOTIFIERS_NVENC3 + 3))
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) ((((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) || \
@@ -350,7 +348,6 @@ extern "C" {
#define NV2080_ENGINE_TYPE_COPY18 (0x0000003c)
#define NV2080_ENGINE_TYPE_COPY19 (0x0000003d)
#define NV2080_ENGINE_TYPE_OFA1 (0x0000003e)
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_ENGINE_TYPE_NVENC3 (0x0000003f)
// See TBD documentation for how these defines work with existing ENGINE_TYPE_COPYN defines
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 (0x00000040)
@@ -402,7 +399,6 @@ extern "C" {
#define NV2080_ENGINE_TYPE_COPY_IDX(i) (((i) <= NV2080_ENGINE_TYPE_COPY9) ? \
((i) - NV2080_ENGINE_TYPE_COPY0) : ((i) - NV2080_ENGINE_TYPE_COPY10 + 10))
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_ENGINE_TYPE_NVENC(i) (((i) < 3) ? (NV2080_ENGINE_TYPE_NVENC0 + (i)) : (NV2080_ENGINE_TYPE_NVENC3 + (i) - 3))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) ((((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) <= NV2080_ENGINE_TYPE_NVENC2)) || \
(((i) == NV2080_ENGINE_TYPE_NVENC3)))

3
src/common/sdk/nvidia/inc/class/cla084.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,6 +68,7 @@ typedef struct NVA084_ALLOC_PARAMETERS {
NvU32 swizzId;
NvU32 vgpuType;
NvU32 vmPid;
NvU32 accountingPid;
NvU32 numChannels;
NvU32 numPluginChannels;
NvU16 placementId;

3
src/common/sdk/nvidia/inc/class/cla084_notification.h
View File

@@ -42,7 +42,8 @@ extern "C" {
#define NVA084_NOTIFIERS_EVENT_PRINT_ERROR_MESSAGE (5)
#define NVA084_NOTIFIERS_EVENT_GUEST_LICENSE_STATE_CHANGED (6)
#define NVA084_NOTIFIERS_EVENT_UPDATE_GUEST_OS_TYPE (7)
#define NVA084_NOTIFIERS_MAXCOUNT (8)
#define NVA084_NOTIFIERS_EVENT_INIT_GR_ENGINE (8)
#define NVA084_NOTIFIERS_MAXCOUNT (9)
#define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)

34
src/common/sdk/nvidia/inc/ctrl/ctrla16f.h → src/common/sdk/nvidia/inc/class/clc863.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,33 +21,11 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef CLC863_H
#define CLC863_H
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrla16f.finn
//
#define HOPPER_MMU_VIDMEM_ACCESS_BIT_BUFFER (0xc863)
#define NVC863_SIZE 1024
/* GK100_GPFIFO control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#define NVA16F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xA16F, NVA16F_CTRL_##cat, idx)
/* GK100_GPFIFO command categories (6bits) */
#define NVA16F_CTRL_RESERVED (0x00)
/*
* NVA16F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NVA16F_CTRL_CMD_NULL (0xa16f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID << 8) | 0x0" */
#endif

2
src/common/sdk/nvidia/inc/class/clc96f.h
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@@ -69,6 +69,8 @@ typedef volatile struct Nvc96fControl_struct {
#define NVC96F_MEM_OP_D_OPERATION 31:27
#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
#define NVC96F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
#define NVC96F_MEM_OP_D_OPERATION_L2_SYSMEM_NCOH_INVALIDATE 0x00000011
#define NVC96F_SEM_ADDR_LO (0x0000005c)
#define NVC96F_SEM_ADDR_LO_OFFSET 31:2

38
src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h → src/common/sdk/nvidia/inc/class/clcc70.h
View File

@@ -1,6 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
* Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -14,7 +13,7 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
@@ -23,33 +22,20 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc46f.finn
// Source file: class/clcc70.finn
//
#define NVCC70_DISPLAY (0xcc70U) /* finn: Evaluated from "NVCC70_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NVCC70_ALLOCATION_PARAMETERS_MESSAGE_ID (0xcc70U)
/* TURING_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVC46F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC36F, NVC46F_CTRL_##cat, idx)
/* TURING_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC46F_CTRL_RESERVED (0x00)
#define NVC46F_CTRL_GPFIFO (0x01)
/*
* NVC46F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned is: NV_OK
*/
#define NVC46F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
typedef struct NVCC70_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
} NVCC70_ALLOCATION_PARAMETERS;

186
src/common/sdk/nvidia/inc/class/clcc71.h Normal file
View File

@@ -0,0 +1,186 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcc71_h_
#define _clcc71_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCC71_DISP_SF_USER (0x000CC71)
typedef volatile struct _clcc71_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */
} _NvCC71DispSfUser, NvCC71DispSfUserMap;
#define NVCC71_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVCC71_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */
#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */
#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */
#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */
#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */
#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */
#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcc71_h_

915
src/common/sdk/nvidia/inc/class/clcc73.h Normal file
View File

@@ -0,0 +1,915 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcc73_h_
#define _clcc73_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCC73_DISP_CAPABILITIES 0xCC73
typedef volatile struct _clcc73_tag0 {
NvU32 dispCapabilities[0x400];
} _NvCC73DispCapabilities,NvCC73DispCapabilities_Map ;
#define NVCC73_SYS_CAP 0x0 /* RW-4R */
#define NVCC73_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
#define NVCC73_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCC73_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NVCC73_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
#define NVCC73_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
#define NVCC73_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
#define NVCC73_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
#define NVCC73_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
#define NVCC73_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
#define NVCC73_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
#define NVCC73_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
#define NVCC73_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVCC73_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
#define NVCC73_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_RISCV0_EXISTS 16:16 /* RWIVF */
#define NVCC73_SYS_CAP_RISCV0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_RISCV0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */
#define NVCC73_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */
#define NVCC73_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */
#define NVCC73_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */
#define NVCC73_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */
#define NVCC73_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
#define NVCC73_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB 0x4 /* RW-4R */
#define NVCC73_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCC73_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
#define NVCC73_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC 0x20 /* RW-4R */
#define NVCC73_SYS_CAPC_TILE0_EXISTS 0:0 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE1_EXISTS 1:1 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE2_EXISTS 2:2 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE3_EXISTS 3:3 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE4_EXISTS 4:4 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE5_EXISTS 5:5 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE6_EXISTS 6:6 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE7_EXISTS 7:7 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCC73_SYS_CAPC_TILE_EXISTS__SIZE_1 8 /* */
#define NVCC73_SYS_CAPC_TILE_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
#define NVCC73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE__SIZE_1 8 /* */
#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPC_MERGER_TILE_BUFFER_SIZE 31:16 /* RWIUF */
#define NVCC73_SYS_CAPD 0x2c /* RW-4R */
#define NVCC73_SYS_CAPD_NUM_TELLTALE_REGIONS 4:0 /* RWIUF */
#define NVCC73_SYS_CAPD_NUM_FROZEN_FRAME_REGIONS 12:8 /* RWIUF */
#define NVCC73_SYS_CAPD_NUM_ROI 20:16 /* RWIUF */
#define NVCC73_SYS_CAPD_AE_SDP_EXISTS 30:30 /* RWIVF */
#define NVCC73_SYS_CAPD_AE_SDP_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPD_AE_SDP_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPD_AMSS_EXISTS 31:31 /* RWIVF */
#define NVCC73_SYS_CAPD_AMSS_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPD_AMSS_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE 0x34 /* RW-4R */
#define NVCC73_SYS_CAPE_VIRWIN0_EXISTS 0:0 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN1_EXISTS 1:1 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN2_EXISTS 2:2 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN3_EXISTS 3:3 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN4_EXISTS 4:4 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN5_EXISTS 5:5 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN6_EXISTS 6:6 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN7_EXISTS 7:7 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN8_EXISTS 8:8 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN9_EXISTS 9:9 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN10_EXISTS 10:10 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN11_EXISTS 11:11 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN12_EXISTS 12:12 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN13_EXISTS 13:13 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN14_EXISTS 14:14 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN15_EXISTS 15:15 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN16_EXISTS 16:16 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN17_EXISTS 17:17 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN18_EXISTS 18:18 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN19_EXISTS 19:19 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN20_EXISTS 20:20 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN21_EXISTS 21:21 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN22_EXISTS 22:22 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN23_EXISTS 23:23 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN24_EXISTS 24:24 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN25_EXISTS 25:25 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN26_EXISTS 26:26 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN27_EXISTS 27:27 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN28_EXISTS 28:28 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN29_EXISTS 29:29 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN30_EXISTS 30:30 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN31_EXISTS 31:31 /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCC73_SYS_CAPE_VIRWIN_EXISTS__SIZE_1 32 /* */
#define NVCC73_SYS_CAPE_VIRWIN_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_SYS_CAPE_VIRWIN_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_MISC_CAPA_NUM_VMS 17:13 /* RWIUF */
#define NVCC73_LINK_CAP 0x30 /* RW-4R */
#define NVCC73_LINK_CAP_PHYCTRL0_EXISTS 0:0 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL1_EXISTS 1:1 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL2_EXISTS 2:2 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL3_EXISTS 3:3 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL4_EXISTS 4:4 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL5_EXISTS 5:5 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL6_EXISTS 6:6 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL7_EXISTS 7:7 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL8_EXISTS 8:8 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL9_EXISTS 9:9 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL10_EXISTS 10:10 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL11_EXISTS 11:11 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL12_EXISTS 12:12 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL13_EXISTS 13:13 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL14_EXISTS 14:14 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL15_EXISTS 15:15 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL16_EXISTS 16:16 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL17_EXISTS 17:17 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL18_EXISTS 18:18 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL19_EXISTS 19:19 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL20_EXISTS 20:20 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL21_EXISTS 21:21 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL22_EXISTS 22:22 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL23_EXISTS 23:23 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL24_EXISTS 24:24 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL25_EXISTS 25:25 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL26_EXISTS 26:26 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL27_EXISTS 27:27 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL28_EXISTS 28:28 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL29_EXISTS 29:29 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL30_EXISTS 30:30 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL31_EXISTS 31:31 /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCC73_LINK_CAP_PHYCTRL_EXISTS__SIZE_1 32 /* */
#define NVCC73_LINK_CAP_PHYCTRL_EXISTS_NO 0x00000000 /* RW--V */
#define NVCC73_LINK_CAP_PHYCTRL_EXISTS_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA 0x10 /* RW-4R */
#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS 26:26 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC 0x18 /* RW-4R */
#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION 13:13 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_TRUE 0x00000001 /* RWI-V */
#define NVCC73_IHUB_COMMON_CAPE 0x24 /* RW-4R */
#define NVCC73_IHUB_COMMON_CAPE_PHYWIN_BUFFER_SIZE 15:0 /* RWIUF */
#define NVCC73_IHUB_COMMON_CAPF 0x28 /* RW-4R */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE 0:0 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE 1:1 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE 2:2 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE 3:3 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE 4:4 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE 5:5 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE 6:6 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE 7:7 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE 16:16 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE 17:17 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE 18:18 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE 19:19 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE 20:20 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE 21:21 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE 22:22 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE 23:23 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE 24:24 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE 25:25 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE 26:26 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE 27:27 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE 28:28 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE 29:29 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE 30:30 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE 31:31 /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE__SIZE_1 32 /* */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */
#define NVCC73_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */
#define NVCC73_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_LTM_PRESENT 25:25 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPA_LTM_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPA_LTM_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */
#define NVCC73_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */
#define NVCC73_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */
#define NVCC73_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */
#define NVCC73_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */
#define NVCC73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */
#define NVCC73_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */
#define NVCC73_POSTCOMP_HDR_CAPE_DSC_MAXLINEWIDTH 15:0 /* RWIUF */
#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT 18:18 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE 21:19 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_9x9x9 0x00000000 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_17x17x17 0x00000001 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_25x25x25 0x00000002 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_33x33x33 0x00000003 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_4 0x00000004 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_5 0x00000005 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_6 0x00000006 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_7 0x00000007 /* RW--V */
#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_NUM_CURVES 23:22 /* RWIUF */
#define NVCC73_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */
#define NVCC73_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */
#define NVCC73_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPF_LTM_MAX_PIXELS 31:16 /* RWIVF */
#define NVCC73_POSTCOMP_HDR_CAPG(i) (0x698+(i)*32) /* RW-4A */
#define NVCC73_POSTCOMP_HDR_CAPG__SIZE_1 8 /* */
#define NVCC73_POSTCOMP_HDR_CAPG_CMI_SZ 11:0 /* RWIUF */
#define NVCC73_POSTCOMP_HDR_CAPG_CMI_LOGNR 14:12 /* RWIUF */
#define NVCC73_POSTCOMP_HDR_CAPG_CMO_SZ 26:15 /* RWIUF */
#define NVCC73_POSTCOMP_HDR_CAPG_CMO_LOGNR 29:27 /* RWIUF */
#define NVCC73_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */
#define NVCC73_SOR_CAP__SIZE_1 8 /* */
#define NVCC73_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
#define NVCC73_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
#define NVCC73_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
#define NVCC73_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
#define NVCC73_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_DUAL_MODE 4:4 /* RWIVF */
#define NVCC73_SOR_CAP_DP_DUAL_MODE_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_DUAL_MODE_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
#define NVCC73_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
#define NVCC73_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
#define NVCC73_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
#define NVCC73_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_TUNNELING_OVER_USB4 15:15 /* RWIVF */
#define NVCC73_SOR_CAP_DP_TUNNELING_OVER_USB4_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_TUNNELING_OVER_USB4_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_SDI 16:16 /* RWIVF */
#define NVCC73_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_DUAL_MST 23:23 /* RWIVF */
#define NVCC73_SOR_CAP_DP_DUAL_MST_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_DUAL_MST_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_A 24:24 /* RWIVF */
#define NVCC73_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_B 25:25 /* RWIVF */
#define NVCC73_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
#define NVCC73_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
#define NVCC73_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
#define NVCC73_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_HDMI_FRL_YUV422 29:29 /* RWIVF */
#define NVCC73_SOR_CAP_HDMI_FRL_YUV422_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_HDMI_FRL_YUV422_TRUE 0x00000001 /* RW--V */
#define NVCC73_SOR_CAP_DP_128B132B 30:30 /* RWIVF */
#define NVCC73_SOR_CAP_DP_128B132B_FALSE 0x00000000 /* RW--V */
#define NVCC73_SOR_CAP_DP_128B132B_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT 13:13 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT 13:13 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVCC73_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */
#define NVCC73_SOR_CLK_CAP__SIZE_1 8 /* */
#define NVCC73_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
#define NVCC73_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
#define NVCC73_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
#ifdef __cplusplus
};
#endif /* extern C */
#endif //_clcc73_h_

216
src/common/sdk/nvidia/inc/class/clcc7a.h Normal file
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@@ -0,0 +1,216 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcc7a__h_
#define _clcc7a__h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCC7A_CURSOR_IMM_CHANNEL_PIO (0x0000CC7A)
typedef volatile struct _clcc7a_tag0 {
NvV32 Reserved00[0x2];
NvV32 Free; // 0x00000008 - 0x0000000B
NvV32 Reserved01[0x7D];
NvV32 Update; // 0x00000200 - 0x00000203
NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207
NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F
NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213
NvV32 Reserved02[0x3F7B];
} NVCC7ADispCursorImmControlPio;
#define NVCC7A_FREE (0x00000008)
#define NVCC7A_FREE_COUNT 5:0
#define NVCC7A_UPDATE (0x00000200)
#define NVCC7A_UPDATE_RELEASE_ELV 0:0
#define NVCC7A_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCC7A_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN 8:4
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCC7A_UPDATE_FORCE_FULLSCREEN 12:12
#define NVCC7A_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCC7A_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS (0x00000204)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVCC7A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVCC7A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0
#define NVCC7A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcc7a_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcc7b_h_
#define _clcc7b_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCC7B_WINDOW_IMM_CHANNEL_DMA (0x0000CC7B)
// dma opcode instructions
#define NVCC7B_DMA
#define NVCC7B_DMA_OPCODE 31:29
#define NVCC7B_DMA_OPCODE_METHOD 0x00000000
#define NVCC7B_DMA_OPCODE_JUMP 0x00000001
#define NVCC7B_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVCC7B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVCC7B_DMA_METHOD_COUNT 27:18
#define NVCC7B_DMA_METHOD_OFFSET 15:2
#define NVCC7B_DMA_DATA 31:0
#define NVCC7B_DMA_DATA_NOP 0x00000000
#define NVCC7B_DMA_JUMP_OFFSET 15:2
#define NVCC7B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVCC7B_PUT (0x00000000)
#define NVCC7B_PUT_PTR 13:0
#define NVCC7B_GET (0x00000004)
#define NVCC7B_GET_PTR 13:0
#define NVCC7B_UPDATE (0x00000200)
#define NVCC7B_UPDATE_RELEASE_ELV 0:0
#define NVCC7B_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCC7B_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCC7B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
#define NVCC7B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVCC7B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVCC7B_UPDATE_FORCE_FULLSCREEN 4:4
#define NVCC7B_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCC7B_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCC7B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVCC7B_SET_POINT_OUT_X 15:0
#define NVCC7B_SET_POINT_OUT_Y 31:16
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcc7b_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcc7e_h_
#define _clcc7e_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCC7E_WINDOW_CHANNEL_DMA (0x0000CC7E)
// dma opcode instructions
#define NVCC7E_DMA
#define NVCC7E_DMA_OPCODE 31:29
#define NVCC7E_DMA_OPCODE_METHOD 0x00000000
#define NVCC7E_DMA_OPCODE_JUMP 0x00000001
#define NVCC7E_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVCC7E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVCC7E_DMA_METHOD_COUNT 27:18
#define NVCC7E_DMA_METHOD_OFFSET 15:2
#define NVCC7E_DMA_DATA 31:0
#define NVCC7E_DMA_DATA_NOP 0x00000000
#define NVCC7E_DMA_JUMP_OFFSET 15:2
#define NVCC7E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVCC7E_PUT (0x00000000)
#define NVCC7E_PUT_PTR 13:0
#define NVCC7E_GET (0x00000004)
#define NVCC7E_GET_PTR 13:0
#define NVCC7E_UPDATE (0x00000200)
#define NVCC7E_UPDATE_RELEASE_ELV 0:0
#define NVCC7E_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCC7E_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN 8:4
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCC7E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12
#define NVCC7E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
#define NVCC7E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
#define NVCC7E_UPDATE_FORCE_FULLSCREEN 16:16
#define NVCC7E_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCC7E_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCC7E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204)
#define NVCC7E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0
#define NVCC7E_GET_LINE (0x00000208)
#define NVCC7E_GET_LINE_LINE 15:0
#define NVCC7E_SET_SEMAPHORE_CONTROL (0x0000020C)
#define NVCC7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11
#define NVCC7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000)
#define NVCC7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001)
#define NVCC7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVCC7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVCC7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVCC7E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14
#define NVCC7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000)
#define NVCC7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCC7E_SET_SEMAPHORE_ACQUIRE (0x00000210)
#define NVCC7E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NVCC7E_SET_SEMAPHORE_RELEASE (0x00000214)
#define NVCC7E_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NVCC7E_SET_NOTIFIER_CONTROL (0x00000220)
#define NVCC7E_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVCC7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVCC7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCC7E_SET_SIZE (0x00000224)
#define NVCC7E_SET_SIZE_WIDTH 15:0
#define NVCC7E_SET_SIZE_HEIGHT 31:16
#define NVCC7E_SET_STORAGE (0x00000228)
#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVCC7E_SET_PARAMS (0x0000022C)
#define NVCC7E_SET_PARAMS_FORMAT 7:0
#define NVCC7E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVCC7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVCC7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVCC7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVCC7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVCC7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVCC7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVCC7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVCC7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVCC7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVCC7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVCC7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVCC7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVCC7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVCC7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVCC7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVCC7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
#define NVCC7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVCC7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVCC7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVCC7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVCC7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVCC7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVCC7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVCC7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVCC7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVCC7E_SET_PARAMS_SWAP_UV 19:19
#define NVCC7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVCC7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVCC7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
#define NVCC7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
#define NVCC7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
#define NVCC7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVCC7E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVCC7E_SET_SEMAPHORE_RELEASE_HI (0x0000023C)
#define NVCC7E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY (0x00000240)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY (0x00000244)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY (0x00000248)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY (0x0000024C)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVCC7E_SET_POINT_IN_X 15:0
#define NVCC7E_SET_POINT_IN_Y 31:16
#define NVCC7E_SET_SIZE_IN (0x00000298)
#define NVCC7E_SET_SIZE_IN_WIDTH 15:0
#define NVCC7E_SET_SIZE_IN_HEIGHT 31:16
#define NVCC7E_SET_SIZE_OUT (0x000002A4)
#define NVCC7E_SET_SIZE_OUT_WIDTH 15:0
#define NVCC7E_SET_SIZE_OUT_HEIGHT 31:16
#define NVCC7E_SET_CONTROL_INPUT_SCALER (0x000002A8)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0
#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4
#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE 8:8
#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE 9:9
#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC)
#define NVCC7E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0
#define NVCC7E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12
#define NVCC7E_SET_COMPOSITION_CONTROL (0x000002EC)
#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0
#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000)
#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001)
#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002)
#define NVCC7E_SET_COMPOSITION_CONTROL_DEPTH 11:4
#define NVCC7E_SET_COMPOSITION_CONTROL_BYPASS 16:16
#define NVCC7E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000)
#define NVCC7E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001)
#define NVCC7E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0)
#define NVCC7E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0
#define NVCC7E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCC7E_SET_KEY_ALPHA (0x000002F8)
#define NVCC7E_SET_KEY_ALPHA_MIN 15:0
#define NVCC7E_SET_KEY_ALPHA_MAX 31:16
#define NVCC7E_SET_KEY_RED_CR (0x000002FC)
#define NVCC7E_SET_KEY_RED_CR_MIN 15:0
#define NVCC7E_SET_KEY_RED_CR_MAX 31:16
#define NVCC7E_SET_KEY_GREEN_Y (0x00000300)
#define NVCC7E_SET_KEY_GREEN_Y_MIN 15:0
#define NVCC7E_SET_KEY_GREEN_Y_MAX 31:16
#define NVCC7E_SET_KEY_BLUE_CB (0x00000304)
#define NVCC7E_SET_KEY_BLUE_CB_MIN 15:0
#define NVCC7E_SET_KEY_BLUE_CB_MAX 31:16
#define NVCC7E_SET_PRESENT_CONTROL (0x00000308)
#define NVCC7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVCC7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVCC7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVCC7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVCC7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVCC7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVCC7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C)
#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330)
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE (0x00000334)
#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0
#define NVCC7E_SET_SCAN_DIRECTION (0x0000033C)
#define NVCC7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0
#define NVCC7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000)
#define NVCC7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001)
#define NVCC7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1
#define NVCC7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000)
#define NVCC7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001)
#define NVCC7E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2
#define NVCC7E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000)
#define NVCC7E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001)
#define NVCC7E_SET_TIMESTAMP_ORIGIN_LO (0x00000340)
#define NVCC7E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NVCC7E_SET_TIMESTAMP_ORIGIN_HI (0x00000344)
#define NVCC7E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NVCC7E_SET_UPDATE_TIMESTAMP_LO (0x00000348)
#define NVCC7E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NVCC7E_SET_UPDATE_TIMESTAMP_HI (0x0000034C)
#define NVCC7E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NVCC7E_SET_INTERLOCK_FLAGS (0x00000370)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#define NVCC7E_SET_CHROMA_VER (0x00000378)
#define NVCC7E_SET_CHROMA_VER_POSITION 1:0
#define NVCC7E_SET_CHROMA_VER_POSITION_TOP (0x00000000)
#define NVCC7E_SET_CHROMA_VER_POSITION_CENTER (0x00000001)
#define NVCC7E_SET_CHROMA_VER_POSITION_BOTTOM (0x00000002)
#define NVCC7E_SET_CHROMA_VER_USE_SWPOSITION 2:2
#define NVCC7E_SET_CHROMA_VER_USE_SWPOSITION_FALSE (0x00000000)
#define NVCC7E_SET_CHROMA_VER_USE_SWPOSITION_TRUE (0x00000001)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD 4:3
#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_0 (0x00000000)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_QUARTER (0x00000001)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_HALF (0x00000002)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN 6:5
#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_0 (0x00000000)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_QUARTER (0x00000001)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_HALF (0x00000002)
#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
#define NVCC7E_SET_CHROMA_VER_USE_SWWEIGHTS 7:7
#define NVCC7E_SET_CHROMA_VER_USE_SWWEIGHTS_FALSE (0x00000000)
#define NVCC7E_SET_CHROMA_VER_USE_SWWEIGHTS_TRUE (0x00000001)
#define NVCC7E_SET_CHROMA_HOR (0x0000037C)
#define NVCC7E_SET_CHROMA_HOR_REPLACE_ODD 0:0
#define NVCC7E_SET_CHROMA_HOR_REPLACE_ODD_DISABLE (0x00000000)
#define NVCC7E_SET_CHROMA_HOR_REPLACE_ODD_ENABLE (0x00000001)
#define NVCC7E_SET_CHROMA_HOR_REPLACE_EVEN 1:1
#define NVCC7E_SET_CHROMA_HOR_REPLACE_EVEN_DISABLE (0x00000000)
#define NVCC7E_SET_CHROMA_HOR_REPLACE_EVEN_ENABLE (0x00000001)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD 3:2
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_0 (0x00000000)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_QUARTER (0x00000001)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_HALF (0x00000002)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN 5:4
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_0 (0x00000000)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_QUARTER (0x00000001)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_HALF (0x00000002)
#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
#define NVCC7E_SET_CHROMA_HOR_USE_SWWEIGHTS 6:6
#define NVCC7E_SET_CHROMA_HOR_USE_SWWEIGHTS_FALSE (0x00000000)
#define NVCC7E_SET_CHROMA_HOR_USE_SWWEIGHTS_TRUE (0x00000001)
#define NVCC7E_SET_EXT_PACKET_CONTROL (0x00000398)
#define NVCC7E_SET_EXT_PACKET_CONTROL_ENABLE 0:0
#define NVCC7E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_EXT_PACKET_CONTROL_LOCATION 4:4
#define NVCC7E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000)
#define NVCC7E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001)
#define NVCC7E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8
#define NVCC7E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000)
#define NVCC7E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001)
#define NVCC7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12
#define NVCC7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000)
#define NVCC7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001)
#define NVCC7E_SET_EXT_PACKET_CONTROL_SIZE 27:16
#define NVCC7E_SET_EXT_PACKET_DATA (0x0000039C)
#define NVCC7E_SET_EXT_PACKET_DATA_DB0 7:0
#define NVCC7E_SET_EXT_PACKET_DATA_DB1 15:8
#define NVCC7E_SET_EXT_PACKET_DATA_DB2 23:16
#define NVCC7E_SET_EXT_PACKET_DATA_DB3 31:24
#define NVCC7E_SET_WIN_INFOFRAME (0x000003A0)
#define NVCC7E_SET_WIN_INFOFRAME_FID 7:0
#define NVCC7E_SET_WIN_INFOFRAME_EN 16:16
#define NVCC7E_SET_WIN_INFOFRAME_EN_DISABLE (0x00000000)
#define NVCC7E_SET_WIN_INFOFRAME_EN_ENABLE (0x00000001)
#define NVCC7E_SET_FMT_COEFFICIENT_C00 (0x00000400)
#define NVCC7E_SET_FMT_COEFFICIENT_C00_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C01 (0x00000404)
#define NVCC7E_SET_FMT_COEFFICIENT_C01_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C02 (0x00000408)
#define NVCC7E_SET_FMT_COEFFICIENT_C02_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C03 (0x0000040C)
#define NVCC7E_SET_FMT_COEFFICIENT_C03_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C10 (0x00000410)
#define NVCC7E_SET_FMT_COEFFICIENT_C10_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C11 (0x00000414)
#define NVCC7E_SET_FMT_COEFFICIENT_C11_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C12 (0x00000418)
#define NVCC7E_SET_FMT_COEFFICIENT_C12_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C13 (0x0000041C)
#define NVCC7E_SET_FMT_COEFFICIENT_C13_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C20 (0x00000420)
#define NVCC7E_SET_FMT_COEFFICIENT_C20_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C21 (0x00000424)
#define NVCC7E_SET_FMT_COEFFICIENT_C21_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C22 (0x00000428)
#define NVCC7E_SET_FMT_COEFFICIENT_C22_VALUE 20:0
#define NVCC7E_SET_FMT_COEFFICIENT_C23 (0x0000042C)
#define NVCC7E_SET_FMT_COEFFICIENT_C23_VALUE 20:0
#define NVCC7E_SET_ILUT_CONTROL (0x00000440)
#define NVCC7E_SET_ILUT_CONTROL_INTERPOLATE 0:0
#define NVCC7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCC7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCC7E_SET_ILUT_CONTROL_MIRROR 1:1
#define NVCC7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCC7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCC7E_SET_ILUT_CONTROL_MODE 3:2
#define NVCC7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVCC7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVCC7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVCC7E_SET_ILUT_CONTROL_SIZE 18:8
#define NVCC7E_SET_CSC00CONTROL (0x0000045C)
#define NVCC7E_SET_CSC00CONTROL_ENABLE 0:0
#define NVCC7E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC00COEFFICIENT_C00 (0x00000460)
#define NVCC7E_SET_CSC00COEFFICIENT_C00_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C01 (0x00000464)
#define NVCC7E_SET_CSC00COEFFICIENT_C01_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C02 (0x00000468)
#define NVCC7E_SET_CSC00COEFFICIENT_C02_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C03 (0x0000046C)
#define NVCC7E_SET_CSC00COEFFICIENT_C03_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C10 (0x00000470)
#define NVCC7E_SET_CSC00COEFFICIENT_C10_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C11 (0x00000474)
#define NVCC7E_SET_CSC00COEFFICIENT_C11_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C12 (0x00000478)
#define NVCC7E_SET_CSC00COEFFICIENT_C12_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C13 (0x0000047C)
#define NVCC7E_SET_CSC00COEFFICIENT_C13_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C20 (0x00000480)
#define NVCC7E_SET_CSC00COEFFICIENT_C20_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C21 (0x00000484)
#define NVCC7E_SET_CSC00COEFFICIENT_C21_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C22 (0x00000488)
#define NVCC7E_SET_CSC00COEFFICIENT_C22_VALUE 20:0
#define NVCC7E_SET_CSC00COEFFICIENT_C23 (0x0000048C)
#define NVCC7E_SET_CSC00COEFFICIENT_C23_VALUE 20:0
#define NVCC7E_SET_CSC0LUT_FP_NORM_SCALE (0x00000490)
#define NVCC7E_SET_CSC0LUT_FP_NORM_SCALE_VALUE 31:0
#define NVCC7E_SET_CSC0LUT_CONTROL (0x000004A0)
#define NVCC7E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0
#define NVCC7E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC0LUT_CONTROL_MIRROR 1:1
#define NVCC7E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCC7E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCC7E_SET_CSC0LUT_CONTROL_ENABLE 4:4
#define NVCC7E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE 6:5
#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
#define NVCC7E_SET_CSC01CONTROL (0x000004BC)
#define NVCC7E_SET_CSC01CONTROL_ENABLE 0:0
#define NVCC7E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC01COEFFICIENT_C00 (0x000004C0)
#define NVCC7E_SET_CSC01COEFFICIENT_C00_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C01 (0x000004C4)
#define NVCC7E_SET_CSC01COEFFICIENT_C01_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C02 (0x000004C8)
#define NVCC7E_SET_CSC01COEFFICIENT_C02_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C03 (0x000004CC)
#define NVCC7E_SET_CSC01COEFFICIENT_C03_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C10 (0x000004D0)
#define NVCC7E_SET_CSC01COEFFICIENT_C10_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C11 (0x000004D4)
#define NVCC7E_SET_CSC01COEFFICIENT_C11_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C12 (0x000004D8)
#define NVCC7E_SET_CSC01COEFFICIENT_C12_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C13 (0x000004DC)
#define NVCC7E_SET_CSC01COEFFICIENT_C13_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C20 (0x000004E0)
#define NVCC7E_SET_CSC01COEFFICIENT_C20_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C21 (0x000004E4)
#define NVCC7E_SET_CSC01COEFFICIENT_C21_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C22 (0x000004E8)
#define NVCC7E_SET_CSC01COEFFICIENT_C22_VALUE 20:0
#define NVCC7E_SET_CSC01COEFFICIENT_C23 (0x000004EC)
#define NVCC7E_SET_CSC01COEFFICIENT_C23_VALUE 20:0
#define NVCC7E_SET_TMO_CONTROL (0x00000500)
#define NVCC7E_SET_TMO_CONTROL_INTERPOLATE 0:0
#define NVCC7E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCC7E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCC7E_SET_TMO_CONTROL_SAT_MODE 3:2
#define NVCC7E_SET_TMO_CONTROL_SIZE 18:8
#define NVCC7E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508)
#define NVCC7E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16
#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C)
#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510)
#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0
#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16
#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514)
#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCC7E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518)
#define NVCC7E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0
#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C)
#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCC7E_SET_CSC10CONTROL (0x0000053C)
#define NVCC7E_SET_CSC10CONTROL_ENABLE 0:0
#define NVCC7E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC10COEFFICIENT_C00 (0x00000540)
#define NVCC7E_SET_CSC10COEFFICIENT_C00_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C01 (0x00000544)
#define NVCC7E_SET_CSC10COEFFICIENT_C01_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C02 (0x00000548)
#define NVCC7E_SET_CSC10COEFFICIENT_C02_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C03 (0x0000054C)
#define NVCC7E_SET_CSC10COEFFICIENT_C03_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C10 (0x00000550)
#define NVCC7E_SET_CSC10COEFFICIENT_C10_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C11 (0x00000554)
#define NVCC7E_SET_CSC10COEFFICIENT_C11_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C12 (0x00000558)
#define NVCC7E_SET_CSC10COEFFICIENT_C12_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C13 (0x0000055C)
#define NVCC7E_SET_CSC10COEFFICIENT_C13_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C20 (0x00000560)
#define NVCC7E_SET_CSC10COEFFICIENT_C20_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C21 (0x00000564)
#define NVCC7E_SET_CSC10COEFFICIENT_C21_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C22 (0x00000568)
#define NVCC7E_SET_CSC10COEFFICIENT_C22_VALUE 20:0
#define NVCC7E_SET_CSC10COEFFICIENT_C23 (0x0000056C)
#define NVCC7E_SET_CSC10COEFFICIENT_C23_VALUE 20:0
#define NVCC7E_SET_CSC1LUT_FP_SCALE (0x00000570)
#define NVCC7E_SET_CSC1LUT_FP_SCALE_VALUE 15:0
#define NVCC7E_SET_CSC1LUT_CONTROL (0x00000580)
#define NVCC7E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0
#define NVCC7E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC1LUT_CONTROL_MIRROR 1:1
#define NVCC7E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCC7E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCC7E_SET_CSC1LUT_CONTROL_ENABLE 4:4
#define NVCC7E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE 6:5
#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
#define NVCC7E_SET_CSC11CONTROL (0x0000059C)
#define NVCC7E_SET_CSC11CONTROL_ENABLE 0:0
#define NVCC7E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_CSC11CONTROL_LEVEL 7:2
#define NVCC7E_SET_CSC11COEFFICIENT_C00 (0x000005A0)
#define NVCC7E_SET_CSC11COEFFICIENT_C00_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C01 (0x000005A4)
#define NVCC7E_SET_CSC11COEFFICIENT_C01_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C02 (0x000005A8)
#define NVCC7E_SET_CSC11COEFFICIENT_C02_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C03 (0x000005AC)
#define NVCC7E_SET_CSC11COEFFICIENT_C03_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C10 (0x000005B0)
#define NVCC7E_SET_CSC11COEFFICIENT_C10_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C11 (0x000005B4)
#define NVCC7E_SET_CSC11COEFFICIENT_C11_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C12 (0x000005B8)
#define NVCC7E_SET_CSC11COEFFICIENT_C12_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C13 (0x000005BC)
#define NVCC7E_SET_CSC11COEFFICIENT_C13_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C20 (0x000005C0)
#define NVCC7E_SET_CSC11COEFFICIENT_C20_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C21 (0x000005C4)
#define NVCC7E_SET_CSC11COEFFICIENT_C21_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C22 (0x000005C8)
#define NVCC7E_SET_CSC11COEFFICIENT_C22_VALUE 20:0
#define NVCC7E_SET_CSC11COEFFICIENT_C23 (0x000005CC)
#define NVCC7E_SET_CSC11COEFFICIENT_C23_VALUE 20:0
#define NVCC7E_SET_CLAMP_RANGE (0x000005D0)
#define NVCC7E_SET_CLAMP_RANGE_LOW 15:0
#define NVCC7E_SET_CLAMP_RANGE_HIGH 31:16
#define NVCC7E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004)
#define NVCC7E_SW_RESERVED_VALUE 31:0
#define NVCC7E_SET_DIRTY_RECT_SIZE (0x000005E4)
#define NVCC7E_SET_DIRTY_RECT_SIZE_WIDTH 15:0
#define NVCC7E_SET_DIRTY_RECT_SIZE_HEIGHT 31:16
#define NVCC7E_SET_DIRTY_RECT_POSITION (0x000005E8)
#define NVCC7E_SET_DIRTY_RECT_POSITION_X 15:0
#define NVCC7E_SET_DIRTY_RECT_POSITION_Y 31:16
#define NVCC7E_SET_SUPERFRAME (0x000005EC)
#define NVCC7E_SET_SUPERFRAME_ENABLE 0:0
#define NVCC7E_SET_SUPERFRAME_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SUPERFRAME_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_SUPERFRAME_MODE 2:1
#define NVCC7E_SET_SUPERFRAME_MODE_FIXED (0x00000000)
#define NVCC7E_SET_SUPERFRAME_MODE_DYNAMIC (0x00000001)
#define NVCC7E_SET_SUPERFRAME_MODE_SW (0x00000003)
#define NVCC7E_SET_SUPERFRAME_RATIO_IN 15:8
#define NVCC7E_SET_SUPERFRAME_RATIO_OUT 23:16
#define NVCC7E_SET_SUPERFRAME_START_COUNT 31:24
#define NVCC7E_SET_INFOFRAME_CTRL(b) (0x000005F0 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_CTRL_ENABLE 0:0
#define NVCC7E_SET_INFOFRAME_CTRL_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_INFOFRAME_CTRL_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION 5:4
#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000)
#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001)
#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002)
#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID 30:16
#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31
#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000)
#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001)
#define NVCC7E_SET_INFOFRAME_HEADER(b) (0x000005F8 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_HEADER_HB0 7:0
#define NVCC7E_SET_INFOFRAME_HEADER_HB1 15:8
#define NVCC7E_SET_INFOFRAME_HEADER_HB2 23:16
#define NVCC7E_SET_INFOFRAME_HEADER_HB3 31:24
#define NVCC7E_SET_INFOFRAME_DATA0(b) (0x00000600 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA0_DB0 7:0
#define NVCC7E_SET_INFOFRAME_DATA0_DB1 15:8
#define NVCC7E_SET_INFOFRAME_DATA0_DB2 23:16
#define NVCC7E_SET_INFOFRAME_DATA0_DB3 31:24
#define NVCC7E_SET_INFOFRAME_DATA1(b) (0x00000608 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA1_DB4 7:0
#define NVCC7E_SET_INFOFRAME_DATA1_DB5 15:8
#define NVCC7E_SET_INFOFRAME_DATA1_DB6 23:16
#define NVCC7E_SET_INFOFRAME_DATA1_DB7 31:24
#define NVCC7E_SET_INFOFRAME_DATA2(b) (0x00000610 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA2_DB8 7:0
#define NVCC7E_SET_INFOFRAME_DATA2_DB9 15:8
#define NVCC7E_SET_INFOFRAME_DATA2_DB10 23:16
#define NVCC7E_SET_INFOFRAME_DATA2_DB11 31:24
#define NVCC7E_SET_INFOFRAME_DATA3(b) (0x00000618 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA3_DB12 7:0
#define NVCC7E_SET_INFOFRAME_DATA3_DB13 15:8
#define NVCC7E_SET_INFOFRAME_DATA3_DB14 23:16
#define NVCC7E_SET_INFOFRAME_DATA3_DB15 31:24
#define NVCC7E_SET_INFOFRAME_DATA4(b) (0x00000620 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA4_DB16 7:0
#define NVCC7E_SET_INFOFRAME_DATA4_DB17 15:8
#define NVCC7E_SET_INFOFRAME_DATA4_DB18 23:16
#define NVCC7E_SET_INFOFRAME_DATA4_DB19 31:24
#define NVCC7E_SET_INFOFRAME_DATA5(b) (0x00000628 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA5_DB20 7:0
#define NVCC7E_SET_INFOFRAME_DATA5_DB21 15:8
#define NVCC7E_SET_INFOFRAME_DATA5_DB22 23:16
#define NVCC7E_SET_INFOFRAME_DATA5_DB23 31:24
#define NVCC7E_SET_INFOFRAME_DATA6(b) (0x00000630 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA6_DB24 7:0
#define NVCC7E_SET_INFOFRAME_DATA6_DB25 15:8
#define NVCC7E_SET_INFOFRAME_DATA6_DB26 23:16
#define NVCC7E_SET_INFOFRAME_DATA6_DB27 31:24
#define NVCC7E_SET_INFOFRAME_DATA7(b) (0x00000638 + (b)*0x00000004)
#define NVCC7E_SET_INFOFRAME_DATA7_DB28 7:0
#define NVCC7E_SET_INFOFRAME_DATA7_DB29 15:8
#define NVCC7E_SET_INFOFRAME_DATA7_DB30 23:16
#define NVCC7E_SET_INFOFRAME_DATA7_DB31 31:24
#define NVCC7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690)
#define NVCC7E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000)
#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcc7e_h

33
src/common/sdk/nvidia/inc/ctrl/ctrla26f.h → src/common/sdk/nvidia/inc/class/clceb0.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,33 +21,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef clceb0_h_
#define clceb0_h_
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrla26f.finn
//
#define NVCEB0_VIDEO_DECODER (0x0000CEB0)
/* GK20A_GPFIFO control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#define NVA26F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xA26F, NVA26F_CTRL_##cat, idx)
/* GK20A_GPFIFO command categories (6bits) */
#define NVA26F_CTRL_RESERVED (0x00)
/*
* NVA26F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NVA26F_CTRL_CMD_NULL (0xa26f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID << 8) | 0x0" */
#endif // clceb0_h

40
src/common/sdk/nvidia/inc/ctrl/ctrlca6f.h → src/common/sdk/nvidia/inc/class/clceb7.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,40 +19,12 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
*/
#pragma once
#ifndef clceb7_h_
#define clceb7_h_
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlca6f.finn
//
#define NVCEB7_VIDEO_ENCODER (0x0000CEB7)
#include "nvcfg_sdk.h"
/* BLACKWELL_CHANNEL_GPFIFO_B control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVCA6F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC36F, NVCA6F_CTRL_##cat, idx)
/* BLACKWELL_CHANNEL_GPFIFO_B command categories (6bits) */
#define NVCA6F_CTRL_RESERVED (0x00)
#define NVCA6F_CTRL_GPFIFO (0x01)
/*
* NVCA6F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned is: NV_OK
*/
#define NVCA6F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
#endif // clceb7_h

30
src/common/sdk/nvidia/inc/class/clced0.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clced0_h_
#define _clced0_h_
#define NVCED0_VIDEO_NVJPG (0x0000CED0)
#endif // _clced0_h

30
src/common/sdk/nvidia/inc/class/clcefa.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcefa_h_
#define _clcefa_h_
#define NVCEFA_VIDEO_OFA (0x0000CEFA)
#endif // _clcefa_h

29
src/common/sdk/nvidia/inc/class/cld1b0.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef cld1b0_h_
#define cld1b0_h_
#define NVD1B0_VIDEO_DECODER (0x0000D1B0)
#endif // cld1b0_h

26
src/common/sdk/nvidia/inc/class/cld1b7.h Normal file
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@@ -0,0 +1,26 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef cld1b7_h_
#define cld1b7_h_
#define NVD1B7_VIDEO_ENCODER (0x0000D1B7)
#endif // cld1b7_

26
src/common/sdk/nvidia/inc/class/cld1fa.h Normal file
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@@ -0,0 +1,26 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef cld1fa_h_
#define cld1fa_h_
#define NVD1FA_VIDEO_OFA (0x0000D1FA)
#endif // cld1fa_h

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,8 +68,7 @@ typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS {
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC 0x00000005
/*
* NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO

45
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,12 +31,14 @@
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl2080/ctrl2080nvlink_common.h"
#include "nvlimits.h"
/* NV01_ROOT (client) GPU control commands and parameters */
typedef NV2080_CTRL_NVLINK_LINK_MASK NV0000_CTRL_NVLINK_LINK_MASK;
/*
* NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
*
@@ -122,6 +124,18 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
* System-on-Chip (SOC).
* NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED
* When ATS is enabled on the system.
* NV0000_CTRL_GPU_ID_INFO_SOC_TYPE
* This field indicates the GPU type for SOC-based GPUs. Legal values
* for this field include:
* NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_NONE
* This value indicates the GPU is not an SOC GPU.
* NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY
* This value indicates the GPU is an SOC display GPU.
* NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_IGPU
* This value indicates the GPU is an iGPU.
* NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY_AND_IGPU
* This value indicates the GPU is both an iGPU and an SOC
* display GPU.
* [out] deviceInstance
* This parameter returns the broadcast device instance number associated
* with the specified GPU. This value can be used to instantiate
@@ -192,6 +206,11 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE 8:7
#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_NONE (0x00000000U)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY (0x00000001U)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_IGPU (0x00000002U)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY_AND_IGPU (0x00000003U)
/*
* NV0000_CTRL_CMD_GPU_GET_INIT_STATUS
@@ -277,6 +296,13 @@ typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
* NV0000_CTRL_CMD_GPU_GET_UUID_INFO.
* The valid entries in excludedGpuIds[] are contiguous, with a value
* of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries.
* gpuFlags[]
* This parameter returns flags for each valid entry in the gpuIds[]
* table. Note that excluded GPUs do not have a gpuFlags[] entry.
* Valid flag values include:
* NV0000_CTRL_GPU_PROBED_ID_INFO_FLAGS_SOC_DISPLAY
* When TRUE this flag indicates the GPU supports SOC Display
* functionality.
*
* Possible status values returned are:
* NV_OK
@@ -290,8 +316,14 @@ typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
NvU32 excludedGpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
NvU32 gpuFlags[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
} NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS;
/* valid flags values */
#define NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY 0:0
#define NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY_FALSE (0x00000000U)
#define NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY_TRUE (0x00000001U)
/*
* NV0000_CTRL_CMD_GPU_GET_PCI_INFO
*
@@ -318,7 +350,7 @@ typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU)
@@ -803,9 +835,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
NvU32 enableMask;
} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS;
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U)
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U)
/*
* NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT
@@ -831,7 +861,8 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS {
NvU32 gpuId;
NvU32 mask;
NvU32 mask; // This field will be deprecated in the future, please use links
NV_DECLARE_ALIGNED(NV0000_CTRL_NVLINK_LINK_MASK links, 8);
NvBool bSkipHwNvlinkDisable;
} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS;

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -554,6 +554,7 @@ typedef struct NV0000_CTRL_NVD_GET_NVLOG_PARAMS {
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS 1
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS 2
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS 3
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_RC_ERROR 4
// pseudo register enums attribute content
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY 0x00000000

20
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1572,24 +1572,6 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS {
#define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U)
/*
* NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS
*
* This command allows privileged users to update the values of
* security settings governing RM behavior.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT,
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_PERMISSIONS
*
* Please note: as implied above, administrator privileges are
* required to modify security settings.
*/
#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */
#define GPS_MAX_COUNTERS_PER_BLOCK 32U
#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U)

63
src/common/sdk/nvidia/inc/ctrl/ctrl003e.h
View File

@@ -30,6 +30,7 @@
// Source file: ctrl/ctrl003e.finn
//
#include "ctrl0041.h"
#include "ctrl/ctrlxxxx.h"
/* NV01_MEMORY_SYSTEM control commands and parameters */
@@ -57,69 +58,13 @@
/*
* NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR
*
* This command returns attributes associated with the memory object
* at the given offset. The architecture dependent return parameter
* comprFormat determines the meaningfulness (or not) of comprOffset.
*
* This call is currently only supported in the MODS environment.
*
* memOffset
* This parameter is both an input and an output. As input, this
* parameter holds an offset into the memory surface. The return
* value is the physical address of the surface at the given offset.
* memFormat
* This parameter returns the memory kind of the surface.
* comprOffset
* This parameter returns the compression offset of the surface.
* comprFormat
* This parameter returns the type of compression of the surface.
* gpuCacheAttr
* gpuCacheAttr returns the gpu cache attribute of the surface.
* Legal return values for this field are
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
* gpuP2PCacheAttr
* gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface.
* Legal return values for this field are
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
* mmuContext
* mmuContext returns the requested type of physical address
* Legal return values for this field are
* TEGRA_VASPACE_A -- return the non-GPU device physical address ( the system physical address itself) for Tegra engines.
* returns the system physical address, may change to use a class value in future.
* FERMI_VASPACE_A -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines.
* 0 -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines.
* use of zero may be deprecated in future.
* contigSegmentSize
* If the underlying surface is physically contiguous, this parameter
* returns the size in bytes of the piece of memory starting from
* the offset specified in the memOffset parameter extending to the last
* byte of the surface.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_BAD_OBJECT_HANDLE
* NVOS_STATUS_BAD_OBJECT_PARENT
* NVOS_STATUS_NOT_SUPPORTED
* See NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR
*
*/
#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x3e0101) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */
#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR
#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x1U)
typedef NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS;
typedef struct NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 memOffset, 8);
NvU32 memFormat;
NvU32 comprOffset;
NvU32 comprFormat;
NvU32 gpuCacheAttr;
NvU32 gpuP2PCacheAttr;
NvU32 mmuContext;
NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8);
} NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS;
/* valid gpuCacheAttr return values */
#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000)

45
src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -183,6 +183,13 @@ typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS {
* This surface has compression resources bound to it.
* NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL
* This surface has zcull resources bound to it.
* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_LO
* This index is used to request the low 32 bits of the physically allocated
* size (64 bit value) in units of bytes for the associated surface.
* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_HI
* This index is used to request the high 32 bits of the physically
* allocated size (64 bit value) in units of bytes for the associated
* surface.
* NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE
* This index is used to request the compression coverage (if any)
* in units of 64K for the associated surface. A value of zero indicates
@@ -192,7 +199,8 @@ typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS {
* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE
* This index is used to request the physically allocated size in units
* of 4K(NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR) for the associated
* surface.
* surface. This interface is obsoleted by
* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_{LO,HI}.
* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR
* This index is used to request the surface attribute field. The returned
* field value can be decoded using the NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_*
@@ -205,6 +213,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO;
/* valid surface info index values */
#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001)
#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_LO (0x00000002)
#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_HI (0x00000003)
#define NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE (0x00000005)
#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE (0x00000007)
#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR (0x00000008)
@@ -450,4 +460,35 @@ typedef struct NV0041_CTRL_CMD_GET_TAG_PARAMS {
NvU32 tag; /* [out] */
} NV0041_CTRL_CMD_GET_TAG_PARAMS;
/*
* NV0041_CTRL_CMD_MAP_MEMORY_FOR_GPU_ACCESS
*
* Map system memory into IOMMU VAS of a GPU described by hSubdevice
* Returns the address
*
*/
#define NV0041_CTRL_CMD_MAP_MEMORY_FOR_GPU_ACCESS (0x410122) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS {
NvHandle hSubdevice;
NV_DECLARE_ALIGNED(NvU64 address, 8);
} NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS;
/*
* NV0041_CTRL_CMD_UNMAP_MEMORY_FOR_GPU_ACCESS
*
* See NV0041_CTRL_CMD_MAP_MEMORY_FOR_GPU_ACCESS
*
*/
#define NV0041_CTRL_CMD_UNMAP_MEMORY_FOR_GPU_ACCESS (0x410153) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID (0x53U)
typedef struct NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS {
NvHandle hSubdevice;
} NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS;
/* _ctrl0041_h_ */

189
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -163,7 +163,7 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR 13:13
#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR 13:13
#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14
@@ -285,8 +285,6 @@ typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS {
#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_1 (0x00000000U)
#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_2 (0x00000001U)
/*
* NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS
*
@@ -349,9 +347,9 @@ typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U
#define NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID (0x44U)
@@ -1464,7 +1462,184 @@ typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS {
NvU32 displayId;
} NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES
*
* @brief
* This command can be used to program the Rectangle regions info into
* Region RAM. These Rectangle regions are then used as regions of interest
* for Tell Tale and Frozen Frame detection.
*
* Some NVDisplay hardware has an internal RAM to support TellTale(TT)
* and Frozen Frame(FF) features. Each entry in this RAM is simply defined
* as a rectangle (x/y position, width and height). RM will load the region
* RAM with rectangle entries using PDISP registers.
*
* Several new Core/Window methods have been added. These methods can be
* programmed to specify which rectangle resources would be enabled and inform
* hw to start using for TT/FF checking. There are also methods that can be used
* to configure the manner of checking (e.g., for frozen frame detection, how
* many regions need to be frozen for how many frames before it's considered as
* a fault). As part of these methods, need to specify the index of the region
* RAM entry (rectangle) that needs to be checked. This ID is already specified
* for each rectangle as part of the info that was programmed by RM to Region RAM.
*
* The rectangles loaded onto Region RAM are not specifically tied to the current
* mode, and do not have to be coupled with only one single mode. Based on the
* current raster size, it is expected that the RM clients would choose the
* Rectangles that are within the raster size. Once TT/FF checking is enabled,
* Display HW continuously checks and will raise an interrupt event if detects an
* error case. If a rectangle resource is chosen that "doesn't fit" the current
* raster size, overlaps with another rectangle resource, etc, then HW will
* generate an exception for these invalid states.
*
* @params
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* numRectangles
* This parameter specifies the number of rectangles whose region info
* has been passed as part of this control call
* rectanglesInfo::rectangleID
* This parameter provides the ID of the rectangle which will be used
* to identify the rectangle during methods programming for TellTale
* or Frozen Frame detection.
* rectanglesInfo::xCoordinate
* This parameter specifies the x-coordinate of the top left corner of
* the rectangle in the viewport.
* rectanglesInfo::yCoordinate
* This parameter specifies the y-coordinate of the top left corner of
* the rectangle in the viewport.
* rectanglesInfo::width
* This parameter specifies the width of the rectangle.
* rectanglesInfo::height
* This parameter specifies the height of the rectangle.
*
* Possible status values returned are:
* NV_OK - Upon successfully programming Rectangles info to Region RAM
* NV_ERR_INVALID_ARGUMENT - When incorrect values are passed in arguments
*/
#define NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES (0x731177U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_MAX_REGION_RAM_RECTANGLES 16U
#define NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS_MESSAGE_ID (0x77U)
typedef struct NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS {
NvU32 subDeviceInstance;
NvU8 numRectangles;
struct {
NvU8 rectangleID;
NvU16 xCoordinate;
NvU16 yCoordinate;
NvU16 width;
NvU16 height;
} rectanglesInfo[NV0073_CTRL_CMD_SYSTEM_MAX_REGION_RAM_RECTANGLES];
} NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS
*
* This command can be used to set the interrupt handling mechanism (One-time
* or Continuous) of TellTale and FrozenFrame/Overlap events. Also, this command
* can be used to Enable/Disable the safety interrupts.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* tellTaleEvents
* The 'mode' variable holds the interrupt configuration values for
* TellTale events. Clients can specify whether the interrupt needs to
* be Disabled or Enabled Continuously or Enabled Only Once using the
* NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_* macros. ENABLE_ONLY_ONCE
* helps avoid interrupt storm by disabling the interrupt after the first
* event since Safety Interrupts are generated per frame.
* The 'specified' field should be used to specify if the 'mode' value at
* that index should be programmed as part of the control call handling
* function. This helps if Clients don't want to update the TellTale
* interrupt configuration of a particular tile in this instance of the
* control call invocation. If it is set to NV_TRUE, the 'mode' value
* will be programmed. If NV_FALSE, 'mode' value will not be programmed.
* frozenFrameEvents
* The 'mode' variable holds the interrupt configuration values for
* FrozenFrame events. Clients can specify whether the interrupt needs to
* be Disabled or Enabled Continuously or Enabled Only Once using the
* NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_* macros. ENABLE_ONLY_ONCE
* helps avoid interrupt storm by disabling the interrupt after the first
* event since Safety Interrupts are generated per frame.
* The 'specified' field should be used to specify if the 'mode' value at
* that index should be programmed as part of the control call handling
* function. This helps if Clients don't want to update the Frozen Frame
* interrupt configuration of a particular head in this instance of the
* control call invocation. If it is set to NV_TRUE, the 'mode' value
* will be programmed. If NV_FALSE, 'mode' value will not be programmed.
* overlapEvents
* The 'mode' variable holds the interrupt configuration values for
* Overlap events. Clients can specify whether the interrupt needs to
* be Disabled or Enabled Continuously or Enabled Only Once using the
* NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_* macros. ENABLE_ONLY_ONCE
* helps avoid interrupt storm by disabling the interrupt after the first
* event since Safety Interrupts are generated per frame.
* The 'specified' field should be used to specify if the 'mode' value at
* that index should be programmed as part of the control call handling
* function. This helps if Clients don't want to update the Overlap
* interrupt configuration of a particular tile in this instance of the
* control call invocation. If it is set to NV_TRUE, the 'mode' value
* will be programmed. If NV_FALSE, 'mode' value will not be programmed.
*/
/*
* NOTE: Though we have created tellTaleEvents, frozenFrameEvents and overlapEvents structs as
* arrays holding interrupt 'mode' for each Head/Tile, RM currently does not support
* configuring these interrupts per Head/Tile. This support is planned to be added in RM
* sometime later, but having the structures per Head/Tile helps in future-proofing the
* control call interface.
* Expectation from the clients is to set the same 'mode' value at all the indexes (for
* all Heads/Tiles). This specified 'mode' value will be globally applied for all
Heads/Tiles for now.
*/
#define NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS (0x731178U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS_MESSAGE_ID" */
/*
* Interrupt configuration values for Safety events
*/
#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_DISABLE 0U
#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_ENABLE_CONTINUOUS 1U
#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_ENABLE_ONLY_ONCE 2U
#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_RESERVED 3U
/*
* Head and Tile count used to specify Safety interrupt configuration for each head/tile.
*/
#define NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_HEAD_COUNT 8U
#define NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_TILE_COUNT 8U
#define NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS_MESSAGE_ID (0x78U)
typedef struct NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS {
NvU32 subDeviceInstance;
struct {
NvU8 mode;
NvBool specified;
} tellTaleEvents[NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_TILE_COUNT];
struct {
NvU8 mode;
NvBool specified;
} frozenFrameEvents[NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_HEAD_COUNT];
struct {
NvU8 mode;
NvBool specified;
} overlapEvents[NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_TILE_COUNT];
} NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS;
/*
* NV0073_CTRL_CMD_DFP_SET_FORCE_BLACK_PIXELS
@@ -1478,9 +1653,6 @@ typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS {
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* displayId
* DisplayId of the connected display.
*
* bForceBlackPixels
* To enable or disable black pixel generation.
*
@@ -1496,7 +1668,6 @@ typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS {
typedef struct NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 head;
NvBool bForceBlack;
} NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS;

40
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -1705,7 +1705,9 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* bSupportDPDownSpread
* Returns NV_TRUE if GPU support downspread.
* bAvoidHBR3
* Returns if we need to avoid HBR3 as much as possible
* Returns NV_TRUE if we need to avoid HBR3 as much as possible
* bIsDpTunnelingHwBugWarEnabled
* Returns NV_TRUE if USB4 DP tunneling HW bug WAR is enabled for the chip.
*
* DSC caps
*
@@ -1737,6 +1739,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvBool bUseRgFlushSequence;
NvBool bSupportDPDownSpread;
NvBool bAvoidHBR3;
NvBool bIsDpTunnelingHwBugWarEnabled;
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
@@ -3617,4 +3620,39 @@ typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS {
NV0073_CTRL_DP_USBC_CABLEID_INFO cableIDInfo;
} NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS;
/*
* NV0073_CTRL_CMD_STUFF_DUMMY_SYMBOL_WAR
*
* Some sink devices require extra padding between SDPs. This is programmed for GB20x+ GPUs.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the display for which the control
* is being issued. The display ID must be valid.
* head
* This parameter specifies the head index for the operation.
* bEnable
* Boolean to enable or disable the WAR.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS_MESSAGE_ID (0x8EU)
typedef struct NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 head;
NvBool bEnable;
} NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS;
#define NV0073_CTRL_CMD_STUFF_DUMMY_SYMBOL_WAR (0x73138eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS_MESSAGE_ID" */
/* _ctrl0073dp_h_ */

6
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -56,10 +56,4 @@ typedef NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_
typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR (0x730406U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID (0x6U)
typedef NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS;
/* ctrl0073internal_h */

8
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -2047,6 +2047,12 @@ typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS {
* bDynamicHdrTonemapping
* if bLtmEnable = true, and if set to true, and output is HDR, enable dynamic per frame HDR tonemapping. Set to false by default.
*
* maxDisplayLuminance
* maximum display luminance
*
* luminanceSscalingFactor
* HDR tone mapping luminance scaling factor
*
* Possible status values returned include:
* NV_OK
* NV_ERR_NOT_SUPPORTED
@@ -2068,6 +2074,8 @@ typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS {
NvU16 detailGain;
NvBool bContentAdaptiveBrightness;
NvBool bDynamicHdrTonemapping;
NvU32 maxDisplayLuminance;
NvU32 luminanceScalingFactor;
} NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS;
#define NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID (0xAFU)

32
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1502,38 +1502,6 @@ typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS {
NvU32 minVblankExtension;
} NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR
*
* This command engages the WAR when VR devices are connected,
* where the Pstate switching can cause delay in Vblank callbacks
* reported to KMD, by servicing disp interrupts inline and reporting the
* callbacks to KMD. Without the WAR, there can be stutters during pstate switch.
* Bug#1778552
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* bEngageWAR
* Indicates if inline disp interrupt serving WAR has to be engaged or
* disengaged.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR (0x730187U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS {
NvU32 subDeviceInstance;
NvBool bEngageWAR;
} NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS;
/*

8
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,7 @@
//
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "nvcfg_sdk.h"
/*
* NV0080_CTRL_CMD_BIF_RESET
@@ -47,7 +48,8 @@
* to _SBR, a secondary-bus reset is performed. When set to
* _FUNDAMENTAL, a fundamental reset is performed.
*
* NOTE: _FUNDAMENTAL is not yet supported.
* NOTE: _FUNDAMENTAL is not supported for Blackwell and later chips.
* Use BOOT_DEVICE_FUSE or BOOT_DEVICE reset type instead.
*
* Possible status return values are:
* NV_OK
@@ -73,6 +75,8 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE 0x8
/*
* NV0080_CTRL_BIF_SET_ASPM_FEATURE
*

108
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
View File

@@ -153,114 +153,6 @@ typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS {
NvU32 size;
} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS <Deprecated since Fermi+>
*
* This command allows the caller to group two sets of channels. A channel
* set includes one or more channels. After grouping, the grouped channel IDs
* are set to next to each other in the runlist. This command can be used
* several times to group more than two channels.
*
* Using a NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE after
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the general usage. A
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not
* allowed.
*
* NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS defines the max channels in a
* group.
*
* hChannel1
* This parameter specifies the handle of the channel that belongs to the
* base set of channels.
* hChannel2
* This parameter specifies the handle of the channel that belongs to the
* additional set of channels.
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS (0x801709) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x9" */
typedef struct NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM {
NvHandle hChannel1;
NvHandle hChannel2;
} NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM;
#define NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS (8)
/*
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE <Deprecated since Fermi+>
*
* This command allows the caller to divide the timeslice (DMA_TIMESLICE) of a
* channel between the channels in the group in which the channel resides.
* After applying this command, a timeslice divided channel (group) has a
* short timeslice and repeats more than once in the runlist. The total
* available execution time is not changed.
*
* Using this command after NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the
* general usage. A NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not
* allowed.
*
* hChannel
* This parameter specifies the handle of the channel for the channel
* group to which the divided timeslice operation will apply.
* tsDivisor
* This parameter specifies the timeslice divisor value. This value
* should not exceed NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE (0x80170b) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xB" */
typedef struct NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM {
NvHandle hChannel;
NvU32 tsDivisor;
} NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM;
#define NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR (12)
/*
* NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST <Deprecated since Fermi+>
*
* This command preepmts the engine represented by the specified runlist.
*
* hRunlist
* This parameter specifies the per engine runlist handle. This
* parameter is being retained to maintain backwards compatibility
* with clients that have not transitioned over to using runlists
* on a per subdevice basis.
*
* engineID
* This parameter specifies the engine to be preempted. Engine defines
* can be found in cl2080.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST (0x80170c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xC" */
typedef struct NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS {
NvHandle hRunlist;
NvU32 engineID;
} NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST
*

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -501,7 +501,7 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 100
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 200
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */

16
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
View File

@@ -120,6 +120,8 @@ typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PAR
* Tell Physical RM whether any ZBC-kind surfaces are allocated.
* If PF and all VFs report false, ZBC table can be flushed by Physical RM.
*
* subdevInstance [IN]
* Subdevice instance of the GPU to be checked with
* bZbcReferenced [IN]
* NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
*
@@ -129,7 +131,21 @@ typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PAR
#define NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x0AU)
typedef struct NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
NvU32 subdevInstance;
NvBool bZbcSurfacesExist;
} NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS;
#define NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
NvBool bTeardown;
} NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
#define NV0080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x802046) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
typedef NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
/* ctrl0080internal_h */

16
src/common/sdk/nvidia/inc/ctrl/ctrl00f1.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -96,14 +96,17 @@ typedef struct NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA {
} NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA;
/*
* gpuFabricProbeHandle [IN]
* gpuFabricProbeHandle
* Fabric probe handle of the remote GPU
*
* key [IN]
* key
* Key is used by the GFM in the MCFLA team response as an ID to allow the
* RM to correlate it with the MCFLA team request.
*
* cliqueId [IN]
* bwModeEpoch
* Currently active bwModeEpoch of the remote GPU being attached.
*
* cliqueId
* Clique ID of the remote GPU being attached.
*
* index
@@ -112,6 +115,9 @@ typedef struct NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA {
* exportNodeId
* ID of the exporter node where memory will be imported.
*
* bwMode
* Currently active bwMode of the remote GPU being attached
*
* exportUuid
* Universally unique identifier of the export object. This is extracted
* from a fabric packet.
@@ -119,9 +125,11 @@ typedef struct NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA {
typedef struct NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA {
NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8);
NV_DECLARE_ALIGNED(NvU64 key, 8);
NV_DECLARE_ALIGNED(NvU64 bwModeEpoch, 8);
NvU32 cliqueId;
NvU16 index;
NvU16 exportNodeId;
NvU8 bwMode;
NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN];
} NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA;

10
src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -142,12 +142,20 @@ typedef struct NV00F8_CTRL_GET_INFO_PARAMS {
*
* cliqueId
* Clique ID of the owner GPU
*
* bwModeEpoch
* Currently active bwModeEpoch of of the owner GPU
*
* bwMode
* Currently active bwMode of the owner GPU
*/
typedef struct NV_FABRIC_MEMORY_ATTRS {
NvU32 kind;
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 cliqueId;
NV_DECLARE_ALIGNED(NvU64 bwModeEpoch, 8);
NvU8 bwMode;
} NV_FABRIC_MEMORY_ATTRS;
#define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U)

18
src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -111,6 +111,13 @@ typedef struct NV00FD_CTRL_GET_INFO_PARAMS {
* flags [IN]
* For future use only. Must be zero for now.
*
* subPageOffset [IN]
* For future use only. Must be zero for now.
*/
/*
* Restrictions:
* a. Memory belonging to only NVSwitch P2P supported GPUs
* which can do multicast can be attached
@@ -130,6 +137,7 @@ typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mapOffset, 8);
NV_DECLARE_ALIGNED(NvU64 mapLength, 8);
NvU32 flags;
NvU32 subPageOffset;
} NV00FD_CTRL_ATTACH_MEM_PARAMS;
/*
@@ -215,11 +223,17 @@ typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS {
* Key is used by the GFM in the MCFLA team response as an ID to allow the
* RM to correlate it with the MCFLA team request.
*
* bwModeEpoch [IN]
* Currently active bwModeEpoch of the remote GPU being attached.
*
* cliqueId [IN]
* Clique ID of the remote GPU being attached.
*
* nodeId [IN]
* nodeID from which the remote GPU is being attached.
*
* bwMode [IN]
* Currently active bwMode of the remote GPU being attached.
*/
#define NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU (0xfd0106) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS_MESSAGE_ID" */
@@ -228,8 +242,10 @@ typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS {
typedef struct NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8);
NV_DECLARE_ALIGNED(NvU64 key, 8);
NV_DECLARE_ALIGNED(NvU64 bwModeEpoch, 8);
NvU32 cliqueId;
NvU16 nodeId;
NvU8 bwMode;
} NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS;
/*

3
src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -45,6 +45,7 @@ typedef struct NV00FE_CTRL_OPERATION_MAP {
NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 dmaFlags; // NVOS46_FLAGS
NvU32 kindOverride;
} NV00FE_CTRL_OPERATION_MAP;
typedef struct NV00FE_CTRL_OPERATION_UNMAP {

1399
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h
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12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl2080/ctrl2080clk.finn
//
/* _ctrl2080clk_h_ */
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
@@ -39,3 +36,10 @@
#include "ctrl/ctrl2080/ctrl2080volt.h"
#include "ctrl/ctrl2080/ctrl2080pmumon.h"
#define NV2080_CTRL_CLK_DOMAIN_TEGRA_UNDEFINED (0x00000000U)
#define NV2080_CTRL_CLK_DOMAIN_TEGRA_GPCCLK (0x00000001U)
#define NV2080_CTRL_CLK_DOMAIN_TEGRA_NVDCLK (0x00000002U)
/* _ctrl2080clk_h_ */

17
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -76,6 +76,10 @@
*
* This call shall return NV_ERR_NOT_SUPPORTED if FORCE_PCIE type is used on non-Grace platforms.
*
* bAllowMmap
* mmap support is allowed or not for the specific dmabuf based fd. User can control it.
* That way user can enable mmap for testing/specific use cases and not for any all handles.
*
* handles
* An array of {handle, offset, size} that describes the dma-buf.
* The offsets and sizes must be OS page-size aligned.
@@ -110,12 +114,13 @@ typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO {
#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS {
NvS32 fd;
NvU32 totalObjects;
NvU32 numObjects;
NvU32 index;
NvS32 fd;
NvU32 totalObjects;
NvU32 numObjects;
NvU32 index;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NvU8 mappingType;
NvU8 mappingType;
NvBool bAllowMmap;
NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8);
} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS;

111
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -109,4 +109,113 @@ typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 dramUncTot, 8);
} NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS;
typedef struct eccLocation {
NvU32 location;
NvU32 sublocation;
NvU32 extlocation;
} eccLocation;
/*
* NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY
*
* unit
* The unit the error occurred in
* location
* The location info for the error
* address
* The address of the error
* bIsParity
* True if error is parity error, false if error is SEC-DED error
* count
* The number of uncorrectable unique error counts that occurred
*/
typedef struct NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY {
NvU32 unit;
eccLocation location;
NvU32 address;
NvBool bIsParity;
NvU32 count;
} NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY;
/*
* NV2080_CTRL_CMD_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS
*
* This command is used to query the ECC inforom object and determine the number
* of unique uncorrectable error counts that occurred at an address.
*
* entryCount
* The number of entries
*
* entries
* The array of NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY
*/
#define NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_MAX_COUNT 600
#define NV2080_CTRL_CMD_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS (0x20803402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS {
NvU32 entryCount;
NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY entries[NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_MAX_COUNT];
} NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS;
#define NV2080_CTRL_ECC_ERROR_TYPE_CORRECTED 0
#define NV2080_CTRL_ECC_ERROR_TYPE_UNCORRECTED 1
/*
* NV2080_CTRL_CMD_ECC_INJECT_ERROR
*
* This command is used to inject ECC errors.
*
* unit
* The ECC unit
*
* errorType
* The type of error to be injected
*
* location
* The location within the ECC unit to be injected
*
* flags
* Specific injection flags
*
* address
* Specific injection address for DRAM
*/
#define NV2080_CTRL_CMD_ECC_INJECT_ERROR (0x20803403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_ECC_INJECT_ERROR_PARAMS {
NvU32 unit;
NvU8 errorType;
eccLocation location;
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 address, 8);
} NV2080_CTRL_ECC_INJECT_ERROR_PARAMS;
/*
* NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS
*
* This command is used to query the status of TPC/Channel repair
*
* bTpcRepairPending
* Boolean indicating if TPC repair is pending
* bChannelRepairPending
* Boolean indicating if Channel repair is pending
*/
#define NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS (0x20803404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS {
NvBool bTpcRepairPending;
NvBool bChannelRepairPending;
} NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS;
/* _ctrl2080ecc_h_ */

265
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -293,127 +293,136 @@
* depending on architecture/memory type).
* NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB
* Returns true if FB is not present on this chip
* NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT
* Returns the count of access counter buffers supported by GPU
*/
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
/* valid fb info index values */
#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated
#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE (0x00000001U)
#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE (0x00000002U)
#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT (0x00000003U)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (0x00000004U)
#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE (0x00000005U)
#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT (0x00000006U)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE (0x00000007U)
#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE (0x00000008U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE (0x00000009U)
#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE (0x0000000AU)
#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH (0x0000000BU)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG (0x0000000CU)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE (0x0000000DU)
#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT (0x0000000EU)
#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB (0x00000010U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB (0x00000011U)
#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB (0x00000012U)
#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB (0x00000013U)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK (0x00000014U)
#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE (0x00000015U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE (0x00000016U)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION (0x00000017U)
#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN (0x00000018U)
#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT (0x00000019U)
#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK (0x0000001AU)
#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE (0x0000001BU)
#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID (0x0000001CU)
#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE (0x0000001DU)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START (0x0000001EU)
#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE (0x0000001FU)
#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE (0x00000020U)
#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T (0x00000021U)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT (0x00000022U)
#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT (0x00000023U)
#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE (0x00000024U)
#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE (0x00000025U)
#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE (0x00000026U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE (0x00000027U)
#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED (0x00000028U)
#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE (0x00000029U)
#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT (0x0000002AU)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK (0x0000002BU)
#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED (0x0000002CU)
#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED (0x0000002DU)
#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED (0x0000002EU)
#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002FU)
#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE (0x00000030U)
#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT (0x00000031U)
#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032U)
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U)
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U)
#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U)
#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 (0x00000037U)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 (0x00000038U)
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000039U)
#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated
#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE (0x00000001U)
#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE (0x00000002U)
#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT (0x00000003U)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (0x00000004U)
#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE (0x00000005U)
#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT (0x00000006U)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE (0x00000007U)
#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE (0x00000008U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE (0x00000009U)
#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE (0x0000000AU)
#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH (0x0000000BU)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG (0x0000000CU)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE (0x0000000DU)
#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT (0x0000000EU)
#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW (0x0000000FU) // Deprecated (index reused to return 0)
#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB (0x00000010U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB (0x00000011U)
#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB (0x00000012U)
#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB (0x00000013U)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK (0x00000014U)
#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE (0x00000015U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE (0x00000016U)
#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION (0x00000017U)
#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN (0x00000018U)
#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT (0x00000019U)
#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK (0x0000001AU)
#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE (0x0000001BU)
#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID (0x0000001CU)
#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE (0x0000001DU)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START (0x0000001EU)
#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE (0x0000001FU)
#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE (0x00000020U)
#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T (0x00000021U)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT (0x00000022U)
#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT (0x00000023U)
#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE (0x00000024U)
#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE (0x00000025U)
#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE (0x00000026U)
#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE (0x00000027U)
#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED (0x00000028U)
#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE (0x00000029U)
#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT (0x0000002AU)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK (0x0000002BU)
#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED (0x0000002CU)
#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED (0x0000002DU)
#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED (0x0000002EU)
#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002FU)
#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE (0x00000030U)
#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT (0x00000031U)
#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032U)
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U)
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U)
#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U)
#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 (0x00000037U)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 (0x00000038U)
#define NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT (0x00000039U)
#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO (0x0000003AU)
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x38U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
#define NV2080_CTRL_FB_INFO_INDEX_MAX NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT
/* Intentionally picking a value much bigger than NV2080_CTRL_FB_INFO_INDEX_MAX to prevent VGPU plumbing updates */
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000080U)
/* valid fb RAM type values */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U)
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM (0x00000001U)
#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 (0x00000003U) /* SDDR2 Used on NV43 and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 (0x00000005U) /* GDDR3 Used on NV40 and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 (0x00000007U) /* SDDR3 Used on G9x and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 (0x00000008U) /* GDDR5 Used on GT21x and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U)
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM (0x00000001U)
#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 (0x00000003U) /* SDDR2 Used on NV43 and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 (0x00000005U) /* GDDR3 Used on NV40 and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 (0x00000007U) /* SDDR3 Used on G9x and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 (0x00000008U) /* GDDR5 Used on GT21x and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 (0x0000000CU) /* SDDR4 Used on Maxwell and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X (0x00000010U) /* GDDR5X Used on GP10x */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 (0x00000011U) /* GDDR6 Used on TU10x */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X (0x00000012U) /* GDDR6X Used on GA10x */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 (0x0000000CU) /* SDDR4 Used on Maxwell and later */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X (0x00000010U) /* GDDR5X Used on GP10x */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 (0x00000011U) /* GDDR6 Used on TU10x */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X (0x00000012U) /* GDDR6X Used on GA10x */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 (0x00000015U) /* GDDR7 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 (0x00000015U) /* GDDR7 */
/* valid RAM LOCATION types */
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U)
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U)
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED (0x00000002U)
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U)
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U)
#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED (0x00000002U)
/* valid Memory Vendor ID values */
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG (0x00000001U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA (0x00000002U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA (0x00000003U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON (0x00000004U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA (0x00000005U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX (0x00000006U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL (0x00000007U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND (0x00000008U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT (0x00000009U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON (0x0000000FU)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN (0xFFFFFFFFU)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG (0x00000001U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA (0x00000002U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA (0x00000003U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON (0x00000004U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA (0x00000005U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX (0x00000006U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL (0x00000007U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND (0x00000008U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT (0x00000009U)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON (0x0000000FU)
#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN (0xFFFFFFFFU)
#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED (0x00000000U)
#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED (0x00000001U)
#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED (0x00000002U)
#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED (0x00000000U)
#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED (0x00000001U)
#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED (0x00000002U)
#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_NON_FULLY_COHERENT (0x00000000U)
#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_FULLY_COHERENT (0x00000001U)
/**
* NV2080_CTRL_CMD_FB_GET_INFO
@@ -437,7 +446,7 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV2080_CTRL_CMD_FB_GET_INFO (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_GET_INFO (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
@@ -849,7 +858,7 @@ typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS {
*/
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 18U
typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
@@ -2706,6 +2715,7 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
typedef struct NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS {
NvBool bStaticBar1Enabled;
NvBool bStaticBar1WriteCombined;
NV_DECLARE_ALIGNED(NvU64 staticBar1StartOffset, 8);
NV_DECLARE_ALIGNED(NvU64 staticBar1Size, 8);
} NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS;
@@ -2844,4 +2854,45 @@ typedef struct NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS {
NvBool skipBootTraining;
} NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS;
/*
* NV2080_CTRL_FB_CMD_GET_CARVEOUT_REGION_INFO
*
* This command returns the carveout memory region characteristics.
*
* numCarveoutRegions
* Number of valid regions returned in carveoutRegion[].
* carveoutRegion[].base
* Base address of carveout memory region.
* carveoutRegion[].size
* size of carveout memory region.
* carveoutType
* carveout type for carveout memory region.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_REGION_INFO (0x20801360U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE {
NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM = 0,
NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM_RESERVED = 1,
NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_UEFI = 2,
} NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE;
typedef struct NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE carveoutType;
} NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO;
#define NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES 8U
#define NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS {
NvU32 numCarveoutRegions;
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO carveoutRegion[NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES], 8);
} NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS;
/* _ctrl2080fb_h_ */

23
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -539,20 +539,23 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
#define NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS 8
#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES 200
typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY {
NV_DECLARE_ALIGNED(NvU64 timestampNs, 8);
NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8);
NvU32 timeRunNs;
NvU32 swrlId;
NvU32 targetTimeSlice;
NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8);
NV_DECLARE_ALIGNED(NvU64 cumulativeIdleTime, 8);
NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8);
} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY;
#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS {
NvU32 engineId;
NvU32 count;
struct {
NV_DECLARE_ALIGNED(NvU64 timestampNs, 8);
NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8);
NvU32 timeRunNs;
NvU32 swrlId;
NvU32 targetTimeSlice;
NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8);
NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8);
} entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES];
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES], 8);
NvU32 schedPolicy;
NvU32 arrEnabled;
NvU32 arrAvgFactor;

107
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -112,8 +112,15 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED (0x00000041U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY (0x00000042U)
#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE (0x00000044U)
#define NV2080_CTRL_GPU_INFO_INDEX_COMPR_BIT_BACKING_COPY_TYPE (0x00000045U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000046U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000042U)
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
@@ -228,6 +235,21 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_YES (0x00000001U)
/* valid Non-PASID ATS capability values */
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_YES (0x00000001U)
/* valid coherent GPU memory mode capability values */
#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NONE (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NUMA (0x00000001U)
#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_DRIVER (0x00000002U)
/* valid compression bit backing copy type values */
#define NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_PHYSICAL (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_VIRTUAL (0x00000001U)
/*
* NV2080_CTRL_CMD_GPU_GET_INFO
*
@@ -1380,8 +1402,6 @@ typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS {
NvU32 newConfiguration;
} NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS
*
@@ -2608,7 +2628,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U
#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U
#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU
#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x00000010U
#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U
#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0
@@ -3147,8 +3167,6 @@ typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS {
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_1024MB 0x40000000U
/*
* NV2080_CTRL_GPU_GET_PARTITION_CAPACITY
*
@@ -3859,23 +3877,6 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
NvU32 protection;
} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR
*
* @brief This command is similar to NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR
* but will be used to set the EGM fabric base addr associated with the gpu.
* Note: For EGM FLA, we will be making use of the existing control call i.e
* NV2080_CTRL_CMD_FLA_RANGE
*
*/
#define NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR (0x20800199U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x99U)
typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8);
} NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES
*
@@ -3968,8 +3969,50 @@ typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS;
#define NV2080_CTRL_GPU_SKYLINE_INFO_MAX_SKYLINES 9U
#define NV2080_CTRL_GPU_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12U
/*!
* NV2080_CTRL_GPU_SKYLINE_INFO
* skylineVgpcSize[OUT]
* - TPC count of non-singleton VGPCs
* singletonVgpcMask[OUT]
* - Mask of active Singletons
* maxInstances[OUT]
* - Max allowed instances of this skyline concurrently on a GPU
* computeSizeFlag
* - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline
*/
typedef struct NV2080_CTRL_GPU_SKYLINE_INFO {
NvU8 skylineVgpcSize[NV2080_CTRL_GPU_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS];
NvU32 singletonVgpcMask;
NvU32 maxInstances;
NvU32 computeSizeFlag;
} NV2080_CTRL_GPU_SKYLINE_INFO;
/*!
* NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS
* skylineTable[OUT]
* - TPC count of non-singleton VGPCs
* - Mask of singleton vGPC IDs active
* - Max Instances of this skyline possible concurrently
* - Associated compute size with the indexed skyline
* validEntries[OUT]
* - Number of entries which contain valid info in skylineInfo
*/
#define NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0x9FU)
typedef struct NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS {
NV2080_CTRL_GPU_SKYLINE_INFO skylineTable[NV2080_CTRL_GPU_SKYLINE_INFO_MAX_SKYLINES];
NvU32 validEntries;
} NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO
*
* Retrieves skyline information about the GPU. Params are sized to currently known max
* values, but will need to be modified in the future should that change.
*/
#define NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO (0x2080019fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO
@@ -4146,6 +4189,19 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION 11:8
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_SYSGUID 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN 3
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION 4
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS 5
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_HEALTHY 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_UNHEALTHY 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_LIMITED_CAPACITY 3
/*!
* NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
*
@@ -4177,6 +4233,8 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
* - Unique ID of a set of GPUs within a fabric partition that can perform P2P
* fabricHealthMask[OUT]
* - Mask where bits indicate different status about the health of the fabric
* fabricHealthSummary[OUT]
* - Summary of the Fabric Health
*/
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U)
@@ -4188,6 +4246,7 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8);
NvU32 fabricCliqueId;
NvU32 fabricHealthMask;
NvU8 fabricHealthSummary;
} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */

33
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -402,8 +402,6 @@ typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV2080_CTRL_GR_GET_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE
*
@@ -1208,6 +1206,8 @@ typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
NvU16 virtualGpcId;
NvU16 migratableTpcId;
NvU16 ugpuId;
NvU16 physicalCpcId;
NvU16 virtualTpcId;
} globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT];
NvU16 numSm;
@@ -1715,6 +1715,35 @@ typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE (0xFFU)
#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MASK (0x0U)
/*
* NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL
*
* This command provides an interface to retrieve the throttle contol values of
* various instruction types for a GR engine.
*
* smIssueThrottleCtrlListSize
* This field specifies the number of entries on the caller's
* smIssueThrottleCtrlList.
* When caller passes smIssueThrottleCtrlListSize = 0, all fuse
* values are returned.
* smIssueThrottleCtrlList
* This field specifies a pointer in the caller's address space
* to the buffer into which the throttle control values are to be returned.
*/
#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL (0x2080123dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID" */
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL;
#define NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x3DU)
typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS {
NvU32 smIssueThrottleCtrlListSize;
NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrlList[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE];
} NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS;
/*
* NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID
*

84
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -46,7 +46,7 @@
// log the error and march on.
//
// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
// numQueries[IN]
// numQueries[in]
// - Specifies the number of valid queries that the caller will be passing in
//
// Possible status values returned are:
@@ -69,7 +69,7 @@
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
* gpcCount[OUT]
* gpcCount[out]
* - No. of logical/local GPCs which client can use to create the
* logical/local mask respectively
*/
@@ -79,9 +79,9 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS {
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
* gpcId[IN]
* gpcId[in]
* - Logical/local GPC ID
* chipletGpcMap[OUT]
* chipletGpcMap[out]
* - Returns chiplet GPC ID for legacy case and device monitoring client
* - Returns local GPC ID (== input gpcId) for SMC client
* - Does not support DM attribution case
@@ -93,9 +93,9 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS {
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
* gpcId[IN]
* gpcId[in]
* - Logical/local GPC ID
* tpcMask[OUT]
* tpcMask[out]
* - Returns physical TPC mask for legacy, DM client and SMC cases
* - Does not support DM attribution case
*/
@@ -106,9 +106,9 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS {
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
* gpcId[IN]
* gpcId[in]
* - Logical/local GPC ID
* ppcMask[OUT]
* ppcMask[out]
* - Returns physical PPC mask for legacy, DM client and SMC cases
* - Does not support DM attribution case
*/
@@ -122,14 +122,14 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS {
* it would break driver compatibility !!!
*
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
* swizzId[IN]
* swizzId[in]
* - Swizz ID of partition
* - A DM client with an invalid swizz ID, will fail this call
* - This parameter is not compulsory for an SMC client; the subscription
* itself will do the necessary validation.
* gpcId[IN]
* gpcId[in]
* - Logical/local GPC ID
* chipletGpcMap[OUT]
* chipletGpcMap[out]
* - Returns chiplet GPC ID for legacy case and device monitoring client
* - Returns local GPC ID (== input gpcId) for SMC client
* - Does not support non-attribution case for DM client
@@ -142,9 +142,9 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS {
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
* gpcId[IN]
* gpcId[in]
* - Logical/local GPC ID
* ropMask[OUT]
* ropMask[out]
* - Returns physical ROP mask for legacy, DM client
* - Returns logical ROP mask for SMC
*/
@@ -155,7 +155,7 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS {
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
* chipletSyspipeMask [OUT]
* chipletSyspipeMask [out]
* - Mask of chiplet SMC-IDs for DM client attribution case
* - Mask of local SMC-IDs for SMC client
* - Legacy case returns 1 GR
@@ -167,13 +167,13 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS {
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
* swizzId[IN]
* swizzId[in]
* - Swizz ID of partition
* - A DM client with an invalid swizz ID, will fail this call
* physSyspipeId[GRMGR_MAX_SMC_IDS] [OUT]
* physSyspipeId[GRMGR_MAX_SMC_IDS] [out]
* - Physical SMC-IDs mapped to partition local idx for DM client attribution case
* - Does not support non-attribution case for DM client, SMC clients, legacy case
* physSyspipeIdCount[OUT]
* physSyspipeIdCount[out]
* - Valid count of physSmcIds which has been populated in above array.
* - Failure case will return 0
*/
@@ -185,14 +185,14 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
* swizzId[IN]
* swizzId[in]
* - Swizz ID of partition
* - Mandatory parameter
* - A DM client with an invalid swizz ID, will fail this call
* grIdx[IN]
* grIdx[in]
* - Local grIdx for a partition
* - Mandatory parameter
* gpcEnMask[OUT]
* gpcEnMask[out]
* - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask
* - These Ids should be used as input further
* - Does not support non-attribution case for DM client, SMC clients, legacy case
@@ -205,7 +205,7 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS {
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID
* syspipeId[OUT]
* syspipeId[out]
* - Partition-local GR idx for client subscribed to exec partition
* - Does not support legacy case, DM client, or SMC client subscribed only to partition
*/
@@ -214,9 +214,41 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS {
} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS;
/*!
* queryType[IN]
* NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS
* chipletSyspipeMask [out]
* - Mask of chiplet GFX capable SMC-IDs for DM client attribution case
* - Mask of local GFX capable SMC-IDs for SMC client
* - Legacy case returns GR0 if GFX capable, else 0
* - Does not support attribution case for DM client
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS {
NvU32 chipletSyspipeMask; // param[out] - Mask of chiplet SMC IDs
} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS
* swizzId[in]
* - Swizz ID of partition
* - Mandatory parameter
* - A DM client with an invalid swizz ID, will fail this call
* grIdx[in]
* - Local grIdx for a partition
* - Mandatory parameter
* gpcEnMask[out]
* - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask
* - These Ids should be used as input further
* - Does not support non-attribution case for DM client, SMC clients, legacy case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS {
NvU32 swizzId; // param[in] - swizz ID of partition
NvU32 grIdx; // param[in] - partition local GR ID
NvU32 gpcEnMask; // param[out] - logical enabled GPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS;
/*!
* queryType[in]
* - Use queryType defines to specify what information is being requested
* status[OUT]
* status[out]
* - Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
@@ -237,6 +269,8 @@ typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS {
NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS dmGpcMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS partitionSyspipeIdData;
NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS ropMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS gfxSyspipeMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS gfxGpcMaskData;
} queryData;
} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS;
@@ -259,5 +293,7 @@ typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS {
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK 8
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID 9
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK 10
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GRAPHICS_SYSPIPE_MASK 11
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GFX_CAPABLE_GPC_MASK 12
/* _ctrl2080grmgr_h_ */

178
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,7 @@
//
#include "nvimpshared.h"
#include "ctrl2080nvlink_common.h"
#include "cc_drv.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -39,6 +40,7 @@
#include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */
#include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */
#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */
#include "ctrl/ctrl2080/ctrl2080mc.h" /* NV2080_INTR_* */
#include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrl90f1.h"
@@ -230,6 +232,8 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
NvU16 virtualGpcId;
NvU16 migratableTpcId;
NvU16 ugpuId;
NvU16 physicalCpcId;
NvU16 virtualTpcId;
} globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM];
NvU16 numSm;
@@ -279,7 +283,7 @@ typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS {
} NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 16
#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10
/*!
@@ -820,23 +824,39 @@ typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
NvBool bTeardown;
} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID
*
* This command validates whether a given CTS ID can be used within a GPU Instance by checking
* if the required GPCs can be allocated from the GPU Instance.
*
* ctsId [in]
* The CTS ID to validate
*
* bCheckClientGI [in]
* Validate the CTS ID against the GPU Instance owned by the client.
*
* giComputeSize [in]
* The compute size for the GPU Instance, which determines the number of GPCs in the GPU Instance.
*
* bCtsIdValid [out]
* Returns whether the CTS ID is valid within the specified GPU Instance.
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS_MESSAGE_ID (0x46U)
typedef struct NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS {
NvU32 ctsId;
NvBool bCheckClientGI;
NvU32 giComputeSize;
NvBool bCtsIdValid;
} NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS {
@@ -1435,36 +1455,12 @@ typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS {
* Interrupt table for Kernel RM.
*
* subtreeMap [OUT]
* Subtree range for each NV2080_INTR_CATEGORY.
* Subtree mask for each NV2080_INTR_CATEGORY.
*/
#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128
/*!
* Categories of interrupts.
*
* Each of these categories get a separate range of interrupt subtrees (top
* level bits).
*/
typedef enum NV2080_INTR_CATEGORY {
NV2080_INTR_CATEGORY_DEFAULT = 0,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
NV2080_INTR_CATEGORY_RUNLIST = 3,
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
NV2080_INTR_CATEGORY_UVM_OWNED = 5,
NV2080_INTR_CATEGORY_UVM_SHARED = 6,
NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
} NV2080_INTR_CATEGORY;
#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX
typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
NvU8 subtreeStart;
NvU8 subtreeEnd;
} NV2080_INTR_CATEGORY_SUBTREE_MAP;
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
NvU16 engineIdx;
NvU32 pmcIntrMask;
@@ -1477,7 +1473,7 @@ typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
NvU32 tableLen;
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
NV_DECLARE_ALIGNED(NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT], 8);
} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
/* Index to retrieve the needed heap space for specific module */
@@ -3439,7 +3435,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK (0x20800a45) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x45" */
/*
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
@@ -5166,6 +5162,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NvU32 nvlinkRefClkSpeedKHz;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
@@ -5281,7 +5278,74 @@ typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 logBufferAddr, 8);
} NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO (0x20800a89U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO (0x20800a89U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE 5
/*
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_HFRP_INFO
*
* This command retrives HFRP info from physical RM
*
* [Out] hfrpPrivBase
* HFRP device PRIV base
* [Out] hfrpIntrCtrlReg
* HFRP intr control base
*
*/
#define NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS_MESSAGE_ID (0x7AU)
typedef struct NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS {
NvU32 hfrpPrivBase[NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE];
NvU32 hfrpIntrCtrlReg[NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE];
} NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_HFRP_INFO (0x20800a7aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS
*
* Send UMD API operations to CMC
*
* [in] opType
* UMD Task construct/destroy operation to perform on CMC
* [in] handle
* Handle of CmcUmdApi object for CMC to identify
* [in] ringBufferSize
* Size of ring buffer in bytes
* [in] ringBufferOffset
* Offset of ring buffer
* [in] userdPa
* PA of USERD memory
* [in] userdVa
* VA of USERD memory
* [in] instBlkAddr
* Address of instance block holding VASpace PDB info
* [in] instBlkAperture
* Aperture of instance block
* [out] workSubmitToken
* WorkSubmitToken generated by CMC for UMD_API object
*
*/
#define NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS_MESSAGE_ID (0x7CU)
typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS {
NvU32 opType;
NvU32 ringBufferSize;
NV_DECLARE_ALIGNED(NvU64 ringBufferOffset, 8);
NV_DECLARE_ALIGNED(NvU64 userdPa, 8);
NV_DECLARE_ALIGNED(NvU64 userdVa, 8);
NV_DECLARE_ALIGNED(NvU64 instBlkAddr, 8);
NvU8 instBlkAperture;
NvU8 userdAperture;
NvU32 workSubmitToken;
NvU32 cmcHandle;
} NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS;
#define NV2080_INTERNAL_CMC_UMD_API_TASK_CONSTRUCT 0x0U
#define NV2080_INTERNAL_CMC_UMD_API_TASK_DESTROY 0x1U
#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_UMD_API_OP (0x20800a7cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS_MESSAGE_ID" */
/*
@@ -5317,4 +5381,32 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARA
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL
*
* This command returns the throttle controls for all the GR engines.
*
*/
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL {
NvU32 smIssueThrottleCtrlListSize;
NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrlList[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE];
} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x04U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrl[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL (0x20800b05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x05U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS;
/* ctrl2080internal_h */

48
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -148,6 +148,9 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B (0x0000000B)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20C (0x0000000C)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
@@ -219,7 +222,7 @@ typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
* NVOS_STATUS_ERROR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU)
@@ -314,4 +317,45 @@ typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS {
NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX];
} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS;
/*!
* Categories of interrupts.
*
* Each of these categories get a separate range of interrupt subtrees (top
* level bits) corresponding to a set of interrupt leaves.
* Interrupt leaves may overlap between two or more categories.
* Interrupt leaves may or may not be contiguous.
*/
typedef enum NV2080_INTR_CATEGORY {
NV2080_INTR_CATEGORY_DEFAULT = 0,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
NV2080_INTR_CATEGORY_RUNLIST = 3,
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
NV2080_INTR_CATEGORY_UVM_OWNED = 5,
NV2080_INTR_CATEGORY_UVM_SHARED = 6,
NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
} NV2080_INTR_CATEGORY;
#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX
typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
// Maximum possible 64 subtrees, but 16 is enough for any existing silicon.
NV_DECLARE_ALIGNED(NvU64 subtreeMask, 8);
} NV2080_INTR_CATEGORY_SUBTREE_MAP;
/*
* NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP
*
* This command gets a mapping from every interrupt category -> subtrees used from
* Host RM.
*/
#define NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP (0x2080170f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS {
NV_DECLARE_ALIGNED(NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT], 8);
} NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS;
/* _ctrl2080mc_h_ */

293
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -31,6 +31,7 @@
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080nvlink_common.h"
#include "nvcfg_sdk.h"
/* NV20_SUBDEVICE_XX bus control commands and parameters */
@@ -73,8 +74,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
NvU32 discoveredLinkMask;
NvU32 enabledLinkMask;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NV_DECLARE_ALIGNED(NvU64 enabledLinks, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinks, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK enabledLinks, 8);
} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS;
/* extract cap bit setting from tbl */
@@ -427,9 +428,6 @@ typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = 1,
} NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT;
#define NV2080_CTRL_NVLINK_MAX_LINKS 32
#define NV2080_CTRL_NVLINK_MAX_ARR_SIZE 64
// NVLink REFCLK types
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U)
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U)
@@ -438,8 +436,10 @@ typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
NvU32 enabledLinkMask;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NvU32 enabledLinkMask; // (This field will be deprecated in the future, use enabledLinks)
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK enabledLinks, 8);
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NvBool bNvleModeEnabled; // whether Nvlink Encryption is enabled or not
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS;
@@ -448,6 +448,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
*
* enabledLinkMask
* This field specifies the mask of available links on this subdevice.
* bNvleModeEnabled
* This field indicates if Nvlink Encryption is enabled or not.
* linkInfo
* This structure stores the per-link status of different NVLink parameters. The link is identified using an index.
*
@@ -689,7 +691,10 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
/*
* NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS
*
* linkMask
* linkMask (This field will be deprecated in the future, please use links)
* Returns the mask of links enabled
*
* links
* Returns the mask of links enabled
*
* linkErrInfo
@@ -711,6 +716,7 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
NvU32 ioctrlMask;
NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS];
@@ -784,7 +790,10 @@ typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
* Mask of counter types to be queried
* One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros
*
* [in] linkMask
* [in] linkMask (This field will be deprecated in the future, please use links)
* Mask of links to be queried
*
* [in] links
* Mask of links to be queried
*
* [out] counters
@@ -802,7 +811,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
* [out] bRx1TlCounterOverflow
* This boolean is set to NV_TRUE if RX Counter 1 has rolled over.
*
* [out] value
* [out] value
* This array contains the error counts for each error type as requested from
* the counterMask. The array indexes correspond to the mask bits one-to-one.
*/
@@ -819,6 +828,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS {
NvU32 counterMask;
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS;
@@ -829,7 +839,11 @@ typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS {
* NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS
* This command clears/resets the counters for the specified types.
*
* [in] linkMask
* [in] linkMask (This field will be deprecated in the future, please use links)
* This parameter specifies for which links we want to clear the
* counters.
*
* [in] links
* This parameter specifies for which links we want to clear the
* counters.
*
@@ -849,6 +863,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS {
typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
NvU32 counterMask;
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS;
@@ -1006,7 +1021,10 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
* NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2
* This command gets the counts for different counter types.
*
* [in] linkMask
* [in] linkMask (This field will be deprecated in the future, please use links)
* Mask of links to be queried
*
* [in] links
* Mask of links to be queried
*
* [in] counterMask
@@ -1027,6 +1045,7 @@ typedef struct NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_ARR_SIZE][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8);
} NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS;
@@ -1036,7 +1055,11 @@ typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS {
* NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2
* This command clears/resets the counters for the specified types.
*
* [in] linkMask
* [in] linkMask (This field will be deprecated in the future, please use links)
* This parameter specifies for which links we want to clear the
* counters.
*
* [in] links
* This parameter specifies for which links we want to clear the
* counters.
*
@@ -1049,6 +1072,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS {
typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 (0x20803051U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID)" */
@@ -1058,8 +1082,12 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS {
* This command causes all the same actions to occur as if the related
* error were to occur, either fatal or recoverable.
*
* [in] linkMask size: 32 bits
* [in] linkMask (This field will be deprecated in the future, please use links)
* Controls which links to apply error injection to.
*
* [in] links
* Controls which links to apply error injection to.
*
* [in] bFatal
* This parameter specifies that the error should be fatal.
*
@@ -1070,6 +1098,7 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS {
typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NvBool bFatalError;
} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS;
@@ -1148,8 +1177,12 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG {
* This command causes all the same actions to occur as if the related
* error were to occur, either fatal or recoverable.
*
* [in] linkMask size: 64 bits
* [in] linkMask size: 64 bits (This field will be deprecated in the future, please use links)
* Mask of the links to be configured.
*
* [in] links
* Mask of the links to be configured.
*
* [in] errCfg
* This parameter specifies that the error configurations.
*/
@@ -1158,6 +1191,7 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG {
typedef struct NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS;
@@ -1199,8 +1233,12 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO {
* NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT
* This command get all the current nvlink error config
*
* [in] linkMask size: 64 bits
* [in] linkMask size: 64 bits (This field will be deprecated in the future, please use links)
* Mask of the links to be configured.
*
* [in] links
* Mask of the links to be configured.
*
* [in] errCfg
* This parameter specifies that the error configurations.
*/
@@ -1209,6 +1247,7 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO {
typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS;
@@ -1218,8 +1257,12 @@ typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
* NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES
* This command gets the number of successful error recoveries
*
* [in] linkMask size: 32 bits
* [in] linkMask size: 32 bits (This field will be deprecated in the future, please use links)
* This parameter controls which links to get recoveries for.
*
* [in] links
* This parameter controls which links to get recoveries for.
*
* [out] numRecoveries
* This parameter specifies the number of successful per link error recoveries
*/
@@ -1229,6 +1272,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS;
@@ -1640,9 +1684,14 @@ typedef struct NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS {
* This command sets the mask of links associated with the GPU
* to a target power state
*
* [in] linkMask
* [in] linkMask (This field will be deprecated in the future, please use links)
* Mask of links that will be put to desired power state
* Note: In Turing RM supports only tansitions into/out of L2
*
* [in] links
* Mask of links that will be put to desired power state
* Note: In Turing RM supports only tansitions into/out of L2
*
* [in] powerState
* Target power state to which the links will transition
* This can be any one of NV2080_CTRL_NVLINK_POWER_STATE_* states
@@ -1669,6 +1718,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS {
typedef struct NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NvU32 powerState;
} NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS;
@@ -1898,7 +1948,11 @@ typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR {
* Control to get the values of ECC ERRORS
*
* Parameters:
* linkMask [IN]
* linkMask [IN] (This field will be deprecated in the future, please use links)
* Links on which the ECC error data requested
* A valid link/port mask returned by the port masks returned by
* NVSWITCH_GET_INFO
* links [IN]
* Links on which the ECC error data requested
* A valid link/port mask returned by the port masks returned by
* NVSWITCH_GET_INFO
@@ -1911,6 +1965,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR {
typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS;
@@ -1939,7 +1994,9 @@ typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS {
* [in] counterMask
* Mask of counter types to be queried
* One of NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_* macros
* [in] linkMask
* [in] linkMask (This field will be deprecated in the future, please use links)
* Mask of links to be queried
* [in] links
* Mask of links to be queried
* [out] value
* Throughput counter value returned
@@ -1980,6 +2037,7 @@ typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES {
typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS {
NvU16 counterMask;
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS;
@@ -2105,7 +2163,9 @@ typedef struct NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO {
* NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS
*
*
* [In] linkMask
* [In] linkMask (This field will be deprecated in the future, please use links)
* Specifies for which links we want to read the counters
* [In] links
* Specifies for which links we want to read the counters
* [Out] refreshCountPass
* Count of number of times PHY refresh pass
@@ -2116,6 +2176,7 @@ typedef struct NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO {
typedef struct NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO refreshCount[NV2080_CTRL_NVLINK_MAX_LINK_COUNT];
} NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS;
@@ -2129,13 +2190,16 @@ typedef struct NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS {
* NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS
*
*
* [In] linkMask
* [In] linkMask (This field will be deprecated in the future, please use links)
* Specifies for which links we want to clear the counters
* [In] links
* Specifies for which links we want to clear the counters
*/
#define NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
} NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */
@@ -2164,27 +2228,50 @@ typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS {
*
* Syncs the different link masks and vbios defined values between CPU-RM and GSP-RM
*
* [in] discoveredLinks
* [in] discoveredLinks (This field will be deprecated in the future, please use discoveredLinkMask)
* Mask of links discovered from IOCTRLs
*
* [in] connectedLinksMask
* [in] discoveredLinkMask
* Mask of links discovered from IOCTRLs
*
* [in] connectedLinksMask (This field will be deprecated in the future, please use connectedLinks)
* Mask of links which are connected (remote present)
*
* [in] bridgeSensableLinks
* [in] connectedLinks
* Mask of links which are connected (remote present)
*
* [in] bridgeSensableLinks (This field will be deprecated in the future, please use bridgeSensableLinkMask)
* Mask of links whose remote endpoint presence can be sensed
*
* [in] bridgedLinks
* [in] bridgeSensableLinkMask
* Mask of links whose remote endpoint presence can be sensed
*
* [in] bridgedLinks (This field will be deprecated in the future, please use bridgedLinkMask)
* Mask of links which are connected (remote present)
* Same as connectedLinksMask, but also tracks the case where link
* is connected but marginal and could not initialize
*
* [out] initDisabledLinksMask
* [in] bridgedLinkMask
* Mask of links which are connected (remote present)
* Same as connectedLinks, but also tracks the case where link
* is connected but marginal and could not initialize
*
* [out] initDisabledLinksMask (This field will be deprecated in the future, please use initDisabledLinks)
* Mask of links for which initialization is disabled
*
* [out] vbiosDisabledLinkMask
* [out] initDisabledLinks
* Mask of links for which initialization is disabled
*
* [out] vbiosDisabledLinkMask (This field will be deprecated in the future, please use vbiosDisabledLinks)
* Mask of links disabled in the VBIOS
*
* [out] initializedLinks
* [out] vbiosDisabledLinks
* Mask of links disabled in the VBIOS
*
* [out] initializedLinks (This field will be deprecated in the future, please use initializedLinkMask)
* Mask of initialized links
*
* [out] initializedLinkMask
* Mask of initialized links
*
* [out] bEnableTrainingAtLoad
@@ -2198,12 +2285,19 @@ typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS {
typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinkMasks, 8);
NvU32 connectedLinksMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK connectedLinks, 8);
NV_DECLARE_ALIGNED(NvU64 bridgeSensableLinks, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK bridgeSensableLinkMasks, 8);
NvU32 bridgedLinks;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK bridgedLinkMasks, 8);
NvU32 initDisabledLinksMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initDisabledLinks, 8);
NV_DECLARE_ALIGNED(NvU64 vbiosDisabledLinkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK vbiosDisabledLinks, 8);
NvU32 initializedLinks;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initializedLinkMasks, 8);
NvBool bEnableTrainingAtLoad;
NvBool bEnableSafeModeAtLoad;
} NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS;
@@ -2224,7 +2318,10 @@ typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS {
*
* Process the init disabled NVLinks and filter those out
*
* [in/out] initDisabledLinksMask
* [in/out] initDisabledLinksMask (This field will be deprecated in the future, please use initDisabledLinks)
* Mask of links initdisabled on a given GPU
*
* [in/out] initDisabledLinks
* Mask of links initdisabled on a given GPU
*
* [in] bSkipHwNvlinkDisable
@@ -2235,6 +2332,7 @@ typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS {
typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS {
NvU32 initDisabledLinksMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initDisabledLinks, 8);
NvBool bSkipHwNvlinkDisable;
} NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS;
@@ -2543,18 +2641,7 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS {
} NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS;
/*!
*
* NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS
*
* Nvlink Fatal Error Recovery
* This command accepts no parameters.
*
*/
#define NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY (0x20803048U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x48" */
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC (0x20803053U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC (0x20803053U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID (0x53U)
@@ -3120,6 +3207,31 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS {
NvU8 split_num;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS;
/*
* NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
*
* This command returns platform-specific information related to the GPU's NVLink setup.
*
* ibGuid
* Infiniband GUID reported by platform (for Blackwell, ibGuid is 8 bytes so indices 8-15 are zero)
* rackGuid
* GUID of the rack containing this GPU (for Blackwell rackGuid is 13 bytes so indices 13-15 are zero)
* chassisPhysicalSlotNumber
* The slot number in the rack containing this GPU (includes switches)
* computeSlotIndex
* The index within the compute slots in the rack containing this GPU (does not include switches)
* nodeIndex
* Index of the node within the slot containing this GPU
* peerType
* Platform indicated NVLink-peer type (e.g. switch present or not)
* moduleId
* ID of this GPU within the node
* nvlinkSignalingProtocol
* signaling protocol (xdr/bidir)
* lanesPerLink
* lanes per link encoding (x1/x2)
*/
#define NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO (0x20803083U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID (0x83U)
@@ -3132,6 +3244,8 @@ typedef struct NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS {
NvU8 nodeIndex;
NvU8 peerType;
NvU8 moduleId;
NvU8 nvlinkSignalingProtocol;
NvU8 lanesPerLink;
} NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS;
/*
@@ -3146,15 +3260,15 @@ typedef struct NV2080_CTRL_NVLINK_UPHY_CLN_CMD {
NvU16 address;
} NV2080_CTRL_NVLINK_UPHY_CLN_CMD;
#define NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS 18U
/*
* NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN
*
*
* This command retrieves the land id cln select, lane id, and pll index.
*
* [in] linkMask
* [in] linkMask (This field will be deprecated in the future, please use links)
* Mask of links whose uphy should be read
* [in] links
* Mask of links whose uphy should be read
* [in] uphyCmd
* Array of input data (pll index and address) for each link,
@@ -3174,14 +3288,15 @@ typedef struct NV2080_CTRL_NVLINK_UPHY_CLN_CMD {
* NV_ERR_TIMEOUT
* If a timeout occurred waiting for minion response
*/
#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN (0x20803084U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN (0x20803084U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID (0x84U)
typedef struct NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_UPHY_CLN_CMD uphyCmd[NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS];
NvU32 data[NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS];
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_UPHY_CLN_CMD uphyCmd[NV2080_CTRL_NVLINK_MAX_LINKS];
NvU32 data[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS;
#define NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT 23U
@@ -3285,6 +3400,8 @@ typedef struct NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS {
*
* This command is used to inject NVL5 ERROR_INJECT_V2 commands
*
* [in] links
* link mask of which links to inject the error on
* [out]
* Error Types to be injected
*
@@ -3329,6 +3446,7 @@ typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY {
typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity;
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS;
@@ -3420,6 +3538,7 @@ typedef struct NV2080_CTRL_NVLINK_L1_FORCE_CONFIG {
typedef struct NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config;
} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS;
@@ -3429,6 +3548,7 @@ typedef struct NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS {
typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS {
NvU32 linkMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8);
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS;
@@ -3449,6 +3569,75 @@ typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS {
NvBool bEncryptEnSet;
} NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS;
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCSR_DATA_SIZE (0x10U)
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCSR (0x20803090U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCSR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCSR_PARAMS_MESSAGE_ID (0x90U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MCSR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU32 base_address;
NvU16 num_addresses;
NvU32 data[NV2080_CTRL_NVLINK_PRM_ACCESS_MCSR_DATA_SIZE];
} NV2080_CTRL_NVLINK_PRM_ACCESS_MCSR_PARAMS;
/*
* NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO
*
* This command is used to get the firmware version info
*
* [out] firmwareVersion
* Array of firmware versions specifying their ucode type, and major/minor/subminor version
* [out] chipTypeArch
* Chip type arch
* [out] numValidEntries
* Number of valid entries in firmwareVersion array
*/
#define NV2080_CTRL_NVLINK_FIRMWARE_VERSION_LENGTH (0x10U)
#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_MSE (0x01U)
#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR (0x02U)
#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_UPHY (0x03U)
#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_CLN (0x04U)
#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_DLN (0x05U)
typedef struct NV2080_CTRL_NVLINK_SEMANTIC_VERSION {
NvU8 ucodeType;
NvU32 major;
NvU32 minor;
NvU32 subMinor;
} NV2080_CTRL_NVLINK_SEMANTIC_VERSION;
#define NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO (0x20803091U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS_MESSAGE_ID (0x91U)
typedef struct NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS {
NV2080_CTRL_NVLINK_SEMANTIC_VERSION firmwareVersion[NV2080_CTRL_NVLINK_FIRMWARE_VERSION_LENGTH];
NvU8 chipTypeArch;
NvU32 numValidEntries;
} NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_SET_NVLE_ENABLED_STATE
*
* This command is used to set the NVLE enablement status in GSP-RM
*
* [Out] bIsNvleEnabled
* Boolean to determine if Nvlink Encryption is enabled or not
*/
#define NV2080_CTRL_CMD_NVLINK_SET_NVLE_ENABLED_STATE (0x20803092U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS_MESSAGE_ID (0x92U)
typedef struct NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS {
NvBool bIsNvleEnabled;
} NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTASV2 (0x20803093U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS_MESSAGE_ID (0x93U)
@@ -3490,17 +3679,17 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS {
NvU16 peq_interval_period;
} NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS (0x20803090U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS (0x20803095U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID (0x90U)
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID (0x95U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS {
NV2080_CTRL_NVLINK_PRM_DATA prm;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRM (0x20803091U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRM (0x20803096U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID (0x91U)
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS_MESSAGE_ID (0x96U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS {
NvBool bWrite;

31
src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h → src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink_common.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,29 +23,20 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc06f.finn
// Source file: ctrl/ctrl2080/ctrl2080nvlink_common.finn
//
#define NV2080_CTRL_NVLINK_MAX_LINKS 64
#define NV2080_CTRL_NVLINK_MAX_ARR_SIZE 64
#define NV2080_CTRL_NVLINK_MAX_MASK_SIZE (0x1) /* finn: Evaluated from "((NV2080_CTRL_NVLINK_MAX_LINKS + 63) / 64)" */
/* PASCAL_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
/* PASCAL_CHANNEL_GPFIFO_B command categories (6bits) */
#define NVC06F_CTRL_RESERVED (0x00)
/*
* NVC06F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NVC06F_CTRL_CMD_NULL (0xc06f0000) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
typedef struct NV2080_CTRL_NVLINK_LINK_MASK {
NvU8 lenMasks;
NV_DECLARE_ALIGNED(NvU64 masks[NV2080_CTRL_NVLINK_MAX_MASK_SIZE], 8);
} NV2080_CTRL_NVLINK_LINK_MASK;

30
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -890,6 +890,34 @@ typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS {
NvU32 currPstate;
} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE
*
* Fetch the busyness of the specified clock domain in percentage
* for Tegra chips.
*
* clkDomain
* Clock domain identifier for Tegra platforms.
*
* clkPercentBusy
* Busyness of the specified clock domain in percentage
* unit ranging from 0 to 100.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE (0x20802069) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */
typedef NvU32 NV2080_CTRL_CLK_DOMAIN_TEGRA;
#define NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x69U)
typedef struct NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS {
NV2080_CTRL_CLK_DOMAIN_TEGRA clkDomain;
NvU32 clkPercentBusy;
} NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS;
/* _ctrl2080perf_h_ */

20
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -212,6 +212,7 @@ typedef struct NV2080_HOST_VGPU_DEVICE {
NvU32 gfid;
NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8);
NvU32 vgpuDeviceInstanceId;
NvU32 accountingPid;
NV_DECLARE_ALIGNED(NvU64 fbUsed, 8);
NvU32 encoderCapacity;
NvU32 eccState;
@@ -499,4 +500,23 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE
*
* This command is used to share the Power State from KMD side to GSP-RM.
*
* state
* This parameter contains Power State Information.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE (0x20804010) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS {
NvU32 state;
} NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */

30
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -454,6 +454,9 @@ typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS {
*
* address
* The physical DRAM address to be targeted by the write kill
*
* bProdInjection
* Whether the write kill is set through the production injection flow or not
*/
#define NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL (0x208f0511) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID" */
@@ -461,6 +464,7 @@ typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS {
typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS {
NvBool setWriteKill;
NvBool bProdInjection;
NV_DECLARE_ALIGNED(NvU64 address, 8);
} NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS;
@@ -698,30 +702,30 @@ typedef struct NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS {
} NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS;
/*
* NV208F_CTRL_CMD_FB_CONVERT_CHANNEL
* NV208F_CTRL_CMD_FB_CONVERT_SUBLOCATION
*
* This API converts either a channel from physical to logical or vice-versa
* This API converts either the given sublocation from physical to logical or vice-versa
*
* conversionType:
* See NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE
* See NV208F_CTRL_FB_SUBLOCATION_CONVERSION_TYPE
* fbpa:
* The physical fbpa the channel resides
* The physical fbpa the sublocation resides
* input:
* Input channel
* Input sublocation
* output:
* Output channel
* Output sublocation
*/
#define NV208F_CTRL_CMD_FB_CONVERT_CHANNEL (0x208f0519) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_CMD_FB_CONVERT_SUBLOCATION (0x208f0519) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS_MESSAGE_ID (0x19U)
#define NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS {
typedef struct NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS {
NvU32 conversionType;
NvU32 fbpa;
NvU32 input;
NvU32 output;
} NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS;
} NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS;
#define NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE_LOGICAL_TO_PHYSICAL (0x00000000U)
#define NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE_PHYSICAL_TO_LOGICAL (0x00000001U)
#define NV208F_CTRL_FB_SUBLOCATION_CONVERSION_TYPE_LOGICAL_TO_PHYSICAL (0x00000000U)
#define NV208F_CTRL_FB_SUBLOCATION_CONVERSION_TYPE_PHYSICAL_TO_LOGICAL (0x00000001U)
/* _ctrl208ffb_h_ */

6
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -41,7 +41,7 @@
* Parameters:
*
* location
* Only used for HSHUBMMU.
* Only used for HSHUBMMU for pre-Blackwell.
*
* sublocation
* Only used for HSHUBMMU.
@@ -68,7 +68,6 @@ typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS {
NvU32 sublocation;
NvU8 unit;
NvU8 errorType;
NvU8 instance;
} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS;
@@ -146,4 +145,5 @@ typedef struct NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS {
NvU32 numHubmmus;
} NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS;
// extension NV_VERIF_FEATURES
/* _ctrl208fmmu_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h
View File

@@ -644,8 +644,6 @@ typedef struct NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS {
NvBool bUseCachedPerfState;
} NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS;
/*
* NV5070_CTRL_CMD_GET_CHANNEL_INFO
*

82
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h
View File

@@ -256,88 +256,6 @@ typedef struct NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS {
NvU32 swapLockoutStart;
} NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS;
/*
* NV5070_CTRL_CMD_SET_VIDEO_STATUS
*
* This command is used to set the current video playback status for use
* by the Display Power Saving (nvDPS) feature. The playback status is
* used to maximize power savings by altering the DFP refresh rate used for
* video playback.
*
* displayId
* This parameter specifies the ID of the video playback display.
* Only one display may be indicated in this parameter.
* clientId
* This parameter specifies the opaque client ID associated with
* the video playback application.
* mode
* This parameter specifies the video playback mode. Valid values
* for this parameter include:
* NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN
* This value indicates that there is either no video playback or
* that video playback is windowed.
* NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEN
* This value indicates that video playback is fullscreen.
* NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D
* This value indicates that there is a D3D app started.
* frameRate
* The parameter indicates the current video playback frame rate.
* The value is a 32 bit unsigned fixed point number, 24 bit unsigned
* integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in
* number of frames per second.
* A value of 0 indicates that video playback is stopped or not playing.
* frameRateAlarmUpperLimit
* The parameter indicates the upper limit which will can be tolerated in
* notifying frame rate change. If the frame rate changed but is still
* below the limit. The newer frame rate doesn't have to be set till it's
* over the limit.
* The value is a 32 bit unsigned fixed point number, 24 bit unsigned
* integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in
* number of frames per second.
* A value of 0 indicates no tolerance of frame rate notifying. Instant
* frame rate has to be set when it has changed.
* frameRateAlarmLowerLimit
* The parameter indicates the lower limit which will can be tolerated in
* notifying frame rate change. If the frame rate changed but is still
* above the limit. The newer frame rate doesn't have to be set till it's
* below the limit.
* The value is a 32 bit unsigned fixed point number, 24 bit unsigned
* integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in
* number of frames per second.
* A value of 0 indicates no tolerance of frame rate notifying. Instant
* frame rate has to be set when it has changed.
*
* The frameRateAlarm limit values can be used by the video client to
* indicate the the range in which frame rate changes do not require
* notification (i.e. frame rates outside these limits will result in
* notification).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV5070_CTRL_CMD_SET_VIDEO_STATUS (0x50700209) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 displayId;
NvU32 clientId;
NvU32 mode;
NvU32 frameRate;
NvU32 frameRateAlarmUpperLimit;
NvU32 frameRateAlarmLowerLimit;
} NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS;
/* valid mode flags */
#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN (0x00000000)
#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEEN (0x00000001)
#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D (0x00000002)
/*
* NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS
*

26
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -43,11 +43,12 @@
#define NVA081_CTRL_VGPU_CONFIG (0x01)
#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00
#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x64
#define NVA081_MAX_VGPU_PER_PGPU 32
#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x80
#define NVA081_MAX_VGPU_PER_PGPU 48
#define NVA081_MAX_VGPU_PER_PGPU_NON_MIG 32
#define NVA081_MAX_VGPU_PER_GI 12
#define NVA081_VM_UUID_SIZE 16
#define NVA081_VGPU_STRING_BUFFER_SIZE 32
#define NVA081_VGPU_STRING_BUFFER_SIZE 64
#define NVA081_VGPU_SIGNATURE_SIZE 128
#define NVA081_VM_NAME_SIZE 128
#define NVA081_PCI_CONFIG_SPACE_SIZE 0x100
@@ -263,6 +264,7 @@ typedef struct NVA081_HOST_VGPU_DEVICE {
NvBool bDriverLoaded;
NvU32 swizzId;
NvU32 placementId;
NvU32 accountingPid;
} NVA081_HOST_VGPU_DEVICE;
/* ECC state values */
@@ -1056,4 +1058,20 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS {
NvU32 vgpuInstanceIds[NVA081_MAX_VGPU_PER_GI];
} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK
*
* This Command Clears the Assigned SwizzId Mask during vGPU destroy
*
* swizzId [IN]
* This parameter specifies the SwizzId of vGPU device
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK (0xa0810125) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS_MESSAGE_ID (0x25U)
typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS {
NvU32 swizzId;
} NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS;
/* _ctrlA081vgpuconfig_h_ */

10
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h
View File

@@ -187,6 +187,8 @@ typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS {
#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */
#define NVC370_CTRL_CMD_CHANNEL_CANCEL_FLIP (0xc3700105) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS_MESSAGE_ID" */
#define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE
#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW
#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM
@@ -220,6 +222,14 @@ typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_SET_ACCL_PARAMS;
typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS;
#define NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS {
NVC370_CTRL_CMD_BASE_PARAMS base;
NvU32 channelClass;
NvU32 channelInstance;
} NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS;
/*
* NVC370_CTRL_CMD_GET_CHANNEL_INFO
*

2
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370or.h
View File

@@ -41,7 +41,7 @@
// NVC370_CTRL_CMD_SET_SOR_FLUSH_MODE
//
// This command is used enable/disable flush mode on all the heads attached to the SOR
// Applies to NV Display 5.0+ (GB20X+ and T264+)
// [in] subDeviceInstance
// This parameter specifies the subdevice instance within the
// NV04_DISPLAY_COMMON parent device to which the operation should be

58
src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h
View File

@@ -1,58 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc86f.finn
//
#include "nvcfg_sdk.h"
/* HOPPER_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVC86F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC36F, NVC86F_CTRL_##cat, idx)
/* HOPPER_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC86F_CTRL_RESERVED (0x00)
#define NVC86F_CTRL_GPFIFO (0x01)
/*
* NVC86F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned is: NV_OK
*/
#define NVC86F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)

58
src/common/sdk/nvidia/inc/ctrl/ctrlc96f.h
View File

@@ -1,58 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc96f.finn
//
#include "nvcfg_sdk.h"
/* BLACKWELL_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVC96F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC36F, NVC96F_CTRL_##cat, idx)
/* BLACKWELL_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC96F_CTRL_RESERVED (0x00)
#define NVC96F_CTRL_GPFIFO (0x01)
/*
* NVC96F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned is: NV_OK
*/
#define NVC96F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)

15
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -608,10 +608,6 @@ typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS;
typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED;
#define FINN_GK110_SUBDEVICE_FB_FB_INTERFACE_ID (0xa0e101U)
typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB;
#define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED;
#define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED;
#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U)
typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED;
#define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U)
@@ -637,8 +633,6 @@ typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED;
#define FINN_MAXWELL_SEC2_SEC2_INTERFACE_ID (0xb6b901U)
typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2;
#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U)
typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U)
typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED;
#define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U)
@@ -688,8 +682,6 @@ typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS;
typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED;
#define FINN_GV100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc3e101U)
typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB;
#define FINN_TURING_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc46f00U)
typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U)
typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U)
@@ -706,13 +698,6 @@ typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION;
typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED;
#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID (0xc76301U)
typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER;
#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U)
typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc96f00U)
typedef FINN_RM_API FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_BLACKWELL_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xca6f00U)
typedef FINN_RM_API FINN_BLACKWELL_CHANNEL_GPFIFO_B_RESERVED;
#define FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID (0xcb3300U)
typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED;
#define FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID (0xcb3301U)

18
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2024, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2025, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -134,7 +134,6 @@
#define ROBUST_CHANNEL_OFA1_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (141)
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define ROBUST_CHANNEL_NVENC3_ERROR (142)
#define GPU_INIT_ERROR (143)
#define NVLINK_SAW_ERROR (144)
@@ -151,12 +150,22 @@
#define NVLINK_SW_DEFINED_ERROR (155)
#define RESOURCE_RETIREMENT_EVENT (156)
#define RESOURCE_RETIREMENT_FAILURE (157)
#define GPU_FATAL_TIMEOUT (158)
#define ROBUST_CHANNEL_CHI_NON_DATA_ERROR (159)
#define CHANNEL_RETIREMENT_EVENT (160)
#define CHANNEL_RETIREMENT_FAILURE (161)
#define ROBUST_CHANNEL_LAST_ERROR (161)
#define ISINK_REENGAGED (162)
#define ISINK_DISENGAGED (163)
#define ISINK_LOW_LIFETIME (164)
#define ISINK_ZERO_LIFETIME (165)
#define NVLINK_SECURE_INTERRUPT_ERROR (166)
#define PCIE_FATAL_TIMEOUT (167)
#define REDUCED_GPU_MEMORY_CAPACITY (168)
#define SEC2_HALT_ERROR (169)
#define ROBUST_CHANNEL_UNUSED_ERROR_170 (170)
#define UNCORRECTABLE_DRAM_ERROR (171)
#define UNCORRECTABLE_SRAM_ERROR (172)
#define ROBUST_CHANNEL_LAST_ERROR (172)
// Indexed CE reference
#define ROBUST_CHANNEL_CE_ERROR(x) \
@@ -223,7 +232,6 @@
(x - ROBUST_CHANNEL_NVDEC5_ERROR + 5))))
// Indexed NVENC reference
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define ROBUST_CHANNEL_NVENC_ERROR(x) \
((x == 0) ? (ROBUST_CHANNEL_NVENC0_ERROR) : \
((x == 1) ? (ROBUST_CHANNEL_NVENC1_ERROR) : \

12
src/common/sdk/nvidia/inc/nvmisc.h
View File

@@ -580,7 +580,6 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
n64 = BIT_IDX_64(LOWESTBIT(n64));\
}
// Destructive operation on n32
#define HIGHESTBITIDX_32(n32) \
{ \
@@ -592,6 +591,17 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
n32 = count; \
}
// Destructive operation on n64
#define HIGHESTBITIDX_64(n64) \
{ \
NvU64 count = 0; \
while (n64 >>= 1) \
{ \
count++; \
} \
n64 = count; \
}
// Destructive operation on n32
#define ROUNDUP_POW2(n32) \
{ \

435
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -898,7 +898,8 @@ typedef struct
#define NVOS32_TYPE_RESERVED 14
#define NVOS32_TYPE_PMA 15
#define NVOS32_TYPE_STENCIL 16
#define NVOS32_NUM_MEM_TYPES 17
#define NVOS32_TYPE_SYNCPOINT 17
#define NVOS32_NUM_MEM_TYPES 18
// Surface attribute field - bitmask of requested attributes the surface
// should have.
@@ -950,6 +951,22 @@ typedef struct
#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009
#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A
//
//
// GPU_CACHE_SNOOPABLE_ON signals to RM that CPU (or other IO device)
// accesses to this surface will snoop the GPU cache.
// _OFF indicates no GPU cache snooping will take place.
// _MAPPING defers the decision to mapping time.
//
// Only applies to fully coherent platforms.
//
//
#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE 9:8
#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_MAPPING 0x00000000
#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_OFF 0x00000001
#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_ON 0x00000002
#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_INVALID 0x00000003
// Zcull region (NV40 and up)
// If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the
// allocation will fail.
@@ -2093,6 +2110,10 @@ typedef struct
#define NVOS46_FLAGS_GPU_CACHEABLE_NO (0x00000002)
#define NVOS46_FLAGS_GPU_CACHEABLE_INVALID (0x00000003)
#define NVOS46_FLAGS_PAGE_KIND_OVERRIDE 19:19
#define NVOS46_FLAGS_PAGE_KIND_OVERRIDE_NO (0x00000000)
#define NVOS46_FLAGS_PAGE_KIND_OVERRIDE_YES (0x00000001)
#define NVOS46_FLAGS_P2P 27:20
#define NVOS46_FLAGS_P2P_ENABLE 21:20
@@ -2129,6 +2150,19 @@ typedef struct
#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000)
#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001)
//
// This flag is used on fully coherent platforms to specify whether the GPU cache
// should be snooped by the CPU or other IO devices for this mapping.
//
// Only takes effect if the physical memory is allocated with
// _ATTR_GPU_CACHE_SNOOPABLE_MAPPING indicating the decision
// should be deferred to map time.
//
#define NVOS46_FLAGS2_GPU_CACHE_SNOOP 1:0
#define NVOS46_FLAGS2_GPU_CACHE_SNOOP_DEFAULT (0x00000000)
#define NVOS46_FLAGS2_GPU_CACHE_SNOOP_ENABLE (0x00000001)
#define NVOS46_FLAGS2_GPU_CACHE_SNOOP_DISABLE (0x00000002)
/* parameters */
typedef struct
{
@@ -2139,6 +2173,8 @@ typedef struct
NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region
NvU64 length NV_ALIGN_BYTES(8); // [IN] limit of region
NvV32 flags; // [IN] flags
NvV32 flags2; // [IN] flags2
NvV32 kindOverride; // [IN] page kind - applied if NVOS46_FLAGS_PAGE_KIND_OVERRIDE is YES
NvU64 dmaOffset NV_ALIGN_BYTES(8); // [OUT] offset of mapping
// [IN] if FLAGS_DMA_OFFSET_FIXED_TRUE
// *OR* hDma is NOT a CTXDMA handle
@@ -2146,6 +2182,7 @@ typedef struct
NvV32 status; // [OUT] status
} NVOS46_PARAMETERS;
typedef NVOS46_PARAMETERS NV_MAP_MEMORY_DMA_PARAMETERS;
/* function OS47 */
#define NV04_UNMAP_MEMORY_DMA (0x0000002F)
@@ -2167,6 +2204,7 @@ typedef struct
NvV32 status; // [OUT] status
} NVOS47_PARAMETERS;
typedef NVOS47_PARAMETERS NV_UNMAP_MEMORY_DMA_PARAMETERS;
#define NV04_BIND_CONTEXT_DMA (0x00000031)
/* parameters */
@@ -2267,6 +2305,392 @@ typedef struct
NvU32 status; // [OUT] status
} NVOS57_PARAMETERS;
/*!
* @defgroup NVPOWERSTATE_STAGE
*
* An enumeration of various "stages" during @ref NVPOWERSTATE_PARAMETERS
* processing, particularly for tracking failures during a given stage.
*
* @{
*/
typedef NvU32 NVPOWERSTATE_STAGE;
#define NVPOWERSTATE_STAGE_NONE 0U
#define NVPOWERSTATE_STAGE_WAIT_FOR_GFW_BOOT_OK 1U
#define NVPOWERSTATE_STAGE_INIT_LIBOS_LOGGING_STRUCTURES 2U
#define NVPOWERSTATE_STAGE_GSP_PREPARE_FOR_BOOTSTRAP 3U
#define NVPOWERSTATE_STAGE_GSP_BOOTSTRAP 4U
#define NVPOWERSTATE_STAGE_BOOT_GSP_RM_PROXY 5U
#define NVPOWERSTATE_STAGE_VBIOS_HANDLE_SECURE_BOOT 6U
#define NVPOWERSTATE_STAGE_RESTORE_PCIE_CONFIG_REGISTERS 7U
#define NVPOWERSTATE_STAGE_GCX_BOOT_TIMER_CB_SCHEDULE 8U
#define NVPOWERSTATE_STAGE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED 9U
#define NVPOWERSTATE_STAGE_PMS_EXPECTED_CHECKPOINT_DONE 10U
#define NVPOWERSTATE_STAGE_POLL_FOR_NVLINK_READY 11U
#define NVPOWERSTATE_STAGE_CE_STATE_PRE_LOAD 12U
#define NVPOWERSTATE_STAGE_LOAD_PROXY_UCODE_EARLY_INIT 13U
#define NVPOWERSTATE_STAGE_RESTORE_NON_WPR_REGION 14U
#define NVPOWERSTATE_STAGE_PMU_20_OS_BOOTSTRAP 15U
#define NVPOWERSTATE_STAGE_STATE_PRE_LOAD_ENGINE 16U
#define NVPOWERSTATE_STAGE_STATE_PRE_LOAD_UNKNOWN 17U
#define NVPOWERSTATE_STAGE_STATE_LOAD_ENGINE 18U
#define NVPOWERSTATE_STAGE_STATE_LOAD_UNKNOWN 19U
#define NVPOWERSTATE_STAGE_STATE_LOAD_PHYSICAL 20U
#define NVPOWERSTATE_STAGE_STATE_POST_LOAD_ENGINE 21U
#define NVPOWERSTATE_STAGE_STATE_POST_LOAD_UNKNOWN 22U
#define NVPOWERSTATE_STAGE_GSP_PREPARE_SUSPEND_RESUME_DATA 23U
#define NVPOWERSTATE_STAGE_MC_POINTER_NULL 24U
#define NVPOWERSTATE_STAGE_SAVE_PCIE_CONFIG_REGISTERS 25U
#define NVPOWERSTATE_STAGE_STATE_PRE_UNLOAD_ENGINE 26U
#define NVPOWERSTATE_STAGE_STATE_PRE_UNLOAD_UNKNOWN 27U
#define NVPOWERSTATE_STAGE_STATE_UNLOAD_ENGINE 28U
#define NVPOWERSTATE_STAGE_STATE_UNLOAD_UNKNOWN 29U
#define NVPOWERSTATE_STAGE_STATE_POST_UNLOAD_ENGINE 30U
#define NVPOWERSTATE_STAGE_STATE_POST_UNLOAD_UNKNOWN 31U
#define NVPOWERSTATE_STAGE_GSP_UNLOAD_RM 32U
#define NVPOWERSTATE_STAGE_MONITOR_STATE_0 33U
#define NVPOWERSTATE_STAGE_MONITOR_STATE_1 34U
#define NVPOWERSTATE_STAGE_MONITOR_STATE_HIBERNATE 35U
#define NVPOWERSTATE_STAGE_SET_POWER_STATE_UNKNOWN 36U
#define NVPOWERSTATE_STAGE__COUNT 37U
/*!@}*/
/*!
* Common structure for any failure within a given GPU engine in a top-level GPU
* state transition
*/
typedef struct
{
/*!
* NVOC class ID of the failing engine
*/
NvU32 classId;
/*!
* Time from beginning of the state transition to this engine's failure
*/
NvU64 cumulativeTimeus;
/*!
* Maximum time any of the engines took to transition
*/
NvU32 engineMaxTimeus;
/*!
* NVOC class ID of the engine that took the longest time to transition
*/
NvU32 engineMaxTimeClassId;
} NVPOWERSTATE_FAILURE_ENGINE_TRANSITION;
/*!
* @defgroup NVPOWERSTATE_FAILURE_STRUCTURE
*
* A set of structures for capturing additional, failure-specific data in a
* @ref NVPOWERSTATE_PARAMETERS processing failure.
*
* @note These structures should correspond 1:1 with the list of
* @ref NVPOWERSTATE_STAGE values
*
* @{
*/
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP;
typedef struct
{
NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition;
} NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN;
typedef struct
{
NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition;
} NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN;
typedef struct
{
NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition;
} NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_MC_POINTER_NULL;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS;
typedef struct
{
NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition;
} NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN;
typedef struct
{
NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition;
} NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN;
typedef struct
{
NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition;
} NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_MONITOR_STATE_0;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_MONITOR_STATE_1;
typedef struct
{
NvU8 rsvd;
} NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE;
typedef struct
{
/*!
* NV_POWER_ADAPTER_STATE_* value
*/
NvU32 state;
} NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN;
/*!@}*/
/*!
* A union to hold failure-specific data for any failure that might happen while
* doing @ref NVPOWERSTATE_PARAMETERS processing
*
* @note Entries in the union should correspond 1:1 with
* @ref NVPOWERSTATE_STAGE values
*/
typedef union
{
NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK waitForGfwBootOk;
NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES initLibosLoggingStructures;
NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP gspPrepareForBootstrap;
NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP gspBootstrap;
NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY bootGspRmProxy;
NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT vbiosHandleSecureBoot;
NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS restorePcieConfigRegisters;
NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE gcxBootTimerCbSchedule;
NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED powerManagementResumePreLoadPhysicalUnattached;
NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE pmsExpectedCheckpointDone;
NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY pollForNvlinkReady;
NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD ceStatePreLoad;
NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT loadProxyUcodeEarlyInit;
NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION restoreNonWprRegion;
NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP pmu20OsBootstrap;
NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE statePreLoadEngine;
NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN statePreLoadUnknown;
NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE stateLoadEngine;
NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN stateLoadUnknown;
NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE statePostLoadEngine;
NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN statePostLoadUnknown;
NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL stateLoadPhysical;
NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA gspPrepareSuspendResumeData;
NVPOWERSTATE_FAILURE_MC_POINTER_NULL mcPointerNull;
NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS savePcieConfigRegisters;
NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE statePreUnloadEngine;
NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN statePreUnloadUnknown;
NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE stateUnloadEngine;
NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN stateUnloadUnknown;
NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE statePostUnloadEngine;
NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN statePostUnloadUnknown;
NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM gspUnloadRm;
NVPOWERSTATE_FAILURE_MONITOR_STATE_0 monitorState0;
NVPOWERSTATE_FAILURE_MONITOR_STATE_1 monitorState1;
NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE monitorStateHibernate;
NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN setPowerStateUnknown;
} NVPOWERSTATE_FAILURE_DATA;
/*!
* Contains failure data for a failure that occurred during
* @ref NVPOWERSTATE_PARAMETERS processing
*/
typedef struct
{
/*!
* The @ref NVPOWERSTATE_STAGE in which the failure occurred, or @ref
* @ref NVPOWERSTATE_STAGE_NONE if no failure occurred.
*
* @note This field is the discriminant for
* @ref NVPOWERSTATE_FAILURE::data
*/
NVPOWERSTATE_STAGE stage;
/*!
* The @ref NV_STATUS value from the failure
*/
NV_STATUS status;
/*!
* Failure-specific data
*
* @note Valid entry is determined by @ref NVPOWERSTATE_FAILURE::stage
*/
NVPOWERSTATE_FAILURE_DATA data;
} NVPOWERSTATE_FAILURE;
/*!
* @brief Initializes a @ref NVPOWERSTATE_FAILURE for tracking
* during a transition
*
* @param[out] pFailure
* Pointer to @ref NVPOWERSTATE_FAILURE to initialize
*/
static NV_FORCEINLINE void
nvPowerStateFailureInit
(
NVPOWERSTATE_FAILURE *pFailure
)
{
(void)NVMISC_MEMSET(
pFailure,
0x0,
sizeof(*pFailure));
}
/*!
* @brief Returns whether the given @ref NVPOWERSTATE_FAILURE is already
* populated with error data
*
* @param[in] pFailure
* @ref NVPOWERSTATE_FAILURE to check
*
* @return @ref NV_TRUE
* Structure is already populated with failure data
* @return @ref NV_FALSE
* Otherwise
*/
static NV_FORCEINLINE NvBool
nvPowerStateFailureIsPopulated
(
const NVPOWERSTATE_FAILURE *pFailure
)
{
return pFailure->stage != NVPOWERSTATE_STAGE_NONE;
}
/* parameters */
typedef struct
{
@@ -2281,6 +2705,7 @@ typedef struct
NvU32 fastBootPowerState;
NvU8 bGC8Transition;
NvU8 bGC8InputRailCutOff; // [OUT] To tell client if input rail was cut off in GC8
NVPOWERSTATE_FAILURE failure;
} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS;
/***************************************************************************\
@@ -2722,6 +3147,9 @@ typedef struct
* will override to the default big page size that is supported by the system.
* If the big page size value is set to ZERO then we will pick the default page size
* of the system.
* pasid
* Process Address Space Identifier. Used by RM internally when
* NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS_TEST is set
**/
typedef struct
{
@@ -2732,6 +3160,7 @@ typedef struct
NvU64 vaLimitInternal NV_ALIGN_BYTES(8);
NvU32 bigPageSize;
NvU64 vaBase NV_ALIGN_BYTES(8);
NvU32 pasid;
} NV_VASPACE_ALLOCATION_PARAMETERS;
#define NV_VASPACE_ALLOCATION_FLAGS_NONE (0x00000000)
@@ -2749,6 +3178,8 @@ typedef struct
#define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11)
#define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12)
#define NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED BIT(13)
// To be used only by SRT for testing ATS within RM
#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS_TEST BIT(14)
#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default
#define NV_VASPACE_ALLOCATION_INDEX_GPU_HOST 0x01 //<! Acquire reference to BAR1 VAS.

1
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -164,6 +164,7 @@ NV_STATUS_CODE(NV_ERR_RESOURCE_RETIREMENT_ERROR, 0x00000086, "An error occ
NV_STATUS_CODE(NV_ERR_FABRIC_STATE_OUT_OF_SYNC, 0x00000087, "NVLink fabric state cached by the driver is out of sync")
NV_STATUS_CODE(NV_ERR_BUFFER_FULL, 0x00000088, "Buffer is full")
NV_STATUS_CODE(NV_ERR_BUFFER_EMPTY, 0x00000089, "Buffer is empty")
NV_STATUS_CODE(NV_ERR_MC_FLA_OFFSET_TABLE_FULL, 0x0000008A, "Multicast FLA offset table has no available slots")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

10
src/common/sdk/nvidia/inc/nvtypes.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,10 +24,6 @@
#ifndef NVTYPES_INCLUDED
#define NVTYPES_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "cpuopsys.h"
#ifndef NVTYPES_USE_STDINT
@@ -51,6 +47,10 @@ extern "C" {
// currently set to msvc100 but do not properly set the include paths
#endif // __cplusplus
#ifdef __cplusplus
extern "C" {
#endif
#if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__)
// ensure or force 8-bytes alignment of NV 64-bit types
#define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8)))