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This commit is contained in:
Andy Ritger
2023-02-28 11:12:44 -08:00
parent e598191e8e
commit 4397463e73
928 changed files with 124728 additions and 88525 deletions
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4
src/common/sdk/nvidia/inc/class/cl00c2.h
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@@ -34,8 +34,8 @@
#define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U)
typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS {
NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT]
NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT]
NvU32 format; // [IN] - PTE format to use
NvU32 pageSize; // [IN] - Page size to use
NV_DECLARE_ALIGNED(NvU64 pageSize, 8); // [IN] - Page size to use
} NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS;

2
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -35,6 +35,8 @@ typedef struct NV00DE_SHARED_DATA {
NvU32 bar1Size;
NvU32 bar1AvailSize;
NvU32 gspAssertCount;
// New data members always add to bottom
} NV00DE_SHARED_DATA;

5
src/common/sdk/nvidia/inc/class/cl2080_notification.h
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@@ -200,8 +200,9 @@ extern "C" {
#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (177)
#define NV2080_NOTIFIERS_MAXCOUNT (178)
#define NV2080_NOTIFIERS_NVPCF_EVENTS (177)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178)
#define NV2080_NOTIFIERS_MAXCOUNT (179)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))

29
src/common/sdk/nvidia/inc/class/clc763.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc763_h_
#define _clc763_h_
#define MMU_VIDMEM_ACCESS_BIT_BUFFER (0xc763)
#endif /* _clc763_h_ */

113
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -90,6 +90,11 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
NvS32 numaId;
} NV0000_CTRL_GPU_GET_ID_INFO_PARAMS;
#define NV0000_CTRL_SLI_STATUS_OK (0x00000000U)
#define NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED (0x00000002U)
#define NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED (0x00000040U)
#define NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT (0x00000001U)
/*
* NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2
* This command returns GPU instance information for the specified GPU.
@@ -149,7 +154,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U)
@@ -436,6 +441,55 @@ typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS {
/*
* NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS
*
* This command returns information about video bridge connections
* detected between GPUs in the system, organized as a table
* with one row per attached GPU and none, one or more peer GPUs
* listed in the columns of each row, if connected to the row head
* GPU via a video bridge.
*
* gpuId
* For each row, this field holds the GPU ID of the GPU
* whose connections are listed in the row.
*
* connectedGpuIds
* For each row, this table holds the GPU IDs of the
* GPUs connected to the GPU identified via the 'gpuId'
* field.
*
* links
* This table holds information about the video bridges
* connected between GPUs in the system. Each row
* represents connections to a single GPU.
*
* Please note: the table only reports video links between already
* attached GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS (0x219U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_VIDEO_LINKS 8U
typedef struct NV0000_CTRL_GPU_VIDEO_LINKS {
NvU32 gpuId;
NvU32 connectedGpuIds[NV0000_CTRL_GPU_MAX_VIDEO_LINKS];
} NV0000_CTRL_GPU_VIDEO_LINKS;
#define NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS {
NV0000_CTRL_GPU_VIDEO_LINKS links[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
} NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_SVM_SIZE
*
@@ -869,5 +923,60 @@ typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NvP64 pData, 8);
} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE
*
* This command is used to set NVLINK bandwidth for power saving
*
* The setting must be applied before the GPU is attached.
* NVLINK_BW_MODE is an NOP for non-NVLink GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_DEVICE
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_STATE
* NV_ERR_IN_USE
*/
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL (0x00U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF (0x01U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN (0x02U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF (0x03U)
#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER (0x04U)
#define NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE (0x286U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x86U)
typedef struct NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS {
NvU8 mode;
} NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE
*
* This command is used to get NVLINK bandwidth for power saving
*
* The setting must be applied before the GPU is attached.
* NVLINK_BW_MODE is an NOP for non-NVLink GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_DEVICE
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_STATE
* NV_ERR_IN_USE
*/
#define NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE (0x287U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS {
NvU8 mode;
} NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS;
/* _ctrl0000gpu_h_ */

31
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
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@@ -296,7 +296,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
/* Generic types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U)
/* processor capabilities */
#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U)
@@ -1583,9 +1584,17 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS {
NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK];
} NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS;
#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */
#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */
#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU)
typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS;
#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU)
typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI
@@ -1621,7 +1630,7 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS {
* NV_ERR_INSUFFICIENT_PERMISSIONS
*
*/
#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U
#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U
#define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS {
@@ -2855,9 +2864,17 @@ typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK];
} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS;
#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */
#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */
#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U)
typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS;
#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U)
typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI
@@ -2893,7 +2910,7 @@ typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
* NV_ERR_INSUFFICIENT_PERMISSIONS
*
*/
#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U
#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U
#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U)
typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS {

5
src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
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@@ -201,10 +201,7 @@ typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS {
* This index is used to request the surface address space type.
* Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE.
*/
typedef struct NV0041_CTRL_SURFACE_INFO {
NvU32 index;
NvU32 data;
} NV0041_CTRL_SURFACE_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO;
/* valid surface info index values */
#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001)

1
src/common/sdk/nvidia/inc/ctrl/ctrl0073.h
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@@ -43,3 +43,4 @@
#include "ctrl0073/ctrl0073svp.h"
#include "ctrl0073/ctrl0073dpu.h"
#include "ctrl0073/ctrl0073psr.h"
#include "ctrl0073/ctrl0073common.h"

1
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
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@@ -39,6 +39,7 @@
#define NV0073_CTRL_SPECIFIC (0x02U)
#define NV0073_CTRL_EVENT (0x03U)
#define NV0073_CTRL_INTERNAL (0x04U)
#define NV0073_CTRL_COMMON (0x05U)
#define NV0073_CTRL_DFP (0x11U)
#define NV0073_CTRL_DP (0x13U)
#define NV0073_CTRL_SVP (0x14U)

33
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h Normal file
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@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073common.finn
//
/* _ctrl0073common_h_ */

12
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -465,7 +465,7 @@ typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS {
/*
* NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG
*
* This enum defines default/primary/secondary sor sublinks to be configured.
* This variable specifies default/primary/secondary sor sublinks to be configured.
* These access modes are:
*
* NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE
@@ -475,11 +475,11 @@ typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS {
* NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK
* Secondary sor sublink to be configured
*/
typedef enum NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG {
NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE = 0,
NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK = 1,
NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK = 2,
} NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG;
typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG;
#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE (0x0U)
#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK (0x1U)
#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK (0x2U)
/*
* NV0073_CTRL_DFP_ASSIGN_SOR_INFO

53
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -728,7 +728,11 @@ typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS {
*
*/
#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x45" */
#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID (0x45U)
typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_GET_LANE_DATA_PARAMS;
/*
@@ -755,7 +759,11 @@ typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS {
*
*/
#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x46" */
#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID (0x46U)
typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS;
/*
* NV0073_CTRL_DP_CSTM
@@ -2764,4 +2772,45 @@ typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
NvBool bDebugValues;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues;
} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS;
/*
* NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY
*
* This command is used to execute RM Over Drive policy and decide if TCON Overdrive needs to be enabled
* or not based on the panel Overdrive grade determined using the panel manufId and prodId.
*
* subDeviceInstance [in]
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId [in]
* This parameter specifies the ID of the eDP display which owns
* the Main Link to be adjusted. The display ID must a eDP display
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
* If more than one displayId bit is set or the displayId is not an eDP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* manfId [in]
* This parameter is an input to this command which tells the
* Internal panel's manufacturer ID.
* prodId [in]
* This parameter is an input to this command which tells the
* Internal panel's product ID.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY (0x731382U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU16 manfId;
NvU16 prodId;
} NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS;
/* _ctrl0073dp_h_ */

13
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -31,17 +31,10 @@
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073system.h"
#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x1U)
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS {
NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS params;
} NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS;
typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS;
/* ctrl0073internal_h */

38
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h
View File

@@ -30,3 +30,41 @@
// Source file: ctrl/ctrl0073/ctrl0073psr.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/*
* NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO
*
* displayId
* Display ID on which this information is being requested.
* frameLockPin
* Returns the frame lock pin of the panel.
* i2cAddress
* Returns the i2c address on which the SR panel is attached.
* NOTE: applies only to LVDS panels, otherwise this field
* should be ignored.
* bSelfRefreshEnabled
* Returns whether SR is enabled in RM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO (0x731602U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID << 8) | NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS {
NvU32 displayId;
NvU32 frameLockPin;
NvU8 i2cAddress;
NvBool bSelfRefreshEnabled;
} NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS;
/* _ctrl0073psr_h_ */

87
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -546,6 +546,44 @@ typedef struct NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS {
#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE (0x00000000U)
#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE (0x00000001U)
/*
* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM
*
* This command is used to signal the resource manager that the audio stream
* is to be mute off or on.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which operation should be directed.
* This parameter must specify a value between zero and the total number
* of subdevices within the parent device. This parameter should be set
* to zero for default behavior.
* displayId
* This parameter specifies the displayId of HDMI resource to configure.
* This comes as input to this command.
* mute
* This field specifies the legal values:
* NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE
* NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM (0x730275U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x75U)
typedef struct NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS {
NvU8 subDeviceInstance;
NvU32 displayId;
NvU8 mute;
} NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS;
#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE (0x00000000U)
#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE (0x00000001U)
/*
@@ -1132,19 +1170,28 @@ typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x91" */
#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x92" */
#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MIN_VALUE 0U
#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MAX_VALUE 100U
typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 brightness;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 brightness;
NvBool bUncalibrated;
} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS;
#define NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x91U)
typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS;
#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x92U)
typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS;
/*
* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS
*
@@ -1329,7 +1376,7 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS {
#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U
#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U
#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID (0xA0U)
@@ -1906,4 +1953,30 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS {
NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS];
} NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS;
/*
* NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY
*
* This command is used to query whether the specified monitor should default
* to adaptive sync.
*
* [in]manufacturerID
* This parameter specifies the 16-bit EDID Manufacturer ID.
* [in]productID
* This parameter specifies the 16-bit EDID Product ID.
* [out]bDefaultAdaptivesync;
* This indicates whether the monitor should default to adaptive sync.
* Possible return values:
* NV_OK
*/
#define NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY (0x7302aeU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID (0xAEU)
typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS {
NvU16 manufacturerID;
NvU16 productID;
NvBool bDefaultAdaptivesync;
} NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS;
/* _ctrl0073specific_h_ */

35
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
View File

@@ -34,6 +34,41 @@
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED
*
* This command returns the support status of the NV stereo emitter
* (also known as the stereo dongle). It reports if the stereo dongle
* is present in terms of the USB interface initialized in Resman.
* This provides a RmControl interface to the STEREO_DONGLE_SUPPORTED
* command in stereoDongleControl.
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleControl
* [IN] bI2cEmitter - I2C driven DT embedded emitter
* [IN] bForcedSupported - GPIO23 driven emitter
* [OUT] support - the control word returned by stereoDongleControl
*
* Possible status values returned are:
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED (0x731702U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
NvBool bI2cEmitter;
NvBool bForcedSupported;
NvU32 support;
} NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS;
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS
*

200
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -468,8 +468,62 @@ typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS {
NvU32 hotplugAlwaysAttached;
} NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE
*
* This command can be used to retrieve dynamic hotplug state information that
* are currently recorded by the RM. This information can be used by the client
* to determine which displays to detect after a hotplug event occurs. Or if
* the client knows that this device generates a hot plug/unplug signal on all
* connectors, then this can be used to cull displays from detection.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* flags
* This parameter specifies optional flags to be used while retrieving
* the hotplug state information.
* Here are the current defined fields:
* NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID
* A client uses this field to determine the lid state.
* Possible values are:
* NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN
* The lid is open.
* NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED
* The lid is closed. The client should remove devices as
* reported inside the
* NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask.
* hotplugAfterEdidMask
* This display mask specifies an NV0073_DISPLAY_MASK value describing
* the set of displays that have seen a hotplug or hotunplug event
* sometime after the last valid EDID read. If the device never has
* a valid EDID read, then it will always be listed here.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE (0x730124U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS {
NvU32 subDeviceInstance;
NvU32 flags;
NvU32 hotplugAfterEdidMask;
} NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS;
/* valid get hoplug state flags */
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID 0:0
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN (0x00000000U)
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U)
/*
* NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP
*
@@ -756,6 +810,136 @@ typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS {
} NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS;
/*
* NV0073_CTRL_SYSTEM_CONNECTOR_INFO
*
* This structure describes a single connector table entry.
*
* type
* This field specifies the connector type.
* displayMask
* This field specifies the the displayMask to which the connector belongs.
* location
* This field specifies the placement of the connector on the platform.
* hotplug
* This field specifies hotplug capabilities (if any) for the connector.
*/
typedef struct NV0073_CTRL_SYSTEM_CONNECTOR_INFO {
NvU32 type;
NvU32 displayMask;
NvU32 location;
NvU32 hotplug;
} NV0073_CTRL_SYSTEM_CONNECTOR_INFO;
/* valid type values */
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN (0x00000000U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_A (0x00000001U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_POD_VGA_15_PIN (0x00000002U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPOSITE (0x00000010U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO (0x00000011U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO_BO_COMPOSITE (0x00000012U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPONENT (0x00000013U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART (0x00000014U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART_EIAJ4120 (0x00000014U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_EIAJ4120 (0x00000017U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_HDTV_YPRPB (0x00000018U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_SVIDEO (0x00000019U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_COMPOSITE (0x0000001AU)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SVIDEO (0x00000020U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_COMPOSITE (0x00000021U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SV_BO_COMPOSITE (0x00000022U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I (0x00000030U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D (0x00000031U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_ADC (0x00000032U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_1 (0x00000038U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_2 (0x00000039U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_SVIDEO (0x0000003AU)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_BNC (0x0000003CU)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG (0x00000040U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM (0x00000041U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG_DET (0x00000042U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM_DET (0x00000043U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TVDS_OEM_ATT (0x00000045U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_UNDOCKED (0x00000050U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_DOCKED (0x00000051U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_UNDOCKED (0x00000052U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_DOCKED (0x00000053U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_UNDOCKED (0x00000052U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_DOCKED (0x00000053U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT (0x00000056U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_INT (0x00000057U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_UNDOCKED (0x00000058U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_DOCKED (0x00000059U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_3PIN_DIN_STEREO (0x00000060U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_A (0x00000061U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_AUDIO_SPDIF (0x00000062U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_C_MINI (0x00000063U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_1 (0x00000064U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_2 (0x00000065U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VIRTUAL_WFD (0x00000070U)
/* valid hotplug values */
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_A_SUPPORTED (0x00000001U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_B_SUPPORTED (0x00000002U)
/*
* Nv0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE
*
* This command can be used to retrieve display connector information.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* version
* This parameter returns the version of the connector table.
* platform
* This parameter returns the type of platform of the associated subdevice.
* connectorTableEntries
* This parameter returns the number of valid entries in the connector
* table.
* connectorTable
* This parameter returns the connector information in the form of an
* array of NV0073_CTRL_SYSTEM_CONNECTOR_INFO structures.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE (0x730165U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID" */
/* maximum number of connector table entries */
#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES (16U)
#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID (0x65U)
typedef struct NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS {
NvU32 subDeviceInstance;
NvU32 version;
NvU32 platform;
NvU32 connectorTableEntries;
/*
* C form:
* NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_CONNECTOR_TABLE_MAX_ENTRIES];
*/
NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES];
} NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS;
/* valid version values */
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_VERSION_30 (0x00000030U)
/* valid platform values */
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_DEFAULT_ADD_IN_CARD (0x00000000U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_TWO_PLATE_ADD_IN_CARD (0x00000001U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_ADD_IN_CARD (0x00000008U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MXM_MODULE (0x00000009U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK (0x00000010U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_LEFT (0x00000011U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_DOCK (0x00000018U)
#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_CRUSH_DEFAULT (0x00000020U)
/*
* NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS
@@ -1090,7 +1274,9 @@ typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x7B" */
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x7BU)
typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS {
NvU32 subDeviceInstance;
@@ -1367,7 +1553,11 @@ typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS {
* the parameters.
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x97" */
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x97U)
typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG
@@ -1378,7 +1568,11 @@ typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS {
* the parameters.
*/
#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x98" */
#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x98U)
typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS;

35
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -62,10 +62,13 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
NvU32 flags;
} NV0080_CTRL_BIF_RESET_PARAMS;
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 2:0
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET (0x00000001)
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR (0x00000002)
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003)
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 3:0
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET 0x1
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR 0x2
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL 0x3
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE 0x4
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6
/*
* NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR
@@ -81,7 +84,7 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U)
@@ -134,5 +137,27 @@ typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS {
NvBool bL1Enable;
} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS;
/*
* NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK
*
* pciePowerControlMask
* pciePowerControlIdentifiedKeyOrder
* pciePowerControlIdentifiedKeyLocation
* ASPM and RTD3 enable/disable information
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK (0x800106) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS {
NvU32 pciePowerControlMask;
NvU32 pciePowerControlIdentifiedKeyOrder;
NvU32 pciePowerControlIdentifiedKeyLocation;
} NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS;
/* _ctrl0080bif_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
View File

@@ -87,7 +87,7 @@
*/
typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK {
NvU32 pageSize;
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8);
NvU32 comptagLine;
NvU32 kind;

22
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -95,10 +95,7 @@ typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS {
* indicates that there is no minimum and the bug is not present on this
* system.
*/
typedef struct NV0080_CTRL_GR_INFO {
NvU32 index;
NvU32 data;
} NV0080_CTRL_GR_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO;
/* valid graphics info index values */
#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000)
@@ -151,13 +148,14 @@ typedef struct NV0080_CTRL_GR_INFO {
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032)
#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000033)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000033)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x34) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO
@@ -210,9 +208,9 @@ typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS {
* disambiguate the target GR engine.
*
*/
#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */
/* Enum for listing TPC partitioning modes */
typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE {
@@ -228,6 +226,14 @@ typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS {
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in]
} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS;
#define NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x7U)
typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS;
#define NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x8U)
typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS;
/**
* NV0080_CTRL_CMD_GR_GET_CAPS_V2
*

1
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h
View File

@@ -88,7 +88,6 @@ typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS {
#define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated
#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P 1:0x40
#define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80
#define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated
#define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
View File

@@ -32,6 +32,7 @@
#include "nvlimits.h"
#include "ctrl0080gr.h"
#include "ctrl0080fifo.h"
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "ctrl/ctrl0080/ctrl0080perf.h"
@@ -91,7 +92,7 @@ typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
/*!
* @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U)

61
src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h
View File

@@ -127,18 +127,18 @@ typedef struct NV00F8_CTRL_DESCRIBE_PARAMS {
} NV00F8_CTRL_DESCRIBE_PARAMS;
/*
* hMemory [IN]
* hMemory
* Physical memory handle to be attached.
*
* offset [IN]
* offset
* Offset into the fabric object.
* Must be physical memory pagesize aligned (at least).
*
* mapOffSet [IN]
* mapOffSet
* Offset into the physical memory descriptor.
* Must be physical memory pagesize aligned.
*
* mapLength [IN]
* mapLength
* Length of physical memory handle to be mapped.
* Must be physical memory pagesize aligned and less than or equal to
* fabric alloc size.
@@ -215,4 +215,57 @@ typedef struct NV00F8_CTRL_DETACH_MEM_PARAMS {
NvU16 numDetached;
} NV00F8_CTRL_DETACH_MEM_PARAMS;
/*
* NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM
*
* Returns number of attached physical memory info to the fabric object in
* a given offset range.
*
* offsetStart [IN]
* Offsets at which memory was attached.
*
* offsetEnd [IN]
* Offsets at which memory was attached.
*
* numMemInfos [OUT]
* Number of memory infos.
*/
#define NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM (0xf80105) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID" */
#define NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offsetStart, 8);
NV_DECLARE_ALIGNED(NvU64 offsetEnd, 8);
NvU16 numMemInfos;
} NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS;
/*
* NV00F8_CTRL_CMD_GET_ATTACHED_MEM
*
* Queries attached physical memory info to the fabric object.
*
* offsetStart [IN]
* Offsets at which memory was attached.
*
* numMemInfos [IN]
* Number of memory infos to be filled.
*
* memInfos [IN/OUT]
* Attached memory infos.
* Use must populate a non-zero `hMemory` handle. This handle will be used by
* RM for duping physical memory.
*/
#define NV00F8_CTRL_CMD_GET_ATTACHED_MEM (0xf80106) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID" */
#define NV00F8_MAX_ATTACHED_MEM_INFOS 64
#define NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offsetStart, 8);
NvU16 numMemInfos;
NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHED_MEM_INFOS], 8);
} NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS;
/* _ctrl00f8_h_ */

63
src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h
View File

@@ -97,8 +97,7 @@ typedef struct NV00FD_CTRL_GET_INFO_PARAMS {
* Physical memory handle to be attached.
*
* offset [IN]
* Offset into the MCFLA object. (Must be zero for now, maybe used in future)
* Must be MCFLA pagesize aligned.
* Offset into the MCFLA object. Must be at least physical pagesize aligned.
*
* mapOffSet [IN]
* Offset into the physical memory descriptor.
@@ -112,15 +111,10 @@ typedef struct NV00FD_CTRL_GET_INFO_PARAMS {
* flags [IN]
* For future use only. Must be zero for now.
*
* devDescriptor [IN]
* devDescriptor is a file descriptor for unix RM clients, but a void
* pointer for windows RM clients. It is transparent to RM clients i.e. RM's
* user-mode shim populates this field on behalf of clients.
*
* Restrictions:
* a. Memory belonging to only NVSwitch P2P supported GPUs
* which can do multicast can be attached
* b. Physical memory with 2MB pagesize is allowed
* b. Physical memory with 2MB or 512MB pagesize is allowed
* c. Memory of an already attached GPU should not be attached
* d. Only vidmem physical memory handle can be attached
*
@@ -136,7 +130,6 @@ typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS {
NV_DECLARE_ALIGNED(NvU64 mapOffset, 8);
NV_DECLARE_ALIGNED(NvU64 mapLength, 8);
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8);
} NV00FD_CTRL_ATTACH_MEM_PARAMS;
/*
@@ -157,4 +150,56 @@ typedef struct NV00FD_CTRL_REGISTER_EVENT_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8);
} NV00FD_CTRL_REGISTER_EVENT_PARAMS;
/*
* NV00FD_CTRL_CMD_ATTACH_GPU
*
* Attaches GPU to the Multicast FLA object. This step must be done before
* attaching memory to the Multicast FLA object.
*
* hSubdevice [IN]
* Subdevice handle of the owner GPU
*
* flags [IN]
* For future use only. Must be zero for now.
*
* devDescriptor [IN]
* devDescriptor is a file descriptor for unix RM clients, but a void
* pointer for windows RM clients. It is transparent to RM clients i.e. RM's
* user-mode shim populates this field on behalf of clients.
*/
#define NV00FD_CTRL_CMD_ATTACH_GPU (0xfd0104) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID" */
#define NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV00FD_CTRL_ATTACH_GPU_PARAMS {
NvHandle hSubdevice;
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8);
} NV00FD_CTRL_ATTACH_GPU_PARAMS;
/*
* NV00FD_CTRL_CMD_DETACH_MEM
*
* Detaches the physical memory handle for a given GPU.
*
* hSubdevice [IN]
* Subdevice handle of the GPU for which memory to be detached.
*
* offset [IN]
* Offset into the MCFLA object at which memory to be detached. Same as
* NV00FD_CTRL_CMD_ATTACH_MEM.
*
* flags [IN]
* For future use only. Must be zero for now.
*/
#define NV00FD_CTRL_CMD_DETACH_MEM (0xfd0105) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */
#define NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS {
NvHandle hSubdevice;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NvU32 flags;
} NV00FD_CTRL_DETACH_MEM_PARAMS;
/* _ctrl00fd_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
View File

@@ -88,6 +88,7 @@
#define NV2080_CTRL_FLA (0x35)
#define NV2080_CTRL_GSP (0x36)
#define NV2080_CTRL_NNE (0x37)
#define NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED (0xb7) /* finn: Evaluated from "(NV2080_CTRL_NNE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_GRMGR (0x38)
#define NV2080_CTRL_UCODE_FUZZER (0x39)
#define NV2080_CTRL_DMABUF (0x3A)

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
View File

@@ -36,10 +36,7 @@
typedef struct NV2080_CTRL_BIOS_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_BIOS_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BIOS_INFO;
/* Maximum number of bios infos that can be queried at once */
#define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F)

11
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
View File

@@ -244,10 +244,7 @@ typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS {
*
*/
typedef struct NV2080_CTRL_BUS_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_BUS_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BUS_INFO;
/* valid bus info index values */
@@ -1397,10 +1394,14 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
* NV_OK and bIsLinkUp is NV_TRUE.
* nrLinks[OUT]
* Total number of C2C links that are up.
* maxNrLinks[OUT]
* Maximum number of C2C links that are supported.
* linkMask[OUT]
* Bitmask of the C2C links present and up.
* perLinkBwMBps[OUT]
* Theoretical per link bandwidth in MBps.
* perLinkLaneWidth[OUT]
* Lane width per link.
* remoteType[OUT]
* Type of the device connected to the remote end of the C2C link.
* Valid values are :
@@ -1427,8 +1428,10 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
NvBool bIsLinkUp;
NvU32 nrLinks;
NvU32 maxNrLinks;
NvU32 linkMask;
NvU32 perLinkBwMBps;
NvU32 perLinkLaneWidth;
NvU32 remoteType;
} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS;

16
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
View File

@@ -228,6 +228,8 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
@@ -269,7 +271,11 @@ typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS {
*
*/
#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */
#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0x7U)
typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS;
#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U)
@@ -324,6 +330,12 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
NvU32 present;
} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0xbU)
typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS;
/* _ctrl2080ce_h_ */

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
View File

@@ -114,10 +114,7 @@ typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
* NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
* This index can be used to request the system address size in bits.
*/
typedef struct NV2080_CTRL_DMA_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_DMA_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_DMA_INFO;
/* valid dma info index values */
#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000)

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
View File

@@ -267,40 +267,6 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS {
} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS {
NvHandle hSemMemory;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO
*

39
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -267,10 +267,7 @@
* Returns the ECC status size (corresponds to subpartitions or channels
* depending on architecture/memory type).
*/
typedef struct NV2080_CTRL_FB_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_FB_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
/* valid fb info index values */
#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated
@@ -686,11 +683,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS {
/* valid values for allocPolicy */
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U)
/*
@@ -707,7 +704,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0xFU)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS;
/*
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM
@@ -773,7 +774,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x18U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead)
@@ -786,7 +791,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0x12U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2
@@ -799,7 +808,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x19U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
/*
@@ -875,7 +888,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U)

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -213,10 +213,7 @@ typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
* This index can be used too get channel groups currently in use per engine/runlist.
*
*/
typedef struct NV2080_CTRL_FIFO_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_FIFO_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO;
/* valid fifo info index values */
#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000)

12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
View File

@@ -332,9 +332,9 @@ typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS {
*
* Get/set the event bitmask for the default queue.
*/
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
@@ -353,6 +353,14 @@ typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
NvU8 queueId;
} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS;
#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID (0x22U)
typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS;
#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID (0x23U)
typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO
*

44
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,14 +23,52 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION (0x20802300) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID (0x00U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS {
NvU32 gpioPin; // in
NvBool bInput; // in
} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT (0x20802301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID (0x01U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS {
NvU32 gpioPin; // in
NvU32 value; // in
} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT (0x20802302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID (0x02U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS {
NvU32 gpioPin; // in
NvU32 value; // out
} NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION (0x20802303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID (0x03U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS {
NvU32 function; // in
NvU32 pin; // in
} NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS;
/* _ctrl2080gpio_h_ */
#include "ctrl/ctrl2080/ctrl2080base.h"

173
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -61,10 +61,7 @@
typedef struct NV2080_CTRL_GPU_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_GPU_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
/* valid gpu info index values */
@@ -108,7 +105,9 @@ typedef struct NV2080_CTRL_GPU_INFO {
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU)
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003eU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003fU)
/* valid minor revision extended values */
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U)
@@ -241,7 +240,9 @@ typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8);
} NV2080_CTRL_GPU_GET_INFO_PARAMS;
#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */
#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS {
NvU32 gpuInfoListSize;
@@ -687,7 +688,9 @@ typedef struct NV2080_CTRL_GPU_REG_OP {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS {
NvHandle hClientTarget;
@@ -1516,6 +1519,10 @@ typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS {
* The board's 699 product part number (LSB justified ASCII field with 0x00
* denoting empty space e.g. "699-21228-0208-200").
*
* board965PartNumber
* The board's 965 product part number (LSB justified ASCII field with 0x00
* denoting empty space e.g. "965-21228-0208-200").
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
@@ -1541,6 +1548,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS {
NvU8 boardRevision[3];
NvU8 boardType;
NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
NvU8 board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
} NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS;
@@ -1867,13 +1875,17 @@ typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */
#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS {
NvU32 attribute;
NvU32 value;
} NV2080_CTRL_CMD_GPU_ILLUM_PARAMS;
#define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U)
typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_SET_ID_ILLUM
*
@@ -1883,7 +1895,11 @@ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */
#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U)
typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION
@@ -2817,7 +2833,11 @@ typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS {
* See confluence page "vGPU UMED Security" for details.
*
*/
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U)
typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE
@@ -3120,12 +3140,11 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OPERATING_SYSTEM
*/
#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */
#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS {
NvU32 gpuInfoListSize;
NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE];
} NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS;
#define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U)
typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS;
/*
* NV2080_CTRL_GPU_SET_PARTITIONING_MODE
@@ -3963,7 +3982,7 @@ typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
* - Total Number of profiles filled
*
* profiles[OUT]
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
*/
#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U)
@@ -4025,11 +4044,11 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
/*
* NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS
*
*
* This command retrieves and constructs the GPU partnumber from the VBIOS.
*
*
* The following data are currently supported:
*
*
* pciDevId
* The PCI device ID
*
@@ -4045,8 +4064,8 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
*/
#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */
/*
* The string format for a GPU part number
/*
* The string format for a GPU part number
* The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string,
* the chip major number, and then the chip minor number.
* Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS
@@ -4112,4 +4131,116 @@ typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS
#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U)
typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Marks the device for reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */
/*
* NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Unmarks the device for reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */
/*
* NV2080_CTRL_CMD_GPU_GET_RESET_STATUS
*
* Gets the current reset status of the device.
*
* bResetNeeded
* Set to NV_TRUE if the device needs to be reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU)
typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS {
NvBool bResetRequired;
} NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Marks the device for drain and reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */
/*
* NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Unmarks the device for drain and reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */
/*
* NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS
*
* Gets the current drain and reset status of the device. Drain and reset is used only SMC configs.
*
* bDrainRecommended
* Set to NV_TRUE if a drain and reset is recommended for the device.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU)
typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS {
NvBool bDrainRecommended;
} NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS;
/*
* NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2
*
* This command returns NVENC software sessions information for the associate GPU.
* This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have
* embedded pointers.
*
* Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information.
*/
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU)
typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS {
NvU32 sessionInfoTblEntry;
NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES];
} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS;
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */
/* _ctrl2080gpu_h_ */

115
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -147,6 +147,9 @@ typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO;
* NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
* This index is used to return the number of "Tensor Cores"
* supported by the graphics pipeline
* NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
* This index is used to return the Graphics capabilities
* supported by the graphics pipeline
*/
typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
@@ -253,6 +256,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
@@ -320,6 +324,19 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D 1:1
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE 2:2
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M 3:3
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U
/**
* NV2080_CTRL_CMD_GR_GET_INFO
*
@@ -389,7 +406,9 @@ typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS {
* ID is given (shareChID), then the 2 channels will share
* the zcull context buffers.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x5" */
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS {
NvHandle hChannel;
@@ -494,7 +513,9 @@ typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS {
NvHandle hChannel;
@@ -542,7 +563,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS {
* ID is given (shareChID), then the 2 channels will share
* the zcull context buffers.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS {
NvHandle hClient;
@@ -580,7 +603,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x9" */
#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
NvHandle hClient;
@@ -607,7 +632,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U
#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xA" */
#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS {
NvU32 mapValueCount;
@@ -645,7 +672,9 @@ typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xE" */
#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS {
NvHandle hChannel;
@@ -724,7 +753,9 @@ typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x10" */
#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS {
NvU32 flags;
@@ -809,7 +840,9 @@ typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x11" */
#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID (0x11U)
typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS {
NvU32 flags;
@@ -842,7 +875,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS {
NvHandle hChannel;
@@ -904,7 +939,9 @@ typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS {
* gfxpSaveCnt
* This parameter returns the number of GfxP saves on the channel.
*/
#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x15" */
#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID (0x15U)
typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS {
NvHandle hChannel;
@@ -1120,12 +1157,14 @@ typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1C" */
#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
#define NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID (0x1CU)
typedef struct NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
NvU32 chID;
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS;
} NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS;
/*
* NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA
@@ -1144,7 +1183,7 @@ typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT 10U
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT 10U
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1D" */
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC {
NV_DECLARE_ALIGNED(NvU64 errorCounter, 8);
@@ -1161,6 +1200,8 @@ typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC gpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT], 8);
} NV2080_CTRL_GR_VAT_ALARM_DATA;
#define NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID (0x1DU)
typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA smVatAlarm, 8);
NvU32 maxGpcCount;
@@ -1209,7 +1250,9 @@ typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS {
* The number of bytes in each slot, i * slotStride gives the offset from the
* base of the pool to a given slot
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1F" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID (0x1FU)
typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
NvU32 maxSlots;
@@ -1233,7 +1276,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
* pControlStructure
* This input is the kernel CPU pointer to the control structure.
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x20" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
@@ -1260,7 +1305,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
* slots
* This input contains an array of the slots to be added to the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x21" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
@@ -1299,7 +1346,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
* many. If there are not enough slots on the freelist to remove the
* requested amount, RM will return the number it was able to remove.
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
@@ -1375,21 +1424,12 @@ typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS {
NvU32 tpcMask;
} NV2080_CTRL_GR_GET_TPC_MASK_PARAMS;
#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x2C" */
#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x2CU)
typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2CU)
typedef struct NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS params, 8);
} NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS;
/*
* NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
*
@@ -1701,21 +1741,12 @@ typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x36" */
#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0x36U)
typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS_MESSAGE_ID (0x36U)
typedef struct NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS params, 8);
} NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS;
/*
* NV2080_CTRL_CMD_GR_GET_ZCULL_MASK
*

17
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
View File

@@ -228,11 +228,18 @@ typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS {
NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)];
} NV2080_CTRL_I2C_RW_REG_PARAMS;
// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */
#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */
// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
#define NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID (0x3U)
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID (0x4U)
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_WRITE_REG_PARAMS;
/*
* NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS
@@ -273,7 +280,7 @@ typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U)

411
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -41,6 +41,7 @@
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrl90f1.h"
#include "ctrl/ctrl30f1.h"
#include "nvcfg_sdk.h"
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO
@@ -206,31 +207,38 @@ typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS {
NvU32 bufferSize;
} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
/*!
* @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS {
NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
* @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240
#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
struct {
@@ -246,10 +254,17 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
NvU16 numTpc;
} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS;
/*!
* Retrieve BSP Static data.
@@ -288,15 +303,14 @@ typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS {
} NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12
#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12
#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10
/*!
* @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK
* @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK
* @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */
@@ -328,6 +342,8 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS {
NvU32 numGfxTpc;
} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
/*!
* floorsweeping masks which are indexed via local GR index
@@ -335,6 +351,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS;
/*
* NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES
*
@@ -382,7 +404,6 @@ typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS {
* @ref NV2080_CTRL_CMD_GR_GET_INFO
* @ref NV2080_CTRL_CMD_GR_GET_INFO_V2
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */
@@ -397,14 +418,21 @@ typedef struct NV2080_CTRL_INTERNAL_GR_INFO {
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO {
NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
} NV2080_CTRL_INTERNAL_STATIC_GR_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */
@@ -421,14 +449,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO {
NvU32 subregionHeightAlignPixels;
} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */
@@ -438,14 +473,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO {
NvU32 ropOperationsCount;
} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */
@@ -453,15 +495,22 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS {
NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
* @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */
@@ -476,14 +525,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */
@@ -499,10 +555,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER {
NvU8 imla4;
} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
/*
* NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
*
@@ -554,9 +618,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
NvBool bEnable;
} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS;
@@ -600,9 +666,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS {
#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS;
@@ -629,6 +697,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE {
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS;
@@ -656,8 +725,6 @@ typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_C
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
NvU32 fecsRecordSize;
NvU32 timestampHiTagMask;
@@ -666,10 +733,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
NvU8 numLowerBitsZeroShift;
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8);
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS;
/**
* NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE
*
@@ -739,16 +814,22 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM
*
@@ -933,6 +1014,8 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
* table [OUT]
* Supported profiles.
*/
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS {
NvU32 count;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8);
@@ -973,6 +1056,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS {
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS {
NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
@@ -1280,7 +1365,11 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS {
/*!
* @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES
*/
#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */
#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU)
typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE
@@ -1299,16 +1388,43 @@ typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS {
/*!
* NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE
*
* tableLen [OUT]
* tableLen [OUT]
* Number of valid records in table field.
*
* table [OUT]
* table [OUT]
* Interrupt table for Kernel RM.
*
* subtreeMap [OUT]
* Subtree range for each NV2080_INTR_CATEGORY.
*/
#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128
/*!
* Categories of interrupts.
*
* Each of these categories get a separate range of interrupt subtrees (top
* level bits).
*/
typedef enum NV2080_INTR_CATEGORY {
NV2080_INTR_CATEGORY_DEFAULT = 0,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
NV2080_INTR_CATEGORY_RUNLIST = 3,
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
NV2080_INTR_CATEGORY_UVM_OWNED = 5,
NV2080_INTR_CATEGORY_UVM_SHARED = 6,
NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
} NV2080_INTR_CATEGORY;
#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX
typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
NvU8 subtreeStart;
NvU8 subtreeEnd;
} NV2080_INTR_CATEGORY_SUBTREE_MAP;
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
NvU16 engineIdx;
NvU32 pmcIntrMask;
@@ -1321,6 +1437,7 @@ typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
NvU32 tableLen;
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
/* Index to retrieve the needed heap space for specific module */
@@ -1438,29 +1555,41 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
/*!
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG
* NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
*
* This command retrieves memory config from HW
*
@@ -1479,8 +1608,9 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
* memBoundaryCfgValInit [OUT]
* Memory boundary config initial value (64KB aligned)
*/
#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U)
typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8);
@@ -1490,6 +1620,12 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
NvU32 memBoundaryCfgValInit;
} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U)
typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8
@@ -1679,6 +1815,10 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */
// Valid fault buffer types
#define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000)
#define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001)
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER
*
@@ -1694,6 +1834,12 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
* shadowFaultBufferPteArray
* Pages of client shadow fault buffer.
*
* shadowFaultBufferType
* Replayable or non-replayable fault buffer
*
* faultBufferSharedMemoryPhysAddr
* Fault buffer shared memory address. Used only by the Replayable fault buffer.
*
* Possible status values returned are:
* NV_OK
*/
@@ -1706,8 +1852,29 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PAR
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8);
NvU32 shadowFaultBufferSize;
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8);
NvU32 shadowFaultBufferType;
NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8);
} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
*
* This command requests physical RM to disable the client shadow fault buffer.
*
* shadowFaultBufferType
* Replayable or non-replayable fault buffer
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU)
typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
NvU32 shadowFaultBufferType;
} NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER
*
@@ -1725,16 +1892,6 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE
NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8);
} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
*
* This command requests physical RM to disable the client shadow fault buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */
/*!
* NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X
*
@@ -1764,7 +1921,7 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U)
@@ -1850,22 +2007,38 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
/*!
* @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U)
typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U)
typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U)
typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U)
typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED
@@ -1877,7 +2050,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
* NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
*
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U)
@@ -1896,8 +2069,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
* gpu instance should behave identically with respect to fragmentation and
* placement / span positioning.
*/
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE
@@ -1908,8 +2082,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
* as the exported gpu instance, but the imported gpu instance should behave
* identically with respect to fragmentation and placement / span positioning.
*/
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4
typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
@@ -1926,6 +2101,22 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8);
} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT
*
@@ -2094,6 +2285,8 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS {
NvU8 hshubId;
} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR
*
@@ -2335,7 +2528,7 @@ typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS {
* P2P Capability is disabled by a regkey.
* NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED
* P2P Capability is not supported.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
@@ -2369,7 +2562,7 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
/*
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE
*
* An internal call to invoke the sequence VGA register reads & writes to
* An internal call to invoke the sequence VGA register reads & writes to
* perform save and restore of VGA
*
* [in] saveOrRestore
@@ -2417,10 +2610,9 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS {
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */
/*!
* NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
@@ -2460,7 +2652,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE {
* - Total Number of profiles filled
*
* profiles[OUT]
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
*/
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU)
@@ -2469,6 +2661,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS {
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS;
/*
@@ -2637,7 +2835,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
/*!
* NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC
*
* Disable the raster sync gpio on the other P2060 GPU
* Disable the raster sync gpio on the other P2060 GPU
* that's connected to master over Video bridge.
*
* [in] bEnableMaster
@@ -2647,7 +2845,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
* If raster sync GPIO direction is saved or not.
*
* [in/out] bRasterSyncGpioDirection
* During save it gets the direction.
* During save it gets the direction.
* In restores it sets the direction.
*
* Possible status values returned are:
@@ -2714,7 +2912,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
* [in] sysOffset
* Offset in SYSMEM region to save to/restore from
* [in] size
* Size of region being saved/restored
* Size of region being saved/restored
*/
#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
@@ -2805,7 +3003,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS
/*!
* NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE
*
* Update the system control capability
* Update the system control capability
*
* bIsSysCtrlSupported [IN]
If the system control is supported
@@ -2843,7 +3041,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI {
NvU32 sensorId;
/*!
* PFM sensor limit value if required
* PFM sensor limit value if required
*/
NvU32 limit;
} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI;
@@ -2900,7 +3098,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
* Sync payload data
*
*/
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU)
typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC
@@ -2914,7 +3116,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
* Sync payload data
*
*/
#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */
#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU)
typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
@@ -2922,7 +3128,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
* Query Coherent FB Aperture Size.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU)
@@ -3168,9 +3374,94 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
NvU32 vPstateIdx;
} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE
*
* This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3
*
* Possible status return values are:
* NV_OK Success
*/
#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS {
NvBool bIsSatisfied;
} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS;
/*
* This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
*/
#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */
/*!
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS
*
* This command is an internal command sent from Kernel RM to Physical RM
* to get number of secure channels supported on SEC2 and CE
*
* maxSec2SecureChannels [OUT]
* maxCeSecureChannels [OUT]
*/
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U)
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
NvU32 maxSec2SecureChannels;
NvU32 maxCeSecureChannels;
} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
*
* This command is an internal command sent from Kernel RM to Physical RM
* to disable the GPU system memory access after quiescing the GPU or
* re-enable sysmem access.
*
* bDisable [IN]
* If NV_TRUE the GPU is quiesced and system memory access is disabled .
* If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)
typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU)
typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS {
NvU32 pinSetIn; // in
NvU32 pinSetOut; // in
NvBool bMasterScanLock; // out
NvU32 masterScanLockPin; // out
NvBool bSlaveScanLock; // out
NvU32 slaveScanLockPin; // out
} NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */
#define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU)
typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS {
NvU32 pinSet; // in
NvU32 gpioFunction; // out
NvU32 gpioPin; // out
NvBool gpioDirection; // out
} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS;
/* ctrl2080internal_h */

42
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -347,23 +347,7 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
*
* This command sets the requested RATED_TDP action corresponding to the
* specified client. @Note, however, that this command is unable to set @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */
#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* Structure containing the requested action for a RATED_TDP client (@ref
@@ -380,6 +364,30 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU)
typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS;
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
*
* This command sets the requested RATED_TDP action corresponding to the
* specified client. @Note, however, that this command is unable to set @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID (0x6FU)
typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS;
/*!
* This struct represents the GPU monitoring perfmon sample for an engine.
*/

24
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
View File

@@ -252,9 +252,17 @@ typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS {
NvU32 rcEnable;
} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */
#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */
#define NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xDU)
typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_SET_RC_RECOVERY_PARAMS;
#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xEU)
typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_GET_RC_RECOVERY_PARAMS;
/* valid values for rcEnable */
#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000)
@@ -353,9 +361,17 @@ typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS {
NvU32 rcBreak;
} NV2080_CTRL_CMD_RC_INFO_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */
#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID (0x11U)
typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_SET_RC_INFO_PARAMS;
#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID (0x12U)
typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_GET_RC_INFO_PARAMS;
/* valid rcMode values */
#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000)

12
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h
View File

@@ -53,7 +53,7 @@
* NV_ERR_INVALID_ARGUMENT
*/
#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x1" */
#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */
typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS {
NvU32 sp;
@@ -62,6 +62,10 @@ typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS {
NvU32 dp;
} NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS;
#define NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x1U)
typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS;
/*
* NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES
*
@@ -82,7 +86,11 @@ typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */
#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x2U)
typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS;

182
src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -199,6 +199,12 @@ typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS {
* useHouseSync
* When a house sync signal is detected, this parameter indicates that it
* should be used as the reference to generate the frame sync signal.
* syncMulDiv
* Enables multiply/divide of the frequency of the house sync signal by an
* integer. Only supported if the
* NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC bit is set. The
* maximum value of multiplyDivideValue is given by
* NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS.maxMulDivValue.
*
* Possible status values returned are:
* NV_OK
@@ -210,48 +216,60 @@ typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS {
#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */
typedef struct NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS {
NvU8 multiplyDivideValue;
NvU8 multiplyDivideMode;
NvU16 rsvd;
} NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS;
typedef struct NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS {
NvU32 which;
NvU32 syncPolarity;
NvU32 syncVideoMode;
NvU32 nSync;
NvU32 syncSkew;
NvU32 syncStartDelay;
NvU32 useHouseSync;
NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS syncMulDiv;
} NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS {
NvU32 which;
NvU32 syncPolarity;
NvU32 syncVideoMode;
NvU32 nSync;
NvU32 syncSkew;
NvU32 syncStartDelay;
NvU32 useHouseSync;
} NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS;
typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS;
#define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U)
typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS;
typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS;
/*
* which values
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002
#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002
#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE
/*
* syncPolarity values
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2
/*
* syncVideoMode values
@@ -259,16 +277,23 @@ typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTRO
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4
/*
* multiplyDivide values
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1
/*
* NV30F1_CTRL_CMD_GSYNC_GET_CAPS
@@ -330,13 +355,18 @@ typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTRO
* programmed into the board has to be between 0 and maxSyncInterval,
* inclusive.
*
* maxMulDivValue
* This parameter returns the maximum possible value that can be
* programmed for multiplying / dividing house sync. Only valid if
* NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC is set.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
* NV_ERR_INVALID_ARGUMENT
*/
#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U)
@@ -353,6 +383,7 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS {
NvU32 maxStartDelay;
NvU32 startDelayResolution;
NvU32 maxSyncInterval;
NvU32 maxMulDivValue;
} NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 (0x00002060)
@@ -363,6 +394,7 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS {
#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS (0x00000004)
#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR (0x00000010)
#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC (0x00000020)
#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT (0x10000000)
#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT (0x20000000)
@@ -482,19 +514,22 @@ typedef struct NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS {
// If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5.
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001)
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS {
typedef struct NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS {
NvU32 gpuId;
NvU32 master;
NvU32 displays;
NvU32 validateExternal;
NvU32 refresh;
NvU32 configFlags;
} NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS;
} NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U)
typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS;
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U)
typedef NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS;
typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS;
/*
* NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC
@@ -705,14 +740,17 @@ typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS {
#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS {
typedef struct NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS {
NvU32 bEmitTestSignal;
} NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS;
} NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U)
typedef NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS;
typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS;
#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U)
typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS;
/*
* NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG
@@ -756,14 +794,17 @@ typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS {
#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U)
typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS {
typedef struct NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS {
NvU32 enable;
} NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS;
} NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U)
typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS;
typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS;
#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U)
typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS;
/*
*
@@ -795,15 +836,18 @@ typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GE
#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U)
typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS {
typedef struct NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS {
NvU32 gpuId;
NvBool enable;
} NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS;
} NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U)
typedef NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS;
typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS;
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U)
typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS;
/*
* NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW
@@ -1285,15 +1329,18 @@ typedef struct NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS {
#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U)
typedef struct NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS {
typedef struct NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS {
NvU32 gpuId;
NvU32 enable;
} NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS;
} NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS;
#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U)
typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS;
#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U)
typedef NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS;
typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS;
/*
* NV30F1_CTRL_CMD_GSYNC_READ_REGISTER
@@ -1478,14 +1525,21 @@ typedef struct NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS {
* NV_ERR_INVALID_STATE
*
*/
#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x87" */
#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x88" */
#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */
typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS {
NvU8 houseSyncMode;
} NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x87U)
typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS;
#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x88U)
typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS;
#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT (0x00)
#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01)

59
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h
View File

@@ -256,65 +256,6 @@ typedef struct NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS {
NvU32 swapLockoutStart;
} NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS;
/*
* NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN
*
* This command returns which lockpin has been connected for the specified
* subdevice in the current SLI and/or framelock configuration.
*
* head
* The head for which the locking is associated with
*
* masterScanLock
* Indicate the connection status and pin number of master scanlock
*
* slaveScanLock
* Indicate the connection status and pin number of slave scanlock
*
* flipLock
* Indicate the connection status and pin number of fliplock
*
* stereoLock
* Indicate the connection status and pin number of stereo lock
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN (0x50700207) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED 0:0
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_PIN 3:1
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED 0:0
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_PIN 3:1
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED 0:0
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_NO (0x00000000)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_YES (0x00000001)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_PIN 3:1
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED 0:0
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_NO (0x00000000)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_YES (0x00000001)
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_PIN 3:1
#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 head;
NvU32 masterScanLock;
NvU32 slaveScanLock;
NvU32 flipLock;
NvU32 stereoLock;
} NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS;
/*
* NV5070_CTRL_CMD_SET_VIDEO_STATUS
*

13
src/common/sdk/nvidia/inc/ctrl/ctrl9067.h
View File

@@ -134,9 +134,7 @@ typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS {
*
*/
#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x1" */
#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x2" */
#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */
#define NV9067_CTRL_CWD_WATERMARK_VALUE_MIN 1
#define NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT 2
@@ -146,5 +144,14 @@ typedef struct NV9067_CTRL_CWD_WATERMARK_PARAMS {
NvU32 watermarkValue;
} NV9067_CTRL_CWD_WATERMARK_PARAMS;
#define NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x1U)
typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_GET_CWD_WATERMARK_PARAMS;
#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */
#define NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x2U)
typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_SET_CWD_WATERMARK_PARAMS;
/* _ctrl9067_h_ */

10
src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h
View File

@@ -81,7 +81,9 @@ typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS {
/*!
* Get VAS page level information.
*/
#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */
#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
/*!
@@ -232,7 +234,11 @@ typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS {
* Get VAS page level information without kernel priviledge. This will internally call
* NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO.
*/
#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */
#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID (0x5U)
typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS;
/*!
* Pin PDEs for a given VA range on the server RM and then mirror the client's page

71
src/common/sdk/nvidia/inc/ctrl/ctrla06c.h
View File

@@ -94,21 +94,12 @@
* NV_ERR_INVALID_OPERATION
*
*/
#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS params;
} NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
/*
* NVA06C_CTRL_CMD_BIND
*
@@ -152,7 +143,15 @@ typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS;
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */
typedef struct NVA06C_CTRL_TIMESLICE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8);
} NVA06C_CTRL_TIMESLICE_PARAMS;
#define NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_SET_TIMESLICE_PARAMS;
/*
* NVA06C_CTRL_CMD_GET_TIMESLICE
@@ -170,11 +169,11 @@ typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS;
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID" */
typedef struct NVA06C_CTRL_TIMESLICE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8);
} NVA06C_CTRL_TIMESLICE_PARAMS;
#define NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_GET_TIMESLICE_PARAMS;
/*
* NVA06C_CTRL_CMD_PREEMPT
@@ -266,7 +265,19 @@ typedef struct NVA06C_CTRL_GET_INFO_PARAMS {
* NV_ERR_INVALID_STATE
* NV_ERR_INSUFFICIENT_PERMISSIONS
*/
#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */
typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS {
NvU32 tsgInterleaveLevel;
} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS;
#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000)
#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001)
#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002)
#define NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x7U)
typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS;
/*
* NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL
@@ -284,15 +295,11 @@ typedef struct NVA06C_CTRL_GET_INFO_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x8" */
#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */
typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS {
NvU32 tsgInterleaveLevel;
} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS;
#define NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x8U)
#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000)
#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001)
#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002)
typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS;
/*
* NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE
@@ -404,7 +411,11 @@ typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS {
* Please see description of NVA06C_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */
#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U)
typedef NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE
@@ -415,7 +426,11 @@ typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS {
* Please see description of NVA06C_CTRL_CMD_SET_TIMESLICE for more information.
*
*/
#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */
#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */
#define NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS;
/* _ctrla06c.h_ */

63
src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h
View File

@@ -38,41 +38,23 @@
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
} NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
/*
* NVA06F_CTRL_RESET_CHANNEL
*
* Please see description of NV906F_CTRL_RESET_CHANNEL for more information.
*/
#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
} NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
/*
* NVA06F_CTRL_CMD_GPFIFO_SCHEDULE
*
@@ -137,21 +119,12 @@ typedef struct NVA06F_CTRL_BIND_PARAMS {
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
} NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
/*
* NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER
*
@@ -192,7 +165,15 @@ typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS {
* NV_ERR_INVALID_STATE
* NV_ERR_INSUFFICIENT_PERMISSIONS
*/
#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x9" */
#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */
typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS {
NvU32 channelInterleaveLevel;
} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS;
#define NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x9U)
typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS;
/*
* NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL
@@ -210,11 +191,11 @@ typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */
#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */
typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS {
NvU32 channelInterleaveLevel;
} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS;
#define NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x10U)
typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS;
/*
* NVA06F_CTRL_CMD_RESTART_RUNLIST

18
src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h
View File

@@ -40,7 +40,11 @@
* Please see description of NVA06F_CTRL_CMD_STOP_CHANNEL for more information.
*
*/
#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */
#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x1U)
typedef NVA06F_CTRL_STOP_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS;
/*
* NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL
@@ -51,7 +55,11 @@
* Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */
#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS;
/*
* NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE
@@ -62,6 +70,10 @@
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x3" */
#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS;
/* ctrla06finternal_h */

30
src/common/sdk/nvidia/inc/ctrl/ctrla080.h
View File

@@ -280,15 +280,19 @@ typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS {
*
*/
#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */
#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID" */
typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS {
typedef struct NVA080_CTRL_SEMA_MEM_PARAMS {
NvHandle hClient;
NvHandle hDevice;
NvHandle hMemory;
NvHandle hCtxDma;
NV_DECLARE_ALIGNED(NvU64 semaAddress, 8);
} NVA080_CTRL_MAP_SEMA_MEM_PARAMS;
} NVA080_CTRL_SEMA_MEM_PARAMS;
#define NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x2U)
typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_MAP_SEMA_MEM_PARAMS;
/*
* NVA080_CTRL_CMD_UNMAP_SEMA_MEM
@@ -308,7 +312,11 @@ typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS {
*
*/
#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */
#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x3U)
typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS;
/*!
* NVA080_CTRL_CMD_SET_FB_USAGE
@@ -322,7 +330,7 @@ typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS {
* Possible status values returned are:
* NV_OK
*/
#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U)
@@ -364,16 +372,18 @@ typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS {
#define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */
#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS {
typedef struct NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS {
NvU32 hClient;
NvU32 hDevice;
NvHandle hMemory;
NvU32 hCtxDma;
NV_DECLARE_ALIGNED(NvU64 semaAddress, 8);
NvU32 semaStride;
} NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS;
} NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS;
#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U)
typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS;
/*!
* NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM
@@ -392,7 +402,7 @@ typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS {
#define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U)
typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS;
typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS;
/*
* NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP

14
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -349,7 +349,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x4" */
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID (0x4U)
typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES
@@ -370,7 +374,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x5" */
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID (0x5U)
typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION
@@ -403,7 +411,7 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U)

42
src/common/sdk/nvidia/inc/ctrl/ctrla084.h
View File

@@ -63,8 +63,7 @@
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS {
NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH];
NvU32 vgpuDeviceInstanceId;
NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH];
} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS;
/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE
@@ -296,7 +295,42 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS {
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS;
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000)
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001)
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000)
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001)
/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GER_BAR_MAPPING_RANGES
*
* This command is used to get Bar mapping ranges in RM.
*
* Parameters:
* offsets [OUT]
* Offsets of the ranges
* sizes [OUT]
* Sizes of the ranges
* mitigated [OUT]
* Specifies whether it's mitigated range
* numRanges [OUT]
* Number of ranges
*
* osPageSize [IN]
* Page size.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES (0xa084010a) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID" */
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES 10
#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID (0xAU)
typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offsets[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8);
NV_DECLARE_ALIGNED(NvU64 sizes[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8);
NvU32 numRanges;
NvU32 osPageSize;
NvBool mitigated[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES];
} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS;
/* _ctrla084_h_ */

92
src/common/sdk/nvidia/inc/ctrl/ctrla16f.h
View File

@@ -65,101 +65,58 @@
* Please see description of NVA06F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x1" */
#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
} NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
/*
* NVA16F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_RESET_CHANNEL for more information.
*
*/
#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x2" */
#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
} NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
/*
* NVA16F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x3" */
#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
} NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
/*
* NVA16F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x4" */
#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA16F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVA16F_CTRL_CMD_BIND_FINN_PARAMS {
NVA16F_CTRL_BIND_PARAMS params;
} NVA16F_CTRL_CMD_BIND_FINN_PARAMS;
/*
* NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x5" */
#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
} NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
/* valid action values */
#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
@@ -182,19 +139,10 @@ typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x7" */
#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
} NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
/* _ctrla16f.h_ */

92
src/common/sdk/nvidia/inc/ctrl/ctrla26f.h
View File

@@ -65,101 +65,58 @@
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x1" */
#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
} NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
/*
* NVA26F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x2" */
#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
} NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
/*
* NVA26F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x3" */
#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
} NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
/*
* NVA26F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x4" */
#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA26F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVA26F_CTRL_CMD_BIND_FINN_PARAMS {
NVA26F_CTRL_BIND_PARAMS params;
} NVA26F_CTRL_CMD_BIND_FINN_PARAMS;
/*
* NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x5" */
#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
} NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
/* valid action values */
#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
@@ -182,19 +139,10 @@ typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x7" */
#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
} NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
/* _ctrla26f.h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrlb069.h
View File

@@ -161,6 +161,8 @@ typedef struct NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS {
* Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0))
* replayableFaultMask
* Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT)
* faultBufferType
* This is an input param denoting replayable/non-replayable fault buffer
*/
#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */
@@ -175,6 +177,7 @@ typedef struct NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8);
NvU32 replayableFaultMask;
NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8);
NvU32 faultBufferType;
} NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS;
/* _ctrlb069_h_ */

126
src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h
View File

@@ -67,103 +67,58 @@
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
} NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
/*
* NVB06F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_RESET_CHANNEL for more information.
*
*/
#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
} NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
/*
* NVB06F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
} NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
/*
* NVB06F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVB06F_CTRL_CMD_BIND_FINN_PARAMS {
NVB06F_CTRL_BIND_PARAMS params;
} NVB06F_CTRL_CMD_BIND_FINN_PARAMS;
/*
* NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
} NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
/* valid action values */
#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
@@ -186,21 +141,12 @@ typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
} NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
/*
* NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE
*
@@ -288,21 +234,12 @@ typedef struct NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS {
* NV_ERR_INVALID_STATE
*/
#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xDU)
typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0xDU)
typedef struct NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS params, 8);
} NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS;
/*
* NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE
*
@@ -399,11 +336,13 @@ typedef struct NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS {
#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PBDMA_FAULTED 4:4
#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ACQUIRE_FAIL 5:5
typedef struct NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS {
NvU32 state;
} NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS;
#define NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0xFU)
typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS {
NvU32 state;
} NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS;
typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS;
/*
* NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE
@@ -449,18 +388,11 @@ typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS {
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */
#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */
typedef NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS;
#define NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0x10U)
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS_MESSAGE_ID (0x10U)
typedef struct NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS {
NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS params;
} NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS;
typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS;
/*
* NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA

121
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
View File

@@ -36,7 +36,7 @@
/*!
* @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM
*/
#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0200) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0204) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */
// FINN PORT: The below type was generated by the FINN port to
@@ -76,4 +76,123 @@ typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS {
NvBool bMemoryProfilingPermitted;
} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS;
#define NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS {
/*!
* [in] Memory handle (RW memory) for streaming records.
* Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize.
*/
NvHandle hMemPmaBuffer;
/*!
* [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer).
*/
NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8);
/*!
* [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
*/
NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
/*!
* [in] Memory handle (RO memory) for streaming number of bytes available.
* Size of this must be of at least @ref pmaBytesAvailableOffset +
* @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE.
*/
NvHandle hMemPmaBytesAvailable;
/*!
* [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable).
*/
NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8);
/*!
* [in] Enable ctxsw for PMA stream.
*/
NvBool ctxsw;
/*!
* [in/out] The PMA Channel Index associated with a given PMA stream.
* This parameter is input when bInputPmaChIdx is true, else it's output parameter.
*/
NvU32 pmaChannelIdx;
/*!
* [out] PMA buffer VA. Note that this is a HWPM Virtual address.
*/
NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
/*!
* [In] This field must be specified by the client to indicate whether the
* pmaChannelIdx is input parameter or output parameter.
*/
NvBool bInputPmaChIdx;
} NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM
*
* Internal logic for PMA Stream Free
*/
#define NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM (0xb0cc0206) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U)
typedef struct NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS {
/*!
* [in] The PMA channel index associated with a given PMA stream.
*/
NvU32 pmaChannelIdx;
} NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS
*
* Get the maximum number of PMA channels
*/
#define NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS (0xb0cc0207) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS {
/*!
* [out] Max number of PMA channels
*/
NvU32 maxPmaChannels;
} NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS;
/*!
* NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES
*
* Internally bind PM resources.
*/
#define NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES (0xb0cc0208) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x8" */
/*!
* NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES
*
* Internally unbind PM resources.
*/
#define NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES (0xb0cc0209) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x9" */
/*!
* NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY
*
* Reserve legacy HWPM resources
*/
#define NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY (0xb0cc020a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0xaU)
typedef struct NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS {
/*!
* [in] Enable ctxsw for HWPM.
*/
NvBool ctxsw;
} NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS;
/* _ctrlb0ccinternal_h_ */

94
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -109,7 +109,7 @@ typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS {
* for streaming the updated bytes available in the buffer.
*
*/
#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x5" */
#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */
/*!
* Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page
@@ -118,6 +118,8 @@ typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS {
#define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */
#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */
#define NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS {
/*!
* [in] Memory handle (RW memory) for streaming records.
@@ -181,6 +183,8 @@ typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS {
NvU32 pmaChannelIdx;
} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS;
/*!
* NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
*
@@ -258,6 +262,11 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS {
* [in] The PMA Channel Index associated with a given PMA stream.
*/
NvU32 pmaChannelIdx;
/*!
* [out] Set to TRUE if PMA buffer has overflowed.
*/
NvBool bOverflowStatus;
} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS;
/*!
@@ -440,9 +449,7 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS {
#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63)
#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU)
typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS {
typedef struct NVB0CC_CTRL_HS_CREDITS_PARAMS {
/*!
* [in] The PMA Channel Index associated with a given PMA stream.
*/
@@ -462,7 +469,11 @@ typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS {
* [in] Credit programming per chiplet
*/
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS;
} NVB0CC_CTRL_HS_CREDITS_PARAMS;
#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU)
typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_SET_HS_CREDITS_PARAMS;
/*!
* NVB0CC_CTRL_CMD_GET_HS_CREDITS
@@ -470,10 +481,79 @@ typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS {
* Gets per chiplet (pmm router) high speed streaming credits for a pma channel.
*
*/
#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xF" */
#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID" */
typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS;
#define NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID (0xFU)
typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS;
typedef enum NVB0CC_CTRL_HES_TYPE {
NVB0CC_CTRL_HES_INVALID = 0,
NVB0CC_CTRL_HES_CWD = 1,
} NVB0CC_CTRL_HES_TYPE;
typedef struct NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS {
/*!
* [in] Enable ctxsw for HES_CWD.
*/
NvBool ctxsw;
} NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS;
/*
* NVB0CC_CTRL_HES_RESERVATION_UNION
*
* Union of all HES reservation params
*
*/
typedef union NVB0CC_CTRL_HES_RESERVATION_UNION {
NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS cwd;
} NVB0CC_CTRL_HES_RESERVATION_UNION;
/*!
* NVB0CC_CTRL_CMD_RESERVE_HES
*
* Reserves HES for use by the calling client.
* This PM system will only be accessible if this reservation is
* taken.
*
* This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HES.
*
* Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
*
*/
#define NVB0CC_CTRL_CMD_RESERVE_HES (0xb0cc0113) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID (0x13U)
typedef struct NVB0CC_CTRL_RESERVE_HES_PARAMS {
/*!
* [in] Denotes the HES reservation type. Choose from @NVB0CC_CTRL_HES_TYPE.
*/
NvU32 type;
/*!
* [in] Union of all possible reserve param structs. Initialize the reserveParams corresponding to the chosen type.
*/
NVB0CC_CTRL_HES_RESERVATION_UNION reserveParams;
} NVB0CC_CTRL_RESERVE_HES_PARAMS;
/*!
* NVB0CC_CTRL_CMD_RELEASE_HES
*
* Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HES.
*
*/
#define NVB0CC_CTRL_CMD_RELEASE_HES (0xb0cc0114) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID (0x14U)
typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
/*!
* [in] type of @NVB0CC_CTRL_HES_TYPE needs to be released.
*/
NVB0CC_CTRL_HES_TYPE type;
} NVB0CC_CTRL_RELEASE_HES_PARAMS;
/* _ctrlb0ccprofiler_h_ */

92
src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h
View File

@@ -65,101 +65,58 @@
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
} NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
/*
* NVC06F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_RESET_CHANNEL for more information.
*
*/
#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
} NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
/*
* NVC06F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
} NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
/*
* NVC06F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVC06F_CTRL_CMD_BIND_FINN_PARAMS {
NVC06F_CTRL_BIND_PARAMS params;
} NVC06F_CTRL_CMD_BIND_FINN_PARAMS;
/*
* NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params;
} NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS;
/* valid action values */
#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
@@ -182,19 +139,10 @@ typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS {
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
} NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
/* _ctrlc06f.h_ */

48
src/common/sdk/nvidia/inc/ctrl/ctrlc369.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -106,4 +106,50 @@ typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8);
} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS;
/*
* NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUFFER
*
* This call creates and registers a client buffer for the replayable faults
*
* pShadowBuffer [OUT]
* This parameter represents the pointer to the shadow buffer
*
* bufferSize [OUT]
* Size in bytes of the shadow buffer for non replayable faults
*
* Possible status values returned are:
* NV_OK
*/
#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF (0xc3690103) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */
#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8);
NvU32 bufferSize;
} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS;
/*
* NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUFFER
*
* This call unregisters and destroys a client buffer for the replayable
* faults
*
* pShadowBuffer [IN]
* This parameter represents the pointer to the shadow buffer
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF (0xc3690104) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */
#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8);
} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS;
/* _ctrlc369_h_ */

75
src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h
View File

@@ -67,83 +67,47 @@
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS {
NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS params;
} NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS;
/*
* NVC36F_CTRL_RESET_CHANNEL
*
* Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS {
NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS params;
} NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS;
/*
* NVC36F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS {
NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS params;
} NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS;
/*
* NVC36F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC36F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVC36F_CTRL_CMD_BIND_FINN_PARAMS {
NVC36F_CTRL_BIND_PARAMS params;
} NVC36F_CTRL_CMD_BIND_FINN_PARAMS;
/*
* NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
@@ -175,21 +139,12 @@ typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC36F_CTRL_EVENT_SET_NOTIFICA
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */
#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U)
typedef struct NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS {
NV_DECLARE_ALIGNED(NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8);
} NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS;
/*
* NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
*

21
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h
View File

@@ -185,7 +185,7 @@ typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS {
#define NVC370_CTRL_CMD_SET_ACCL (0xc3700102) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */
#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | 0x3" */
#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */
#define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE
#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW
@@ -204,28 +204,21 @@ typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS {
#define NVC370_CTRL_ACCL_SKIP_SYNCPOINT NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT
#define NVC370_CTRL_ACCL_IGNORE_TIMESTAMP NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP
#define NVC370_CTRL_ACCL_IGNORE_MGI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI
#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U)
typedef struct NVC370_CTRL_SET_ACCL_PARAMS {
typedef struct NVC370_CTRL_ACCL_PARAMS {
NVC370_CTRL_CMD_BASE_PARAMS base;
NvU32 channelClass;
NvU32 channelInstance;
NvU32 accelerators;
NvU32 accelMask;
} NVC370_CTRL_SET_ACCL_PARAMS;
typedef NVC370_CTRL_SET_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS;
} NVC370_CTRL_ACCL_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS {
NVC370_CTRL_GET_ACCL_PARAMS params;
} NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS;
#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U)
typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_SET_ACCL_PARAMS;
#define NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0x3U)
typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS;
/*
* NVC370_CTRL_CMD_GET_CHANNEL_INFO

1
src/common/sdk/nvidia/inc/ctrl/ctrlc637.h
View File

@@ -302,6 +302,7 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO {
NvU8 uuid[NVC637_UUID_LEN];
NvU32 sharedEngFlags;
NvU32 gpcMask;
NvU32 gfxGpcCount;
NvU32 veidOffset;
NvU32 veidCount;
NvU32 smCount;

242
src/common/sdk/nvidia/inc/ctrl/ctrlc763.h Normal file
View File

@@ -0,0 +1,242 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc763.finn
//
#include "ctrl/ctrlxxxx.h"
/* Vidmem Access bit buffer control commands and parameters */
#define NVC763_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC763, NVC763_CTRL_##cat, idx)
/* MMU_VIDMEM_ACCESS_BIT_BUFFER command categories (6bits) */
#define NVC763_CTRL_RESERVED (0x00)
#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER (0x01)
/*
* SW def for number of range checkers. Current value taken from
* NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1
* on GA102. Compile time assert to check that the below
* definition is consistent with HW manuals is included in
* each gmmu HAL where this is relevant.
*/
#define NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS 8
/*
* NVC763_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NVC763_CTRL_CMD_NULL (0xc7630000) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */
#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_ENABLE_LOGGING (0xc7630101) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID" */
// Supported granularities for the vidmem access bit buffer logging
typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY {
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64KB = 0,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128KB = 1,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256KB = 2,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512KB = 3,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1MB = 4,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2MB = 5,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_4MB = 6,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_8MB = 7,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_16MB = 8,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_32MB = 9,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64MB = 10,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128MB = 11,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256MB = 12,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512MB = 13,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1GB = 14,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2GB = 15,
} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY;
/**
* enum of disable mode to be used when the MMU enters protected mode
*/
typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE {
/*!
* Disable mode will set all the access/dirty bits as '0'
*/
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_CLEAR = 0,
/*!
* Disable mode will set all the access/dirty bits as '1'
*/
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_SET = 1,
} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE;
//
// If clients want to enable logging specifically for some MMU, clients need to
// do it in a loop
//
typedef enum NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE {
/*!
* Read/Write Attrs only for HUBMMU registers
*/
NV_VIDMEM_ACCESS_BIT_BUFFER_HUBMMU = 0,
/*!
* Read/Write Attrs only for GPCMMU registers
*/
NV_VIDMEM_ACCESS_BIT_BUFFER_GPCMMU = 1,
/*!
* Read/Write Attrs only for HSHUBMMU registers
*/
NV_VIDMEM_ACCESS_BIT_BUFFER_HSHUBMMU = 2,
/*!
* Default will enable for all MMU possible
*/
NV_VIDMEM_ACCESS_BIT_BUFFER_DEFAULT = 3,
} NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE;
typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE {
/*!
Mode to track access bits
*/
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_ACCESS = 0,
/*!
Mode to track dirty bits
*/
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_DIRTY = 1,
} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE;
/*
* NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS
*
* This structure is used to enable logging of the VAB and specifies
* the requested configuration for the 8 independent range checkers.
* The tracking mode and disable mode are the same for all range checkers.
*/
#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS {
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY granularity[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS];
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE trackMode;
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE disableMode;
NV_DECLARE_ALIGNED(NvU64 startAddress[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS], 8);
NvU8 rangeCount;
NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE mmuType;
} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS;
#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DISABLE_LOGGING (0xc7630102) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | 0x2" */
/*
* NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_BUFFER_DUMP
*
* This call initiates the dump request with the properties set using enable
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DUMP (0xc7630103) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID" */
/*
* NV_VAB_OP enumerates the types of dumps supported
*
* The options are:
*
* AGGREGATE
* Collects access buffer bits over multiple dumps using a bitwise OR.
*
* DIFF
* Sets a bit to 1 if it changed from 0 to 1 with this dump. If a bit was
* cleared since the last dump it will be 0. If a bit does not change
* with this dump it will be 0.
*
* CURRENT
* Copies the current access bit buffer state as is from HW. This operation
* clears any underlying aggregation from previous dumps with the other
* two operations.
*
* INVALID
* Should be unused and otherwise indicates error
*/
typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP {
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_AGGREGATE = 0,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_DIFF = 1,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_CURRENT = 2,
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_INVALID = 3,
} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP;
/*
* NVC763_CTRL_VIDMEM_ACCESS_BIT_DUMP_PARAMS
*
* This structure records the dumped bits for the client
* masked by the client's access bit mask determined
* during VidmemAccessBitBuffer construction.
*
* bMetadata [IN]
* Whether or not clients want disable data.
*
* op_enum [IN]
* A member of NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP controlling the type of dump.
*
* accessBits [OUT]
* The client's access bits masked according to the client's access bit mask.
*
* gpcDisable [OUT]
* The GPC disable data from the VAB dump. See GPC_DISABLE in the Ampere-801 FD.
*
* hubDisable [OUT]
* The HUB disable data from the VAB dump. See HUB_DISABLE in the Ampere-801 FD.
*
* hsceDisable [OUT]
* The HSCE disable data from the VAB dump. See HSCE_DIS in the Ampere-801 FD.
*
* linkDisable [OUT]
* The LINK disable data from the VAB dump. See LINK_DIS in the Ampere-801 FD.
*/
#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID (0x3U)
typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS {
NvBool bMetadata;
NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP op_enum;
NV_DECLARE_ALIGNED(NvU64 accessBits[64], 8);
NV_DECLARE_ALIGNED(NvU64 gpcDisable, 8);
NvU32 hubDisable;
NvU16 hsceDisable;
NvU8 linkDisable;
} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS;
#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_PUT_OFFSET (0xc7630104) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID" */
#define NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID (0x4U)
typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS {
NvU32 vidmemAccessBitPutOffset;
} NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS;
/* _ctrlc763_h_ */

7
src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h
View File

@@ -23,6 +23,8 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlxxxx.finn
@@ -65,3 +67,8 @@
#define NVxxxx_CTRL_LEGACY_PRIVILEGED (0xC0)
#define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80)
typedef struct NVXXXX_CTRL_XXX_INFO {
NvU32 index;
NvU32 data;
} NVXXXX_CTRL_XXX_INFO;

49
src/common/sdk/nvidia/inc/finn_rm_api.h → src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -40,7 +40,7 @@
* FINN compiler version
*/
#define FINN_VERSION_MAJOR 1
#define FINN_VERSION_MINOR 15
#define FINN_VERSION_MINOR 17
#define FINN_VERSION_PATCH 0
typedef struct FINN_RM_API
@@ -52,6 +52,17 @@ typedef struct FINN_RM_API
} FINN_RM_API;
/*!
* @brief Private functions not to be called directly
*/
/**@{*/
NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char **dst, NvLength dst_size, NvBool seri_up);
NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up);
/**@}*/
/*!
* @brief Serializes an RM API control params struct and copies it into the
* serialization buffer as a FINN message.
@@ -67,7 +78,7 @@ typedef struct FINN_RM_API
*
* @param[in] interface FINN interface ID of the param struct.
* @param[in] message FINN message ID of the param struct.
* @param[in] src Pointer to the source param struct from which to
* @param[in] api Pointer to the source param struct from which to
* copy the data.
* @param[in, out] dst Double pointer to the destination buffer into
* which to copy the data. *dst will be set to
@@ -85,8 +96,14 @@ typedef struct FINN_RM_API
* @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small.
*/
/**@{*/
NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size);
NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size);
static NV_INLINE NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *api, NvU8 **dst, NvLength dst_size)
{
return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char **) dst, dst_size, NV_TRUE);
}
static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *api, NvU8 **dst, NvLength dst_size)
{
return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char **) dst, dst_size, NV_FALSE);
}
/**@}*/
@@ -113,9 +130,9 @@ NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src
* deserialization on failure.
* @param[in] src_size Maximum size of the source buffer measured in
* `NvU8` units.
* @param[in, out] dst Pointer to the destination param struct into which
* @param[in, out] api Pointer to the destination param struct into which
* to copy the data.
* @param[in] dst_size Size of the destination param struct measured in
* @param[in] api_size Size of the destination param struct measured in
* `char` units per `sizeof` operator.
*
* @retval NV_OK Deserialization successful.
@@ -129,10 +146,17 @@ NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src
* @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch.
*/
/**@{*/
NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size);
NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size);
static NV_INLINE NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *api, NvLength api_size)
{
return finnDeserializeInternal_FINN_RM_API((const char **) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_FALSE);
}
static NV_INLINE NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *api, NvLength api_size)
{
return finnDeserializeInternal_FINN_RM_API((const char **) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_TRUE);
}
/**@}*/
/*!
* @brief Calculates the serialized size of an RM API param struct.
*
@@ -145,6 +169,7 @@ NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLen
*/
NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src);
/*!
* @brief Fetches the unserialized size of an API param struct.
*
@@ -158,6 +183,7 @@ NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src
*/
NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message);
#define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U)
typedef FINN_RM_API NV_RM_ALLOC_INTERFACE;
#define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U)
@@ -217,6 +243,8 @@ typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED;
typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY;
#define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U)
typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED;
#define FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID (0x7305U)
typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_COMMON;
#define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U)
typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP;
#define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U)
@@ -224,7 +252,8 @@ typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP;
#define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U)
typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL;
#define FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID (0x7316U)
typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_PSR;
#define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U)
typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC;
#define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U)
@@ -363,6 +392,8 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR;
#define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC;
#define FINN_NV20_SUBDEVICE_0_NNE_INTERFACE_ID (0x208037U)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NNE;
#define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD;

24
src/common/sdk/nvidia/inc/nv-hypervisor.h
View File

@@ -90,30 +90,6 @@ typedef enum VGPU_DEVICE_STATE_E
NV_VGPU_DEV_IN_USE = 2
} VGPU_DEVICE_STATE;
typedef enum _VMBUS_CMD_TYPE
{
VMBUS_CMD_TYPE_INVALID = 0,
VMBUS_CMD_TYPE_SETUP = 1,
VMBUS_CMD_TYPE_SENDPACKET = 2,
VMBUS_CMD_TYPE_CLEANUP = 3,
} VMBUS_CMD_TYPE;
typedef struct
{
NvU32 request_id;
NvU32 page_count;
NvU64 *pPfns;
void *buffer;
NvU32 bufferlen;
} vmbus_send_packet_cmd_params;
typedef struct
{
NvU32 override_sint;
NvU8 *nv_guid;
} vmbus_setup_cmd_params;
/*
* Function prototypes
*/

2
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -119,7 +119,7 @@
#define INFOROM_FS_ERROR (125)
#define ALI_TRAINING_FAIL (136)
#define ROBUST_CHANNEL_LAST_ERROR (ALI_TRAINING_FAIL)
#define NVLINK_FLA_PRIV_ERR (137)
// Indexed CE reference

73
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -607,7 +607,6 @@ typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32
#define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6
#define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7
// NVOS32 function
#define NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT 1
#define NVOS32_FUNCTION_ALLOC_SIZE 2
#define NVOS32_FUNCTION_FREE 3
// #define NVOS32_FUNCTION_HEAP_PURGE 4
@@ -684,32 +683,6 @@ typedef struct
union
{
// NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT
struct
{
NvU32 owner; // [IN] - memory owner ID
NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated)
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 depth; // [IN] - depth of surface in bits
NvU32 width; // [IN] - width of surface in pixels
NvU32 height; // [IN] - height of surface in pixels
NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 format; // [IN/OUT] - format requested, and format allocated
NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated
NvU32 zcullCovg; // [OUT] - zcull covg allocated
NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses
NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated
NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on
NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset
NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit
NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address
NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range
NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
} AllocDepthWidthHeight;
// NVOS32_FUNCTION_ALLOC_SIZE
struct
{
@@ -1800,15 +1773,6 @@ typedef struct
#define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000)
#define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001)
// Systems with a coherent NVLINK2 connection between the CPU and GPU
// have the option of directly mapping video memory over that connection.
// During mapping you may specify a preference.
//
#define NVOS33_FLAGS_BUS 21:20
#define NVOS33_FLAGS_BUS_ANY 0
#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1
#define NVOS33_FLAGS_BUS_PCIE 2
// Internal use only
#define NVOS33_FLAGS_OS_DESCRIPTOR 22:22
#define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000)
@@ -2885,6 +2849,43 @@ typedef struct
NvV32 status; // [OUT] status of call
} NV_GSP_TEST_SEND_EVENT_NOTIFICATION_PARAMETERS;
/*
* NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH
* NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT
* Location is Coherent System memory (also the default option)
* NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH
* Location is Non-Coherent System memory
* NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID
* Location is FB
*
* Currently only used by MODS for the V1 VAB interface. To be deleted.
*/
typedef enum
{
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = 0,
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH,
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH,
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID
} NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE;
/**
* @brief Multiclient vidmem access bit allocation params
*/
typedef struct
{
/* [OUT] Dirty/Access tracking */
NvBool bDirtyTracking;
/* [OUT] Current tracking granularity */
NvU32 granularity;
/* [OUT] 512B Access bit mask with 1s set on
bits that are reserved for this client */
NV_DECLARE_ALIGNED(NvU64 accessBitMask[64], 8);
/* Number of entries of vidmem access buffer. Used by VAB v1 - to be deleted */
NvU32 noOfEntries;
/* Address space of the vidmem access bit buffer. Used by VAB v1 - to be deleted */
NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE addrSpace;
} NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS;
/**
* @brief HopperUsermodeAParams
* This set of optionalparameters is passed in on allocation of