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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-11 16:19:53 +00:00
530.30.02
This commit is contained in:
Andy Ritger
@@ -36,7 +36,7 @@
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/*!
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* @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM
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*/
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#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0200) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0204) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */
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// FINN PORT: The below type was generated by the FINN port to
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@@ -76,4 +76,123 @@ typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS {
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NvBool bMemoryProfilingPermitted;
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} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS;
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#define NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x4U)
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typedef struct NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS {
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/*!
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* [in] Memory handle (RW memory) for streaming records.
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* Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize.
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*/
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NvHandle hMemPmaBuffer;
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/*!
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* [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer).
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8);
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/*!
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* [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX.
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8);
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/*!
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* [in] Memory handle (RO memory) for streaming number of bytes available.
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* Size of this must be of at least @ref pmaBytesAvailableOffset +
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* @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE.
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*/
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NvHandle hMemPmaBytesAvailable;
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/*!
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* [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable).
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8);
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/*!
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* [in] Enable ctxsw for PMA stream.
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*/
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NvBool ctxsw;
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/*!
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* [in/out] The PMA Channel Index associated with a given PMA stream.
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* This parameter is input when bInputPmaChIdx is true, else it's output parameter.
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*/
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NvU32 pmaChannelIdx;
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/*!
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* [out] PMA buffer VA. Note that this is a HWPM Virtual address.
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*/
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NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8);
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/*!
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* [In] This field must be specified by the client to indicate whether the
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* pmaChannelIdx is input parameter or output parameter.
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*/
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NvBool bInputPmaChIdx;
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} NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM
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*
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* Internal logic for PMA Stream Free
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*/
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#define NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM (0xb0cc0206) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U)
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typedef struct NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS {
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/*!
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* [in] The PMA channel index associated with a given PMA stream.
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*/
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NvU32 pmaChannelIdx;
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} NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS
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*
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* Get the maximum number of PMA channels
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*/
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#define NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS (0xb0cc0207) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID (0x7U)
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typedef struct NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS {
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/*!
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* [out] Max number of PMA channels
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*/
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NvU32 maxPmaChannels;
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} NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES
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*
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* Internally bind PM resources.
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*/
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#define NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES (0xb0cc0208) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x8" */
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/*!
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* NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES
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*
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* Internally unbind PM resources.
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*/
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#define NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES (0xb0cc0209) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x9" */
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/*!
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* NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY
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*
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* Reserve legacy HWPM resources
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*/
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#define NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY (0xb0cc020a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0xaU)
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typedef struct NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS {
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/*!
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* [in] Enable ctxsw for HWPM.
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*/
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NvBool ctxsw;
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} NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS;
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/* _ctrlb0ccinternal_h_ */
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@@ -109,7 +109,7 @@ typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS {
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* for streaming the updated bytes available in the buffer.
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*
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*/
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#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x5" */
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#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */
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/*!
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* Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page
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@@ -118,6 +118,8 @@ typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS {
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#define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */
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#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */
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#define NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x5U)
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typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS {
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/*!
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* [in] Memory handle (RW memory) for streaming records.
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@@ -181,6 +183,8 @@ typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS {
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NvU32 pmaChannelIdx;
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} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_BIND_PM_RESOURCES
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*
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@@ -258,6 +262,11 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS {
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* [in] The PMA Channel Index associated with a given PMA stream.
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*/
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NvU32 pmaChannelIdx;
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/*!
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* [out] Set to TRUE if PMA buffer has overflowed.
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*/
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NvBool bOverflowStatus;
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} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS;
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/*!
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@@ -440,9 +449,7 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS {
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#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63)
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#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU)
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typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS {
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typedef struct NVB0CC_CTRL_HS_CREDITS_PARAMS {
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/*!
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* [in] The PMA Channel Index associated with a given PMA stream.
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*/
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@@ -462,7 +469,11 @@ typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS {
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* [in] Credit programming per chiplet
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*/
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NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
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} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS;
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} NVB0CC_CTRL_HS_CREDITS_PARAMS;
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#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU)
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typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_SET_HS_CREDITS_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_GET_HS_CREDITS
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@@ -470,10 +481,79 @@ typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS {
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* Gets per chiplet (pmm router) high speed streaming credits for a pma channel.
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*
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*/
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#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xF" */
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#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID" */
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typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS;
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#define NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID (0xFU)
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typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS;
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typedef enum NVB0CC_CTRL_HES_TYPE {
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NVB0CC_CTRL_HES_INVALID = 0,
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NVB0CC_CTRL_HES_CWD = 1,
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} NVB0CC_CTRL_HES_TYPE;
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typedef struct NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS {
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/*!
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* [in] Enable ctxsw for HES_CWD.
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*/
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NvBool ctxsw;
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} NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS;
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/*
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* NVB0CC_CTRL_HES_RESERVATION_UNION
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*
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* Union of all HES reservation params
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*
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*/
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typedef union NVB0CC_CTRL_HES_RESERVATION_UNION {
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NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS cwd;
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} NVB0CC_CTRL_HES_RESERVATION_UNION;
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/*!
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* NVB0CC_CTRL_CMD_RESERVE_HES
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*
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* Reserves HES for use by the calling client.
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* This PM system will only be accessible if this reservation is
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* taken.
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*
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* This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HES.
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*
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* Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY.
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*
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*/
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#define NVB0CC_CTRL_CMD_RESERVE_HES (0xb0cc0113) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID (0x13U)
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typedef struct NVB0CC_CTRL_RESERVE_HES_PARAMS {
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/*!
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* [in] Denotes the HES reservation type. Choose from @NVB0CC_CTRL_HES_TYPE.
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*/
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NvU32 type;
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/*!
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* [in] Union of all possible reserve param structs. Initialize the reserveParams corresponding to the chosen type.
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*/
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NVB0CC_CTRL_HES_RESERVATION_UNION reserveParams;
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} NVB0CC_CTRL_RESERVE_HES_PARAMS;
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/*!
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* NVB0CC_CTRL_CMD_RELEASE_HES
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*
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* Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HES.
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*
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*/
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#define NVB0CC_CTRL_CMD_RELEASE_HES (0xb0cc0114) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID" */
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#define NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID (0x14U)
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typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
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/*!
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* [in] type of @NVB0CC_CTRL_HES_TYPE needs to be released.
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*/
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NVB0CC_CTRL_HES_TYPE type;
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} NVB0CC_CTRL_RELEASE_HES_PARAMS;
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/* _ctrlb0ccprofiler_h_ */
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