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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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257
src/common/inc/displayport/displayport.h
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@@ -129,6 +129,7 @@ typedef enum
linkBW_8_10Gbps = 0x1E,
linkBW_Supported
} DP_LINK_BANDWIDTH;
// TODO-@vduraisamy - below enum needs to be moved back to displayport2x.h
typedef enum
{
// enum value unit = 10M
@@ -140,7 +141,12 @@ typedef enum
dp2LinkRate_3_24Gbps = 0x0144, // 324
dp2LinkRate_4_32Gbps = 0x01B0, // 432
dp2LinkRate_5_40Gbps = 0x021C, // 540
dp2LinkRate_6_75Gbps = 0x02A3, // 675
dp2LinkRate_8_10Gbps = 0x032A, // 810
dp2LinkRate_5_00Gbps = 0x01F4, // 500
dp2LinkRate_10_0Gbps = 0x03E8, // 1000
dp2LinkRate_13_5Gbps = 0x0546, // 1350
dp2LinkRate_20_0Gbps = 0x07D0, // 2000
dp2LinkRate_Supported
} DP2X_LINKRATE_10M;
@@ -159,14 +165,34 @@ typedef enum
dataRate_8_10Gbps = 810000000
} DP_LINK_8B_10B_DATA_RATES;
#define IS_8B_10B_CODING(dataRate) (((NvU64)(val)== dataRate_1_62Gbps) || \
((NvU64)(val)== dataRate_2_16Gbps) || \
((NvU64)(val)== dataRate_2_43Gbps) || \
((NvU64)(val)== dataRate_2_70Gbps) || \
((NvU64)(val)== dataRate_3_24Gbps) || \
((NvU64)(val)== dataRate_4_32Gbps) || \
((NvU64)(val)== dataRate_5_40Gbps) || \
((NvU64)(val)== dataRate_8_10Gbps))
#define IS_8B_10B_CODING(dataRate) (((NvU64)(dataRate)== dataRate_1_62Gbps) || \
((NvU64)(dataRate)== dataRate_2_16Gbps) || \
((NvU64)(dataRate)== dataRate_2_43Gbps) || \
((NvU64)(dataRate)== dataRate_2_70Gbps) || \
((NvU64)(dataRate)== dataRate_3_24Gbps) || \
((NvU64)(dataRate)== dataRate_4_32Gbps) || \
((NvU64)(dataRate)== dataRate_5_40Gbps) || \
((NvU64)(dataRate)== dataRate_8_10Gbps))
typedef enum
{
// Uses 128b/132b channel encoding
// Link Data Rate = link rate * (128 / 132) / 8
// = link rate * 4 / 33
dataRate_UHBR_2_50Gbps = 303030303,
dataRate_UHBR_2_70Gbps = 327272727,
dataRate_UHBR_5_00Gbps = 606060606,
dataRate_UHBR_10_00Gbps = 1212121212,
dataRate_UHBR_13_50Gbps = 1636363636,
dataRate_UHBR_20_10Gbps = 2424242424U
} DP_LINK_128B_132B_DATA_RATES;
#define IS_128B_132B_CODING(dataRate) (((NvU64)(dataRate)== dataRate_UHBR_2_50Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_2_70Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_5_00Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_10_00Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_13_50Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_20_10Gbps))
typedef enum
{
@@ -212,9 +238,18 @@ typedef enum
{
trainingPattern_Disabled = 0x0,
trainingPattern_1 = 0x1,
// trainingPattern_128B132B_TPS1 = 0x1, (use trainingPattern_1 enum as both are same)
trainingPattern_2 = 0x2,
trainingPattern_3 = 0x3,
trainingPattern_4 = 0xB
trainingPattern_4 = 0xB,
trainingPattern_128B132B_TPS2 = 0xD,
trainingPattern_PRBS_9 = 0xE,
trainingPattern_PRBS_11 = 0xF,
trainingPattern_PRBS_15 = 0x10,
trainingPattern_PRBS_23 = 0x11,
trainingPattern_PRBS_31 = 0x12,
trainingPattern_SqNum = 0x13,
trainingPattern_CSTM_264 = 0x14
} DP_TRAININGPATTERN;
typedef enum
@@ -228,8 +263,9 @@ typedef enum
{
dpColorFormat_RGB = 0,
dpColorFormat_YCbCr444 = 0x1,
dpColorFormat_YCbCr422 = 0x2,
dpColorFormat_YCbCr422 = 0x2, // this is for simple 422
dpColorFormat_YCbCr420 = 0x3,
dpColorFormat_YCbCr422_Native = 0x4,
dpColorFormat_Unknown = 0xF
} DP_COLORFORMAT;
@@ -509,10 +545,87 @@ typedef struct VesaPsrSinkCaps
} vesaPsrSinkCaps;
#pragma pack()
typedef struct
{
//
// If True, then DSC CRC of multiple SU regions supported irrespective
// of byte counts.
// If False, then DSC CRC of multiple SU regions supported only when
// the byte count is multiple of 6.
//
NvBool bDscCrcOfMultipleSuSupported;
//
// If True, then SU coordinates need to adhere granularity specified in
// 000B2h, 000B3h, 000B4h.
// If False, then SU coordinates does not need to adhere any granularity.
//
NvBool bSelUpdateGranularityNeeded;
//
// If True, then source will use Y granularity specified in 000B5h, 000B6h
// for PR.
// If False, sink does not support Y granularity extended cap.
// Value in 000B4h shall be used for PR.
//
NvBool bSuYGranularityExtendedCap;
//
// Applicable to PR SU operation. Sets the grid pattern granularity in X axis.
// If non zero, X coordinate shall be even divisible by 000B2h, 000B3h
// If zero, no X coordinate granularity requirement exists.
//
NvU8 selUpdateXGranularityCap; // This represents 00B2h register
NvU8 selUpdateXGranularityCap1; // This represents 00B3h register
//
// Applicable to PR SU operation. Sets the grid pattern granularity in Y axis.
// If value is 00h or 01h, No restrictions to SU region Y coordinate.
// If value is 02h or higher, Y coordinate shall be evenly by divisible by 000B4h
//
NvU8 selUpdateYGranularityCap;
//
// Applicable to PR SU operation. when image compression is performed locally
// in sink device, this sets additional granularity in Y axis.
//
NvU8 selUpdateYGranularityExtCap;
NvU8 selUpdateYGranularityExtCap1;
} SelectiveUpdateCaps;
typedef struct PanelReplayCaps
{
// Indicates if Panel replay is supported or not
NvBool bPanelReplaySupported;
// Indicates if selective updates is supported or not
NvBool bSelUpdateSupported;
// Indicates if Early region transport is supported or not
NvBool bEarlyRegionTpSupported;
// Tells whether sink supports DSC decode functionality in PR.
NvBool bDscDecodeNotSupportedInPr;
//
// If true, it indicates that sink device does not support Asynchronous
// Video Timing while in a PR Active state. Source device shall keep
// transmitting Adaptive-Sync SDPs during a PR Active state.
//
NvBool bAdaptiveSyncSdpNotSupportedInPr;
//
// Applicable to PR function operation using AUX-less ALPM when both
// an Adaptive-Sync SDP v2 (HB2[4:0] = 02h) and a selective update –or–
// full frame update occurred during a video frame.
// 0 = Main-Link shall remain turned ON following the Adaptive-Sync
// SDP transmission and until after the first selective update region –or–
// full frame update transmission is complete.
// 1 = Source device may optionally turn OFF the Main-Link after the
// Adaptive-Sync SDP transmission and then turn the Main-Link back ON
// in time for the selective update –or– full frame update.
//
NvBool bLinkOffSupportAfterAsSdpSent;
SelectiveUpdateCaps suCaps;
} panelReplayCaps;
typedef struct PanelReplayConfig
@@ -540,6 +653,62 @@ typedef struct PanelReplayConfig
// CRC mismatch.
//
NvBool bHpdOnRfbActiveFrameCrcError;
// Configure selective update feature on sink.
NvBool bEnableSelectiveUpdate;
// Configure Early region transport on sink.
NvBool bSuRegionEarlyTpEnable;
//
// Applicable only during a PR Active state with AUX-less ALPM enabled.
// Sink device ignores the setting when while receiving an Adaptive-Sync
// SDP with HB2[4:0] = 02h and DB0[2] = 0. After receiving an
// Adaptive-Sync SDP with HB2[4:0] = 02h and DB0[2] = 1, the bit value
// determines the Sink device’s refresh timing.
// 0 = Sink device shall use the coasting VTotal value in the last
// Adaptive-Sync SDP received.
// 1 = Sink device evice governs the display refresh rate and ignores the
// coasting VTotal value
//
NvBool bSinkRrUnlockGranted;
//
// Applicable only to PR SU operation.
// 0 = Source device shall use the Y granularity value declared by the
// PANEL REPLAY SELECTIVE UPDATE Y GRANULARITY
// CAPABILITY register (DPCD 000B4h).
// 1 = Source device shall use a supported value listed in the
// SU Y GRANULARITY EXTENDED CAPABILITY register
// (DPCD 000B5h and 000B6h). The selected value shall be indicated
// by way of DPCD 001B1h[6:3].
//
NvBool bSelUpdateYExtValEnable;
//
// Applicable only to the PR function.
// 0 = Sink device shall capture the SU region, starting with the active
// video image scan line immediately following the first BE control link
// symbol sequence after the VSC SDP.
// 1 = Sink device shall capture the SU region, starting with the active
// video image scan line immediately following the second BE control link
// symbol sequence after the VSC SDP.
//
NvBool bSuRegionScanLineIndicate;
//
// Applicable only to PR SU operation.
// Used by the Source device to indicate which supported Y granularity
// extended capability value shall be used. Only a value declared to be
// supported by DPCD 000B5h and 000B6h may be chosen. Enabled
// when DPCD 001B1h[2] = 1, and may be used only when the SU Y
// Granularity Extended Capability Supported bit in the PANEL REPLAY
// CAPABILITY register is set (DPCD 000B1h[6] = 1).
//
NvU8 selUpdateYExtVal : 4;
//Adaptive-Sync SDP Setup Time Configuration during PR_State.
NvU8 asSdpSetUpTimePrActive: 2;
} panelReplayConfig;
// PR state
@@ -571,6 +740,68 @@ typedef struct
PanelReplayState prState;
} PanelReplayStatus;
typedef struct
{
//
// 0 = PM_State 2a (FW_STANDBY) is not supported.
// 1 = PM_State 2a (FW_STANDBY) is supported.
//
NvBool bFwStandbySupported;
//
// If Sink device reports this as TRUE then it supports AUX-less ALPM.
// PM_State 3b (ALW_SLEEP) is supported by default.
//
NvBool bAuxLessAlpmSupported;
//
// Indicates whether the Sink device supports the
// AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED debug bit in the
// RECEIVER_ALPM_ARP_STATUS register (DPCD 0200Bh[3]).
//
NvBool bAuxLessAlpmPhySleepSupported;
} AlpmCaps;
typedef struct
{
// Source will use this to configure ALPM on sink side
NvBool bEnableAlpm;
//
// when this field is enabled Sink will trigger HPD to notify source
// the event of an AUX-less ALPM lock timeout error
//
NvBool bHpdOnAlpmLockError;
// This field needs to be set to True to enable Aux less ALPM
NvBool bSelectedAlpmMode;
//
// This is duration of ACDS phase.
// The Aux less exit sequence is composed of LFPS, followed by a
// PHY Establishment period and then the AUX-less ALPM Clock and
// Data Switch(ACDS) period.
//
NvBool bAcdsPeriodDuration;
} AlpmConfig;
typedef struct
{
//
// Set by the Sink device if it does not achieve LANEx_CR_DONE,
// LANEx_CHANNEL_EQ_DONE, LANEx_SYMBOL_LOCKED, and
// INTERLANE_ALIGN_DONE, within the specified time period, after
// receiving the wake sequence signal (LFPS and Silence)
//
NvBool bAuxlessAlpmLockTimeout;
//
// Used for debug purposes. Set by the Sink device when
// two consecutive ML_PHY_SLEEP sequences are detected.
//
NvBool bAuxlessAlpmPhySleepDetected;
} AlpmStatus;
// Multiplier constant to get link frequency in KHZ
// Maximum link rate of Main Link lanes = Value x 270M.
// To get it to KHz unit, we need to multiply 270K.
@@ -588,6 +819,7 @@ typedef struct
// a * 1000(KHz) / 10 * 1000 * 1000(10Mhz)
//
#define LINK_RATE_KHZ_TO_10MHZ(a) ((a) / 10000)
#define LINK_RATE_10MHZ_TO_KHZ(a) ((a) * 10000)
#define LINK_RATE_270MHZ_TO_10MHZ(a) ((a) * 27)
#define LINK_RATE_10MHZ_TO_270MHZ(a) ((a) / 27)
@@ -599,7 +831,10 @@ typedef struct
#define DP_LINK_BW_FREQ_MULTI_MBPS 27000000
// Convert link rate in 10M to its value in bps
#define DP_LINK_RATE_10M_TO_BPS(linkRate) (linkRate * 10000000)
#define DP_LINK_RATE_10M_TO_BPS(linkRate) (linkRate * 10000000)
// Convert link rate in 270M to its value in bps
#define DP_LINK_RATE_270M_TO_BPS(linkRate) (linkRate * 270000000)
// Convert link rate from bps to Bps
#define DP_LINK_RATE_BITSPS_TO_BYTESPS(linkRate) (linkRate / 8)

190
src/common/inc/displayport/displayport2x.h Normal file
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@@ -0,0 +1,190 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DISPLAYPORT2X_H_
#define _DISPLAYPORT2X_H_
#include "nvmisc.h"
#include "dpcd.h"
#include "dpcd14.h"
#include "dpcd20.h"
#include "displayport.h"
/**************** Resource Manager Defines and Structures ******************\
* *
* Module: DISPLAYPORT2x.H *
* Defines DISPLAYPORT V2.x *
* *
\***************************************************************************/
//
// 4 Legacy Link Rates: RBR, HBR, HBR2, HBR3
// 5 ILRs: 2.16G, 2.43G, 3.24G, 4.32G, 6.75G
// 3 UHBRs: 10G, 13.5G, 20G
// 2 Internal Test: 2.5G, 5G Do NOT use in any other use cases.
//
#define NV_SUPPORTED_DP2X_LINK_RATES__SIZE 14
//
// For 128b/132b link rate to data rate, linkRate * 128/132 * 1/8 * 10M -> ((linkRate * 4 * 1000000) / 33)
// For 128b/132b data rate to link rate, dataRate * 132/128 * 8 * 1/10M -> ((dataRate * 33) / (4 * 10000000))
// Data rates used here are in Bytes per second.
//
#define LINK_RATE_TO_DATA_RATE_128B_132B(linkRate) ((linkRate * 4 * 10000000UL) / 33)
#define DATA_RATE_128B_132B_TO_LINK_RATE(dataRate) (NV_UNSIGNED_DIV_CEIL((dataRate * 33ULL), (4 * 10000000ULL)))
// To calculate the effective link rate with channel encoding accounted
#define OVERHEAD_128B_132B(linkRate) ((linkRate * 128) / 132)
//
// 128b/132b precise Data Bandwidth Efficiency.
// Per Spec 3.5.2.18, effective BW with 128b/132b channel coding is linkRate * 0.9671.
// This covers Phy logial layer efficiency 52/1584 and link layer efficiency of 4/65540 as well.
// Also add SSC margin of 0.5%.
// Additionally add another 0.1% for source to be slightly more conservative for DSC environments
// and provide maximum compatibility for LTTPR CDS LT sequence.
//
// (1 - 52/1584) * (1 - 4/65540) * 0.994 = 0.9612
//
#define DATA_BW_EFF_128B_132B(linkRate) ((linkRate * 9612) / 10000)
// For channel equalization, max loop count is 20 when waiting CHANNEL_EQ_DONE set.
#define NV_DP2X_MAX_LOOP_COUNT_POLL_CHNL_EQ_DONE (20U)
typedef enum
{
linkBW_6_75Gbps = 0x19
} DP2X_LINK_BANDWIDTH_270M;
// The definition here is to match HW register defines for link speed.
typedef enum
{
dp2LinkSpeedId_1_62Gbps = 0x00,
dp2LinkSpeedId_2_70Gbps = 0x01,
dp2LinkSpeedId_5_40Gbps = 0x02,
dp2LinkSpeedId_8_10Gbps = 0x03,
dp2LinkSpeedId_2_16Gbps = 0x04,
dp2LinkSpeedId_2_43Gbps = 0x05,
dp2LinkSpeedId_3_24Gbps = 0x06,
dp2LinkSpeedId_4_32Gbps = 0x07,
dp2LinkSpeedId_6_75Gbps = 0x08,
dp2LinkSpeedId_10_0Gbps = 0x12,
dp2LinkSpeedId_13_5Gbps = 0x13,
dp2LinkSpeedId_20_0Gbps = 0x14,
dp2LinkSpeedId_UHBR_1_62Gbps = 0x1C,
dp2LinkSpeedId_UHBR_5_00Gbps = 0x1D,
dp2LinkSpeedId_UHBR_2_70Gbps = 0x1E,
dp2LinkSpeedId_UHBR_2_50Gbps = 0x1F,
dp2LinkSpeedId_Supported
} DP2X_LINK_SPEED_INDEX;
typedef enum
{
dp2xTxFFEPresetId_0 = 0,
dp2xTxFFEPresetId_1 = 1,
dp2xTxFFEPresetId_2 = 2,
dp2xTxFFEPresetId_3 = 3,
dp2xTxFFEPresetId_4 = 4,
dp2xTxFFEPresetId_5 = 5,
dp2xTxFFEPresetId_6 = 6,
dp2xTxFFEPresetId_7 = 7,
dp2xTxFFEPresetId_8 = 8,
dp2xTxFFEPresetId_9 = 9,
dp2xTxFFEPresetId_10 = 10,
dp2xTxFFEPresetId_11 = 11,
dp2xTxFFEPresetId_12 = 12,
dp2xTxFFEPresetId_13 = 13,
dp2xTxFFEPresetId_14 = 14,
dp2xTxFFEPresetId_15 = 15,
dp2xTxFFEPresetId_Supported
} DP2X_TXFFE_PRESET_INDEX;
// Link Training stages for 128b/132b channel coding.
typedef enum
{
DP2X_LT_Set_ResetLink = 0,
DP2X_LT_Poll_ResetLink = 1,
DP2X_LT_Set_PreLT = 2,
DP2X_LT_Set_ChnlEq = 3,
DP2X_LT_Poll_ChnlEq_Done = 4,
DP2X_LT_Poll_ChnlEq_InterlaneAlign = 5,
DP2X_LT_Set_CDS = 6,
DP2X_LT_Poll_CDS = 7,
DP2X_LT_Set_PostLT = 8,
DP2X_LT_StageSupported
} DP2X_LT_STAGES;
typedef enum
{
DP2X_ResetLinkForPreLT,
DP2X_ResetLinkForFallback,
DP2X_ResetLinkForChannelCoding
} DP2X_RESET_LINK_REASON;
//
// Multiplier constant to get link frequency (multiplier of 10MHz) in MBps with 128b/132b channel coding.
// a * 10 * 1000 * 1000(10Mhz) * (128 / 132)(128b/132b) / 8(Byte)
//
#define DP_LINK_BW_FREQ_MULTI_10M_TO_MBPS (10 * 1000 * 1000 * 128 / (132 * 8))
//
// Multiplier constant to get DP2X link frequency in KHZ
// Maximum link rate of Main Link lanes = Value x 10M.
// To get it to KHz unit, we need to multiply 10K.
//
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_10MHZ_TO_KHZ (10*1000)
//
// Multiplier constant to get link frequency (multiplier of 270MHz) in MBps
// a * 10 * 1000 * 1000(10Mhz) * (8 / 10)(8b/10b) / 8(Byte)
// = a * 1000000
//
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_10MHZ_TO_10HZ (1000*1000)
#define IS_STANDARD_DP2_X_LINKBW(val) (((NvU32)(val)==dp2LinkRate_1_62Gbps) || \
((NvU32)(val)==dp2LinkRate_2_70Gbps) || \
((NvU32)(val)==dp2LinkRate_5_40Gbps) || \
((NvU32)(val)==dp2LinkRate_8_10Gbps))
#define IS_INTERMEDIATE_DP2_X_LINKBW(val) (((NvU32)(val)==dp2LinkRate_2_16Gbps) || \
((NvU32)(val)==dp2LinkRate_2_43Gbps) || \
((NvU32)(val)==dp2LinkRate_3_24Gbps) || \
((NvU32)(val)==dp2LinkRate_4_32Gbps) || \
((NvU32)(val)==dp2LinkRate_6_75Gbps))
#define IS_DP2_X_UHBR_LINKBW(val) (((NvU32)(val)==dp2LinkRate_2_50Gbps) || \
((NvU32)(val)==dp2LinkRate_5_00Gbps) || \
((NvU32)(val)==dp2LinkRate_10_0Gbps) || \
((NvU32)(val)==dp2LinkRate_13_5Gbps) || \
((NvU32)(val)==dp2LinkRate_20_0Gbps))
#define IS_VALID_DP2_X_LINKBW(val) (IS_STANDARD_DP2_X_LINKBW(val) || \
IS_INTERMEDIATE_DP2_X_LINKBW(val) || \
IS_DP2_X_UHBR_LINKBW(val))
#define IS_LEGACY_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
((NvU32)(val)==linkBW_2_43Gbps) || \
((NvU32)(val)==linkBW_3_24Gbps) || \
((NvU32)(val)==linkBW_4_32Gbps) || \
((NvU32)(val)==linkBW_6_75Gbps))
#endif // #ifndef _DISPLAYPORT2X_H_

27
src/common/inc/displayport/dpcd.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -447,6 +447,9 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LESS_THAN_0_5 (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE 6:6 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_NO (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_YES (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED 7:7 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_FALSE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */
@@ -915,16 +918,20 @@ number of Downstream ports will be limited to 32.
// 00283h - 002BFh: RESERVED. Read all 0s.
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS (0x000002C0) /* R-XUR */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED 0:0 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS (0x000002C0) /* R-XUR */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED 0:0 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_VC_PAYLOAD_ID_SLOT0_5_0 7:2 /* R-XUF */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT(i) (0x000002C1+(i)) /* R--1A */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT__SIZE 63 /* R---S */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT1 (0x000002C1) /* R-XUR */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT1_VC_PAYLOAD_ID_SLOT0_6 7:7 /* R-XUF */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT(i) (0x000002C1+(i)) /* R--1A */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT__SIZE 63 /* R---S */
// Source Device-Specific Field, Burst write for 00300h-0030Bh
// 6 hex digits: 0x300~0x302.

372
src/common/inc/displayport/dpcd20.h
View File

@@ -48,6 +48,12 @@
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0 /* R-XUF */
@@ -68,6 +74,12 @@
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR 5:5 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE 6:6 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT 7:7 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS (0x00002020) /* R-XUR */
@@ -110,6 +122,321 @@
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LINK_BANDWIDTH_SET (0x00000100) /* RWXUR */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL 7:0 /* RWXUF */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_10_0 (0x00000001) /* RWXUV */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_20_0 (0x00000002) /* RWXUV */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_13_5 (0x00000004) /* RWXUV */
// UHBR-128B/132B specific
#define NV_DPCD20_128B_132B_TRAINING_PATTERN (0x00000102) /* RWXUR */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT 3:0 /* RWXUF */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_NONE (0x00000000) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS1 (0x00000001) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2 (0x00000002) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2_CDS (0x00000003) /* RWXUV */
// Bit 7:4 are reserved for 128b/132b. Driver should keep them 0
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_RESERVED 7:4 /* RWXUF */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_RESERVED_ZERO (0x00000000) /* RWXUV */
#define NV_DPCD20_TRAINING_LANE_SET(i) (0x00000103+(i)) /* RW-1A */
#define NV_DPCD20_TRAINING_LANE_SET__SIZE 4 /* RW--S */
#define NV_DPCD20_TRAINING_LANE_SET_TX_FFE_PRESET_VALUE 3:0 /* RWXUF */
#define NV_DPCD20_TRAINING_LANE0_SET (0x00000103) /* RWXUR */
#define NV_DPCD20_LINK_QUAL_LANE_SET(i) (0x0000010B+(i)) /* RW-1A */
#define NV_DPCD20_LINK_QUAL_LANE_SET__SIZE 4 /* RW--S */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS 6:0 /* RWXUF */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_128B132B_TPS1 (0x00000008) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_128B132B_TPS2 (0x00000010) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS9 (0x00000018) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS11 (0x00000020) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS15 (0x00000028) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS23 (0x00000030) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS31 (0x00000038) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_264_BIT_CUSTOM (0x00000040) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON (0x00000048) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON (0x00000049) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF (0x0000004A) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF (0x0000004B) /* R-XUV */
#define NV_DPCD20_LINK_SQUARE_PATTERN_NUM_PLUS_1 (0x0000010F) /* RWXUR */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF (0x00000121) /* RWXUR */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED 0:0 /* RWXUF */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUV */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED (0x00000204) /* R-XUR */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED 4:4 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_SINK_STATUS (0x00000205) /* R-XUR */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_TEST_REQUEST (0x00000218) /* R-XUR */
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING 4:4 /* R-XUF */
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_8B10B (0x00000000) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_128B132B (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ 5:5 /* R-XUF */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO 6:6 /* R-XUF */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_LINK_RATE (0x00000219) /* R-XUR */
#define NV_DPCD20_TEST_LINK_RATE_TYPE 7:0 /* R-XUF */
#define NV_DPCD20_TEST_LINK_RATE_TYPE_10_0G (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_LINK_RATE_TYPE_20_0G (0x00000002) /* R-XUV */
#define NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G (0x00000004) /* R-XUV */
// Bug 4953977: Unigraf UCD323 uses the wrong value to request test link training.
// WAR to add off-spec value
#define NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G_2 (0x00000003) /* R-XUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_PHY_TEST_PATTERN (0x00000248) /* R-XUR */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_DP20 6:0 /* R-XUF */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS1 (0x00000008) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS2 (0x00000010) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS9 (0x00000018) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS11 (0x00000020) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS15 (0x00000028) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS23 (0x00000030) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS31 (0x00000038) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_264_BIT_CUSTOM (0x00000040) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON (0x00000048) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON (0x00000049) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF (0x0000004A) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF (0x0000004B) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_LTTPR_CLOCK_SWITCH 7:7 /* R-XUF */
#define NV_DPCD20_PHY_SQUARE_PATTERN_NUM_PLUS_1 (0x00000249) /* R-XUR */
// 0x2230 - 0x2250 = 33 bytes
#define NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN(i) (0x00002230+(i)) /* R--1A */
#define NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN__SIZE 33 /* R---S */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX (0x00002251) /* R-XUR */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP 0:0 /* R-XUF */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP_NOT_SUPPORTED (0x00000000) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL (0x00002252) /* R-XUR */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE 0:0 /* R-XUF */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION 2:1 /* R-XUF */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_15 (0x00000000) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_30 (0x00000001) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_60 (0x00000002) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_120 (0x00000003) /* R-XUV */
// Field definition for 0x0206/0x0207h (ADJUST_REQUEST_LANEX), only used only with 128b/132b for DP2.0+
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEX_TX_FFE_PRESET_VALUE 3:0 /* R-XUF */
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_TX_FFE_PRESET_VALUE 7:4 /* R-XUF */
// Field definition for 0x0200E (LANE_ALIGN_STATUS_UPDATED_ESI), used only when DP2.0+ 128b/132b is enabled.
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED 4:4 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
// Field definition for 0x0200F (SINK_STATUS_ESI), used only when DP2.0+ 128b/132b is enabled.
#define NV_DPCD20_SINK_STATUS_ESI (0x0000200F) /* R-XUR */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING (0x00002206) /* R-XUR */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B 0:0 /* R-XUF */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B 1:1 /* R-XUF */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES (0x00002215) /* R-XUR */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10 0:0 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20 1:1 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5 2:2 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_YES (0x00000001) /* R-XUV */
//
// The interval is (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) * INTERVAL_UNIT.
// The maximum is 256 ms.
//
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL (0x00002216) /* R-XUR */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT 7:7 /* R-XUF */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_MAX_MS 256
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING (0x000F0006) /* RWXUR */
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUF */
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES (0x000F0007) /* R-XUR */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED 1:1 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1 1:1 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2 2:2 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3 3:3 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4 4:4 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5 5:5 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6 6:6 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7 7:7 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS (0x000F0009) /* R-XUR */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS_NOT_SUPPORTED (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_TOTAL_LTTPR_CNT (0x000F000A) /* RWXUR */
#define NV_DPCD20_PHY_REPEATER_TOTAL_LTTPR_CNT_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD (0x000000B1) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR 3:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED 4:4 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED 5:5 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED 6:6 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP 7:7 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY (0x000000B2) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY1 (0x000000B3) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY1_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_CAPABILITY (0x000000B4) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_CAPABILITY_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY (0x000000B5) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY1 (0x000000B6) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY1_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2 (0x000001B1) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_SELECTION 6:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION 7:7 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION3 (0x0000011A) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION3_AS_SDP_SETUP_CONFIG_PR_ACTIVE_TIME 7:6 /* R-XUF */
//
// Adding DPCD registers for EDP ALPM.
//
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES (0x0000002E) /* R-XUR */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT 1:1 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP 2:2 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT 3:3 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION (0x00000116) /* R-XUR */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM 0:0 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR 1:1 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE 2:2 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE_AUX_WAKE_ALPM (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE_AUX_LESS_ALPM (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION 3:3 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS (0x0000200B) /* R-XUR */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR 0:0 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR 2:2 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED 3:3 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED_YES (0x00000001) /* R-XUV */
//
// Adding DPCD registers for DP Tunneling feature.
@@ -179,6 +506,22 @@
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_TWO (0x00000002) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_FOUR (0x00000004) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_MAIN_LINK_CHANNEL_CODING (0x000E002B) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES (0x000E002C) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED 1:1 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DPTX_BW_ALLOCATION_MODE_CONTROL (0x000E0030) /* R-XUR */
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ 6:6 /* R-XUF */
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ_NO (0x00000000) /* R-XUV */
@@ -187,4 +530,33 @@
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_YES (0x00000001) /* R-XUV */
// DPCD Registers for Cable ID
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX (0x00000110) /* R-XUR */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY 1:0 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_UHBR_NOT_CAPABLE (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_10_0_GBPS_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_10_AND_20_GBPS_SUPPORTED (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE 5:3 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_CABLE_TYPE_UNKNOWN (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_PASSIVE (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_LRD (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_ACTIVE_RETIMER (0x00000003) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX (0x00002217) /* R-XUR */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY 1:0 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_UHBR_NOT_CAPABLE (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_10_0_GBPS_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_10_AND_20_GBPS_SUPPORTED (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE 5:3 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_CABLE_TYPE_UNKNOWN (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_PASSIVE (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_LRD (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_ACTIVE_RETIMER (0x00000003) /* R-XUV */
#endif // #ifndef _DISPLAYPORT20_H_

22
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r565_00
#define NV_BUILD_BRANCH r571_57
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r565_00
#define NV_PUBLIC_BRANCH r571_57
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r565/r565_00-213"
#define NV_BUILD_CHANGELIST_NUM (35186646)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r571_57-275"
#define NV_BUILD_CHANGELIST_NUM (35438409)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r565/r565_00-213"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35186646)
#define NV_BUILD_NAME "rel/gpu_drv/r570/r571_57-275"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35438409)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r565_00-169"
#define NV_BUILD_CHANGELIST_NUM (35186646)
#define NV_BUILD_BRANCH_VERSION "r571_57-35"
#define NV_BUILD_CHANGELIST_NUM (35438409)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "566.31"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35186646)
#define NV_BUILD_BRANCH_BASE_VERSION R565
#define NV_BUILD_NAME "572.13"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35438409)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

3
src/common/inc/nvCpuIntrinsics.h
View File

@@ -285,8 +285,7 @@ static NV_FORCEINLINE int __NVatomicDecrement_LSE(int volatile *location)
//
// for (__NVbsfFirst(&index, &mask, maskInit); mask; __NVbsfNext(&index, &mask)) { ... }
//
// These operations are implemented using gcc/MSVC builtins/intrinsics. A test program to verify the correct
// functionality of these routines is available at //sw/pvt/ddadap/bitscantest.c
// These operations are implemented using gcc/MSVC builtins/intrinsics.
//
// The scan process provides the next valid "index". In __NVbsfNext() the bit corresponding to the passed in
// (1 << index) will be masked out.

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "565.77"
#define NV_VERSION_STRING "570.86.15"
#else

2
src/common/inc/nvVer.h
View File

@@ -3,7 +3,7 @@
#define NV_COMPANY_NAME_STRING_SHORT "NVIDIA"
#define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation"
#define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL
#define NV_COPYRIGHT_YEAR "2024"
#define NV_COPYRIGHT_YEAR "2025"
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \

5
src/common/inc/nvlog_defs.h
View File

@@ -102,9 +102,10 @@ struct _NVLOG_BUFFER
#define NVLOG_MAX_BUFFERS_v11 16
#define NVLOG_MAX_BUFFERS_v12 256
#define NVLOG_MAX_BUFFERS_v13 3840
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v12
#define NVLOG_LOGGER_VERSION 12 // v1.2
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v13
#define NVLOG_LOGGER_VERSION 13 // v1.3
// Due to this file's peculiar location, NvPort may or may not be includable
typedef struct PORT_SPINLOCK PORT_SPINLOCK;

71
src/common/inc/swref/published/ampere/ga100/dev_nv_pcfg_xve_regmap.h Normal file
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@@ -0,0 +1,71 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __dev_nv_pcfg_xve_regmap_h__
#define __dev_nv_pcfg_xve_regmap_h__
#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000
/*
* <prefix>_MAP has 1 bit set for each dword register.
* <prefix>_COUNT has total number of set bits in <prefix>_MAP.
*/
#define NV_PCFG_XVE_REGISTER_VALID_COUNT 445
#define NV_PCFG_XVE_REGISTER_VALID_MAP { \
/* 0x00088000 */ 0xFFF1FFFF, 0x139FFF9F, \
/* 0x00088100 */ 0x1FBA3C7F, 0x00000000, \
/* 0x00088200 */ 0x03F00000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA1F, 0x00000000, \
/* 0x00088700 */ 0x0001FFFF, 0x00000000, \
/* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \
/* 0x00088900 */ 0xFFFFFFFF, 0x000FFFFF, \
/* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \
/* 0x00088B00 */ 0x00000000, 0xFFFFF000, \
/* 0x00088C00 */ 0x0007BFE7, 0xFFFFFFFC, \
/* 0x00088D00 */ 0xFFFFFFFF, 0x7FFF3FFF, \
/* 0x00088E00 */ 0x000007FF, 0x00000000, \
/* 0x00088F00 */ 0x00000000, 0xFC000000 }
#define NV_PCFG_XVE_REGISTER_WR_COUNT 321
#define NV_PCFG_XVE_REGISTER_WR_MAP { \
/* 0x00088000 */ 0x3EF193FA, 0x1187C505, \
/* 0x00088100 */ 0x1FBA0828, 0x00000000, \
/* 0x00088200 */ 0x03200000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x80007EC0, 0x3F075007, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA10, 0x00000000, \
/* 0x00088700 */ 0x0001FFFF, 0x00000000, \
/* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \
/* 0x00088900 */ 0xFFFC7804, 0x000FFFFF, \
/* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \
/* 0x00088B00 */ 0x00000000, 0xF8A54000, \
/* 0x00088C00 */ 0x00003C01, 0x3FFFFFFC, \
/* 0x00088D00 */ 0xFFFFFFFC, 0x739B2C3F, \
/* 0x00088E00 */ 0x000007F8, 0x00000000, \
/* 0x00088F00 */ 0x00000000, 0xFC000000 }
#endif // {__dev_nv_pcfg_xve_regmap_h__}

1
src/common/inc/swref/published/blackwell/gb100/dev_pcfg_pf0.h
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@@ -257,5 +257,6 @@
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_PRI_ERROR_2ND 29:29 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_DEVICE_LOCKDOWN 30:30 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUNCTION_LOCKDOWN 31:31 /* R-IVF */
#define NV_PF0_PF_RESIZABLE_BAR_CAPABILITY 0x0000019c /* R--4R */
#endif // __gb100_dev_pcfg_pf0_h__

49
src/common/inc/swref/published/blackwell/gb100/dev_riscv_pri.h
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@@ -1,49 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_riscv_pri_h__
#define __gb100_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM 2:2 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM 3:3 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE 5:5 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE 6:6 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM 12:12 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_NO_FAULT 0x00000000 /* R-I-V */
#endif // __gb100_dev_riscv_pri_h__

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src/common/inc/swref/published/blackwell/gb10b/dev_boot.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_boot_h__
#define __gb10b_dev_boot_h__
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#endif // __gb10b_dev_boot_h__

29
src/common/inc/swref/published/blackwell/gb10b/dev_ce.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_ce_h__
#define __gb10b_dev_ce_h__
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 2 /* */
#endif // __gb10b_dev_ce_h__

64
src/common/inc/swref/published/blackwell/gb10b/dev_fault.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_fault_h__
#define __gb10b_dev_fault_h__
#define NV_PFAULT_CLIENT_HUB_PD1 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC1 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC2 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC3 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_SCC1 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB1 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_SCC2 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB2 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_SCC3 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB3 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD1 0x00000046 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD2 0x00000047 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD3 0x00000048 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE1 0x00000049 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE2 0x0000004A /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE3 0x0000004B /* */
#define NV_PFAULT_CLIENT_HUB_PD2 0x0000004C /* */
#define NV_PFAULT_CLIENT_HUB_PD3 0x0000004D /* */
#define NV_PFAULT_CLIENT_HUB_ESC0 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC1 0x00000064 /* */
#define NV_PFAULT_CLIENT_HUB_ESC2 0x00000065 /* */
#define NV_PFAULT_CLIENT_HUB_ESC3 0x00000066 /* */
#define NV_PFAULT_CLIENT_HUB_ESC4 0x00000067 /* */
#define NV_PFAULT_CLIENT_HUB_ESC5 0x00000068 /* */
#define NV_PFAULT_CLIENT_HUB_ESC6 0x00000069 /* */
#define NV_PFAULT_CLIENT_HUB_ESC7 0x0000006a /* */
#define NV_PFAULT_CLIENT_HUB_ESC8 0x0000006b /* */
#define NV_PFAULT_CLIENT_HUB_ESC9 0x0000006c /* */
#define NV_PFAULT_CLIENT_HUB_ESC10 0x0000006d /* */
#define NV_PFAULT_CLIENT_HUB_ESC11 0x0000006e /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE0 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER2 0x0000007C /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER3 0x0000007D /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER4 0x0000007E /* */
#define NV_PFAULT_CLIENT_HUB_NVENC3 0x0000007F /* */
#endif // __gb10b_dev_fault_h__

37
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_fb_h__
#define __gb10b_dev_fb_h__
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO 0x008a1d58 /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xffffff00 /* RW--V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI 0x008a1d5c /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000fffff /* RW--V */
#endif // __gb10b_dev_fb_h__

30
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_perf_h__
#define __gb10b_dev_perf_h__
#define NV_PERF_PMASYS_CBLOCK_BPC_CONFIG_SECURE__SIZE_1 3 /* */
#define NV_PERF_PMASYS_CHANNEL_OUTBASE__SIZE_2 2 /* */
#endif // __gb10b_dev_perf_h__

30
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_ram_h__
#define __gb10b_dev_ram_h__
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (19+1*32):(0+1*32) /* RWXUF */
#endif // __gb10b_dev_ram_h__

130
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_xtl_ep_pcfg_gpu_h__
#define __gb10b_dev_xtl_ep_pcfg_gpu_h__
/* This file is autogenerated. Do not edit */
#define NV_EP_PCFG_GPU 0xFFF:0x000 /* RW--D */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2 0x00000084 /* R--4R */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES 3:0 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B 0x00000003 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B_AND_C 0x00000006 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B_AND_C 0x00000007 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B_AND_C_AND_D 0x0000000E /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B_AND_C_AND_D 0x0000000F /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_NOT_SUPP 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE 4:4 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING 5:5 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING 6:6 /* R-CVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_NOT_SUPPORTED 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM 11:11 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER 13:12 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS 15:14 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER 16:16 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED 0x00000001 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER 17:17 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED 0x00000001 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF 19:18 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_MSG_SGNL 0x00000001 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_WAKE_SGNL 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_MSG_WAKE_SGNL 0x00000003 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT 20:20 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX 21:21 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX 23:22 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_4 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_1 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_2 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_3 0x00000003 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION 25:24 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED_DSM 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED_DSM_FF 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_RESERVED 0x00000003 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ 26:26 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS 31:31 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC 0x000002B4 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC__SAFETY "parity" /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR 15:0 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_OVERRIDEABLE 0 /* */
#endif // __gb10b_dev_xtl_ep_pcfg_gpu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_hwproject_h__
#define __gb10b_hwproject_h__
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 41
#endif // __gb10b_hwproject_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_pri_nv_xal_ep_h__
#define __gb10b_pri_nv_xal_ep_h__
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#define NV_XAL_EP_BAR0_WINDOW_BASE 24:0 /* RWIUF */
#define NV_XAL_EP_BAR0_WINDOW_BASE_0 0x0000000 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x0000010 /* */
#endif // __gb10b_pri_nv_xal_ep_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_boot_h__
#define __gb202_dev_boot_h__
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_SEQUENCE_TOO_BIG 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRE_IFF_CRC_CHECK_FAILED 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_POST_IFF_CRC_CHECK_FAILED 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_ECC_UNCORRECTABLE_ERROR 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_CMD_FORMAT_ERROR 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRI_ERROR 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_SCPM 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_DCLS 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_EMP 12:12 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_UNCORRECTABLE_ERROR 13:13 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_L5_WDT 14:14 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 15:15 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 16:16 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 17:17 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 18:18 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 19:19 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 20:20 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 21:21 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_XTAL_CTFDC 22:22 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_XTAL_FMON 23:23 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_GPC_FMON 24:24 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 30:30 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 31:31 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_INTERRUPT 32:32 /* R-XUF */
#endif // __gb202_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_ce_h__
#define __gb202_dev_ce_h__
#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */
#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */
#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
#endif // __gb202_dev_ce_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_ce_base_h__
#define __gb202_dev_ce_base_h__
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 4
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 4
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gb202_dev_ce_base_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_fault_h__
#define __gb202_dev_fault_h__
#define NV_PFAULT /* ----G */
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 55 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 6 /* */
#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF1 11 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF2 12 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF3 13 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF4 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF5 15 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF6 16 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF7 17 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF8 18 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF9 19 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE 20 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE1 21 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE2 22 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE3 23 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE4 24 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE5 25 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE6 26 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE7 27 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 30 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 31 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 32 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC5 33 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC6 34 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC7 35 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 36 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG1 37 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG2 38 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG3 39 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG4 40 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG5 41 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG6 42 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG7 43 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 65 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 65 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 66 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 67 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 68 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 69 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 70 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 71 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 72 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 73 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 74 /* */
#define NV_PFAULT_MMU_ENG_ID_CE10 75 /* */
#define NV_PFAULT_MMU_ENG_ID_CE11 76 /* */
#define NV_PFAULT_MMU_ENG_ID_CE12 77 /* */
#define NV_PFAULT_MMU_ENG_ID_CE13 78 /* */
#define NV_PFAULT_MMU_ENG_ID_CE14 79 /* */
#define NV_PFAULT_MMU_ENG_ID_CE15 80 /* */
#define NV_PFAULT_MMU_ENG_ID_CE16 81 /* */
#define NV_PFAULT_MMU_ENG_ID_CE17 82 /* */
#define NV_PFAULT_MMU_ENG_ID_CE18 83 /* */
#define NV_PFAULT_MMU_ENG_ID_CE19 84 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 44 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 45 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 46 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC3 47 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 48 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST0 85 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST1 86 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST2 87 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST3 88 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST4 89 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST5 90 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST6 91 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST7 92 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST8 93 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST9 94 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST10 95 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST11 96 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST12 97 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST13 98 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST14 99 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST15 100 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST16 101 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST17 102 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST18 103 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST19 104 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST20 105 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST21 106 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST22 107 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST23 108 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST24 109 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST25 110 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST26 111 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST27 112 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST28 113 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST29 114 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST30 115 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST31 116 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST32 117 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST33 118 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST34 119 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST35 120 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST36 121 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST37 122 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST38 123 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST39 124 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST40 125 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST41 126 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST42 127 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST43 128 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST44 129 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 257 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 258 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 259 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 260 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 261 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 262 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 263 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 264 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 265 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 266 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 267 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 268 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 269 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 270 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 271 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 272 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 273 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 274 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 275 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 276 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 277 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 278 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 279 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 280 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 281 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 282 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 283 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 284 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 285 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 286 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 287 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 288 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 289 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 290 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 291 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 292 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 293 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 294 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 295 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 296 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 297 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 298 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 299 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 300 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 301 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 302 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 303 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 304 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 305 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 306 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 307 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 308 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 309 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 310 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 311 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 312 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 313 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 314 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 315 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 316 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 317 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 318 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 319 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 320 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 321 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 322 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 323 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 324 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 325 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 326 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 327 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 328 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 329 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 330 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 331 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 332 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 333 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 334 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 335 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 336 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 337 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 338 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 339 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 340 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 341 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 342 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 343 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 344 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 345 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 346 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 347 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 348 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 349 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 350 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 351 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 352 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 353 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 354 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 355 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 356 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 357 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 358 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 359 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 360 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 361 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 362 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 363 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 364 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 365 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 366 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 367 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 368 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 369 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 370 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 371 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 372 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 373 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 374 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 375 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 376 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 377 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 378 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 379 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 380 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 381 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 382 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 383 /* */
#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */
#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */
#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */
#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */
#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */
#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */
#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */
#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */
#define NV_PFAULT_FAULT_TYPE_CC_VIOLATION 0x0000000b /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */
#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */
#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */
#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */
#define NV_PFAULT_CLIENT_HUB_PD1 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC1 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC2 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC3 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_SCC1 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB1 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_SCC2 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB2 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_SCC3 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB3 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD1 0x00000046 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD2 0x00000047 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD3 0x00000048 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE1 0x00000049 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE2 0x0000004A /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE3 0x0000004B /* */
#define NV_PFAULT_CLIENT_HUB_PD2 0x0000004C /* */
#define NV_PFAULT_CLIENT_HUB_PD3 0x0000004D /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_2 0x00000072 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_3 0x00000073 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC0 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC1 0x00000064 /* */
#define NV_PFAULT_CLIENT_HUB_ESC2 0x00000065 /* */
#define NV_PFAULT_CLIENT_HUB_ESC3 0x00000066 /* */
#define NV_PFAULT_CLIENT_HUB_ESC4 0x00000067 /* */
#define NV_PFAULT_CLIENT_HUB_ESC5 0x00000068 /* */
#define NV_PFAULT_CLIENT_HUB_ESC6 0x00000069 /* */
#define NV_PFAULT_CLIENT_HUB_ESC7 0x0000006a /* */
#define NV_PFAULT_CLIENT_HUB_ESC8 0x0000006b /* */
#define NV_PFAULT_CLIENT_HUB_ESC9 0x0000006c /* */
#define NV_PFAULT_CLIENT_HUB_ESC10 0x0000006d /* */
#define NV_PFAULT_CLIENT_HUB_ESC11 0x0000006e /* */
#define NV_PFAULT_CLIENT_HUB_FSP 0x00000079 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE0 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER2 0x0000007C /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER3 0x0000007D /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER4 0x0000007E /* */
#define NV_PFAULT_CLIENT_HUB_NVENC3 0x0000007F /* */
#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */
#endif // __gb202_dev_fault_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_fsp_addendum_h__
#define __gb202_dev_fsp_addendum_h__
#define NV_GFW_FSP_UCODE_VERSION NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(1)
#define NV_GFW_FSP_UCODE_VERSION_FULL 11:0
#define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8
#define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0
#endif // __gb202_dev_fsp_addendum_h__

38
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_fsp_pri_h__
#define __gb202_dev_fsp_pri_h__
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x008f0320+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gb202_dev_fsp_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_mmu_h__
#define __gb202_dev_mmu_h__
#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */
#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */
#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */
#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */
#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */
#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */
#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */
#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#endif // __gb202_dev_mmu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_ram_h__
#define __gb202_dev_ram_h__
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
#define NV_RAMRL_ENTRY_CHAN_RUNQUEUE_SELECTOR_RUNQUEUE1 0x00000001 /* */
#define NV_RAMRL_ENTRY_BASE_SHIFT 8 /* */
#endif // __gb202_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_runlist_h__
#define __gb202_dev_runlist_h__
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */
#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */
#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */
#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */
#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */
#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */
#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */
#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */
#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
#define NV_RUNLIST_PREEMPT 0x014 /* RW-4R */
#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */
#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */
#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */
#endif // __gb202_dev_runlist_h__

32
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_therm_h__
#define __gb202_dev_therm_h__
#define NV_THERM_I2CS_SCRATCH 0x00ad00bc /* RW-4R */
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
#endif // __gb202_dev_therm_h__

33
src/common/inc/swref/published/blackwell/gb202/dev_therm_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_therm_addendum_h__
#define __gb202_dev_therm_addendum_h__
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
#endif // __gb202_dev_therm_addendum_h__

35
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_vm_h__
#define __gb202_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_DOORBELL_VECTOR 11:0 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_ID 22:16 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL 30:30 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL_DISABLE 0x0 /* -W--V */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL_ENABLE 0x1 /* -W--V */
#endif // __gb202_dev_vm_h__

54
src/common/inc/swref/published/blackwell/gb202/dev_xtl_ep_pcfg_gpu.h Normal file
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@@ -0,0 +1,54 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_xtl_ep_pcfg_gpu_h__
#define __gb202_dev_xtl_ep_pcfg_gpu_h__
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_1 0x000002B4 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2 0x000002B8 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_IFF_POS 31:25 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_IFF_POS_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_IFF_POS_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_BAR_FIREWALL_ENGAGE 24:24 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_BAR_FIREWALL_ENGAGE_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_BAR_FIREWALL_ENGAGE_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2 0x00000084 /* R--4R */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 0x00000088 /* RW-4R */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* RWIVF */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_DEFAULT 0x00000000 /* RWI-V */
#endif // __gb202_dev_xtl_ep_pcfg_gpu_h__

36
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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GB202_KIND_MACROS_H_INCLUDED
#define GB202_KIND_MACROS_H_INCLUDED
#define KIND_INVALID(k) ( ((k) ==NV_MMU_CLIENT_KIND_INVALID))
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_COMPRESSIBLE(k) ( ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_DISALLOWS_PLC(k) ( !((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_S8Z24)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define KIND_Z(k) ( ((k) >=NV_MMU_CLIENT_KIND_Z16 && (k) <= NV_MMU_CLIENT_KIND_Z24S8))
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))
#endif // GB202_KIND_MACROS_H_INCLUDED

30
src/common/inc/swref/published/blackwell/gb202/pri_nv_xal_ep.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_pri_nv_xal_ep_h__
#define __gb202_pri_nv_xal_ep_h__
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#endif // __gb202_pri_nv_xal_ep_h__

23
src/common/inc/swref/published/disp/v03_00/dev_disp.h
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@@ -114,11 +114,34 @@
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_RESET 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_RESET 0x00000001 /* -W--V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN 0x00611858 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH(i) (0+(i)):(0+(i)) /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH__SIZE_1 32 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_INIT 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_NOT_PENDING 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_PENDING 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_RESET 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER 0x0061185C /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE 0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_INIT 0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_RESET 0x00000001 /* -W--V */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(i) (0x0061611C+(i)*2048) /* RW-4A */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE 31:0 /* RWIUF */

46
src/common/inc/swref/published/disp/v04_01/dev_disp.h Normal file
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@@ -0,0 +1,46 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v04_01_dev_disp_h__
#define __v04_01_dev_disp_h__
#define NV_PDISP 0x006F1FFF:0x00610000 /* RW--D */
#define NV_PDISP_FE_EVT_DISPATCH 0x00611A00 /* R--4R */
#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN 26:26 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN 0x00611868 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH(i) (0+(i)):(0+(i)) /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH__SIZE_1 32 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_INIT 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_NOT_PENDING 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_PENDING 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_RESET 0x00000001 /* */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM 9:9 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_PENDING 0x00000001 /* R---V */
#endif // __v04_01_dev_disp_h__

40
src/common/inc/swref/published/disp/v05_01/dev_disp.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,6 +23,7 @@
#ifndef __v05_01_dev_disp_h__
#define __v05_01_dev_disp_h__
#define NV_PDISP_POSTCOMP_LOADV_COUNTER(i) (0x0061A11C+(i)*1024) /* RW-4A */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE 31:0 /* RWIUF */
@@ -30,4 +31,41 @@
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING(i) (0x00611EF0+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_INTR_RETRIGGER(i) (0x00611F30+(i)*4) /* RW-4A */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER 0:0 /* RWIVF */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER_NONE 0x00000000 /* RWI-V */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER_TURE 0x00000001 /* -W--T */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP(i) (0x006405E8+(i)*4) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP__SIZE_1 8 /* */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MAX 7:0 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MAX__PRODCHK 0 /* */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MAX_INIT 0x00000077 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MIN 15:8 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MIN__PRODCHK 0 /* */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MIN_INIT 0x00000019 /* RWI-V */
#define NV_PDISP_RG_IN_LOADV_COUNTER(i) (0x00616320+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_IN_LOADV_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE 31:0 /* RWIUF */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE__PRODCHK 0 /* */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PDISP_RG_CRASHLOCK_COUNTER(i) (0x00616484+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_CRASHLOCK_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V 31:16 /* RWIUF */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V__PRODCHK 0 /* */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V_ZERO 0x00000000 /* RW--V */
#endif // __v05_01_dev_disp_h__

2
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h
View File

@@ -117,4 +117,6 @@
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM 15:15 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_L1_PM_SS_CONTROL_1_REGISTER 0x00000298 /* RW-4R */
#define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CAP 0x00000138 /* R--4R */
#endif // __gh100_dev_xtl_ep_pcfg_gpu_h__

6
src/common/inc/swref/published/hopper/gh100/hwproject.h
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@@ -20,7 +20,13 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GH100_HWPROJECT_H_INCLUDED
#define GH100_HWPROJECT_H_INCLUDED
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52
#define NV_XPL_BASE_ADDRESS 540672
#define NV_XTL_BASE_ADDRESS 593920
#define NV_FBPA_PRI_STRIDE 16384
#endif // GH100_HWPROJECT_H_INCLUDED

19
src/common/inc/swref/published/nv_arch.h
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@@ -48,7 +48,9 @@
#define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170)
#define GPU_ARCHITECTURE_HOPPER GPU_ARCHITECTURE(_CLASSIC, 0x0180)
#define GPU_ARCHITECTURE_ADA GPU_ARCHITECTURE(_CLASSIC, 0x0190)
#define GPU_ARCHITECTURE_BLACKWELL GPU_ARCHITECTURE(_CLASSIC, 0x01A0)
#define GPU_ARCHITECTURE_BLACKWELL_GB1XX GPU_ARCHITECTURE(_CLASSIC, 0x01A0)
#define GPU_ARCHITECTURE_BLACKWELL_GB2XX GPU_ARCHITECTURE(_CLASSIC, 0x01B0)
#define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040)
#define GPU_ARCHITECTURE_T13X GPU_ARCHITECTURE(_TEGRA, 0x0013)
@@ -93,6 +95,7 @@
#define GPU_IMPLEMENTATION_GA106 0x06
#define GPU_IMPLEMENTATION_GA107 0x07
#define GPU_IMPLEMENTATION_GA102F 0x0F
#define GPU_IMPLEMENTATION_GH100 0x00
#define GPU_IMPLEMENTATION_AD102 0x02
#define GPU_IMPLEMENTATION_AD103 0x03
@@ -103,6 +106,20 @@
#define GPU_IMPLEMENTATION_GB100 0x00
#define GPU_IMPLEMENTATION_GB102 0x02
#define GPU_IMPLEMENTATION_GB10B 0x0B
#define GPU_IMPLEMENTATION_GB202 0x02
#define GPU_IMPLEMENTATION_GB203 0x03
#define GPU_IMPLEMENTATION_GB204 0x04
#define GPU_IMPLEMENTATION_GB205 0x05
#define GPU_IMPLEMENTATION_GB206 0x06
#define GPU_IMPLEMENTATION_GB207 0x07
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00

8
src/common/inc/swref/published/nv_ref.h
View File

@@ -133,6 +133,7 @@
#define NV_PMC_BOOT_0_ARCHITECTURE_GH100 0x00000018 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_AD100 0x00000019 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GB100 0x0000001A /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GB200 0x0000001B /* R---V */
#define NV_PMC_BOOT_1 0x00000004 /* R--4R */
#define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */
@@ -152,11 +153,18 @@
#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE 29:24 /* */
#define NV_PMC_BOOT_42_CHIP_ID 29:20 /* R-XVF */
#define NV_PMC_BOOT_42_ARCHITECTURE_GM100 0x00000011 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GM200 0x00000012 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GP100 0x00000013 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV100 0x00000014 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV110 0x00000015 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_TU100 0x00000016 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GH100 0x00000018 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AD100 0x00000019 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GB100 0x0000001A /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GB200 0x0000001B /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AMODEL 0x0000001F /* */
#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* */

3
src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,4 +25,5 @@
#define __ls10_ptop_discovery_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SOE_0 0x00840000 /* */
#endif // __ls10_ptop_discovery_ip_h__

4
src/common/inc/swref/published/turing/tu102/kind_macros.h
View File

@@ -21,7 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#define _kind_macros_orig_H_
#ifndef TU102_KIND_MACROS_H_INCLUDED
#define TU102_KIND_MACROS_H_INCLUDED
#define KIND_INVALID(k) ( ((k) ==NV_MMU_CLIENT_KIND_INVALID))
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
@@ -32,3 +33,4 @@
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))
#endif // TU102_KIND_MACROS_H_INCLUDED