63 Commits

Author	SHA1	Message	Date
Chao Liu	52c3fe05be	Refactor for MIOpen integration (#4) ... Refactor, so can bring multi-index transformation and padding support into MIOpen	2019-10-11 11:37:31 -05:00
Chao Liu	9b280cc50d	remove dead code	2019-09-27 02:00:59 -05:00
Chao Liu	b12bbceebc	clean up	2019-09-26 14:59:19 -05:00
Chao Liu	51a9fa1dbd	removing dependency on old tensor descriptor	2019-09-26 11:49:05 -05:00
Chao Liu	39d92e7dfd	removing old implementation of tensor descriptor	2019-09-25 22:24:06 -05:00
Chao Liu	545d930568	refactor	2019-09-24 18:06:05 -05:00
Chao Liu	51884fc214	WIP: explicitly separate offset component into compile-time, block-invariant and per-thread components	2019-09-21 22:53:03 -05:00
Chao Liu	bf7e7d62a8	refactor	2019-09-19 23:44:23 -05:00
Chao Liu	b6e1c52a80	use buffer_load buffer_store intrinsic	2019-09-19 15:39:07 -05:00
Chao Liu	86cc678f18	add global_load and buffer_load inline asm	2019-09-18 15:41:55 -05:00
Chao Liu	5b7a18c506	experimenting global and buffer load/store	2019-09-18 02:05:42 -05:00
Chao Liu	c7a6545ec4	experimenting global and buffer load/store	2019-09-18 01:37:28 -05:00
Chao Liu	9f46cdf5fa	experimenting global and buffer load/store	2019-09-18 00:15:57 -05:00
Chao Liu	f58bf38445	enable hip compiler flag: -amdgpu-enable-global-sgpr-addr	2019-09-17 17:34:39 -05:00
Chao Liu	f7be86b9e4	refactor	2019-09-16 22:47:55 -05:00
Chao Liu	bf97542846	add lds doble buffer to nchw padded v4r1 and v4r4	2019-09-15 16:58:16 -05:00
Chao Liu	2c93b3057d	initial implementation for nchw v4r4 padding	2019-09-15 16:31:54 -05:00
Chao Liu	53094f7fae	clean up	2019-09-15 12:13:58 -05:00
Chao Liu	bd7a230006	clean up	2019-09-12 14:55:46 -05:00
Chao Liu	724e984bff	enabling padding for chwn format	2019-09-11 01:13:13 -05:00
Chao Liu	7a7fe16086	more utility code	2019-09-09 00:29:33 -05:00
Chao Liu	625838def0	added tuple	2019-09-06 18:07:56 -05:00
Chao Liu	86ceded98b	Merge remote-tracking branch 'origin/master' into add_padding	2019-08-15 13:48:45 -05:00
Chao Liu	0979fb4af9	clean up	2019-08-15 13:21:51 -05:00
Chao Liu	4fb81e008c	adding padding to implicit gemm v1r3	2019-08-14 10:55:34 -05:00
Chao Liu	40836ab926	add back some code	2019-08-13 12:21:38 -05:00
Chao Liu	8bdaba51f8	clean up	2019-08-13 00:37:23 -05:00
Chao Liu	fab2f10a55	clean up	2019-08-12 15:48:35 -05:00
Chao Liu	1c4ef23cff	cleaning up	2019-08-09 22:48:28 -05:00
Chao Liu	4908fe3fdc	tweak on amd	2019-08-08 12:14:06 -05:00
Chao Liu	a9b2b1dcd7	added ThreadwiseGenericTensorSliceCopy_v2r1	2019-08-08 02:42:52 -05:00
Chao Liu	bc9ea646f8	use ford/for instead of static_ford/static_for in threadwise copy, somehow register spill is greatly reduced on AMD	2019-08-07 19:09:13 -05:00
Chao Liu	5636576f9b	bug fix in ford, forgot to reorder lengths	2019-08-07 18:27:10 -05:00
Chao Liu	9d99a58072	adding ThreadwiseGenericTensorSliceCopy_v1r2	2019-08-07 16:51:14 -05:00
Chao Liu	1b3c2e4035	reworked ThreadwiseGenericTensorSliceCopy_v1	2019-08-07 00:52:13 -05:00
Chao Liu	fdcfae3a62	reimplement threadwise copy	2019-08-06 17:41:58 -05:00
Chao Liu	adc1008836	tweak	2019-08-03 15:05:25 -05:00
Chao Liu	c2d246696f	added implicit gemm v4r4 and double buffer	2019-08-03 00:19:19 -05:00
Chao Liu	c01af89928	added new tensor copy operator	2019-08-03 00:02:24 -05:00
Chao Liu	a9a392b44d	experimenting TensorCoordinate and new merged tensor copy operator	2019-08-01 15:32:40 -05:00
Chao Liu	2eeeb1766b	refactor	2019-07-30 22:50:51 -05:00
Chao Liu	08cbac98cc	added (1x4)x(2x4) threadwise gemm	2019-07-30 18:20:55 -05:00
Chao Liu	c5e5a9307b	retune implicit gemm v4r1	2019-07-30 12:10:28 -05:00
Chao Liu	cd8de11218	experimenting new merged tensor copy	2019-07-30 09:35:54 -05:00
Chao Liu	284e7bb317	refactored implicit gemm v1r3	2019-07-29 15:25:38 -05:00
Chao Liu	efd419ecbe	refactored implicit gemm v1r3	2019-07-29 15:01:01 -05:00
Chao Liu	9ba3b49158	adding implicit gemm v4r4	2019-07-28 19:39:57 -05:00
Chao Liu	8669e242ad	debugging	2019-07-15 22:00:48 -05:00
Chao Liu	5f82fdd9d3	adding implicit gemm v4r3	2019-07-15 17:42:18 -05:00
Chao Liu	61faf02b52	adding implicit GEMM v4r2	2019-07-15 16:17:36 -05:00