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AVX512 based SGEMM Optimizations

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- Updated with optimal cache-blocking sizes for MC, KC and NC for AVX512 Native SGEMM kernel.

AMD-Internal: [CPUPL-2385]
Change-Id: I1feae5ac79e960c6b26df24756d460243820b797
This commit is contained in:
Arnav Sharma
2022-08-11 08:45:49 +00:00
committed by Arnav Sharma
parent c85bbfdb50
commit a226e54421
1 changed files with 3 additions and 3 deletions
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6
config/zen4/bli_cntx_init_zen4.c
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@@ -43,10 +43,10 @@
/* s d c z */ \
bli_blksz_init_easy( &blkszs[ BLIS_MR ], 32, 16, 3, 3 ); \
bli_blksz_init_easy( &blkszs[ BLIS_NR ], 12, 14, 8, 4 ); \
bli_blksz_init_easy( &blkszs[ BLIS_MC ], 480, 240, 144, 18 ); \
bli_blksz_init ( &blkszs[ BLIS_KC ], 384, 512, 256, 566, \
bli_blksz_init_easy( &blkszs[ BLIS_MC ], 512, 240, 144, 18 ); \
bli_blksz_init ( &blkszs[ BLIS_KC ], 480, 512, 256, 566, \
480, 320, 256, 566 ); \
bli_blksz_init_easy( &blkszs[ BLIS_NC ], 3072, 4004, 4080, 256 ); \
bli_blksz_init_easy( &blkszs[ BLIS_NC ], 6144, 4004, 4080, 256 ); \
\
bli_blksz_init_easy( &blkszs[ BLIS_AF ], 8, 8, -1, -1 ); \
bli_blksz_init_easy( &blkszs[ BLIS_DF ], 8, 8, -1, -1 ); \