V, Varsha
d995496ac1
BugFix: BF16 AVX2 fallback GEMV m=1 path for reordered B inputs
...
- For BF16 GEMVM1 fallback path when B matrix is reordered,
there wasn't a panel adjustment happening after the kernel execution.
- When the input size exceeds the panel boundary this would cause
wrong panel access leading to incorrect results. Hence, added the same.
[ AMD-Internal : CPUPL-8201 ]
2026-03-25 12:34:51 +05:30
..
2026-02-04 13:16:46 +00:00
2026-03-25 12:34:51 +05:30
2025-02-07 05:41:44 -05:00
2025-10-17 15:38:02 +05:30
2025-06-30 11:16:04 +05:30
2025-09-11 18:27:19 +05:30
2025-06-30 11:16:04 +05:30
2025-09-17 18:28:34 +01:00
2025-08-26 16:46:37 +05:30
2024-08-05 15:35:08 -04:00
2025-02-10 01:06:39 -05:00
2025-08-26 16:37:43 +01:00
2025-08-26 16:37:43 +01:00
2026-03-05 13:33:56 +00:00
2026-03-05 13:33:56 +00:00
2025-09-11 18:27:19 +05:30
2025-06-30 11:16:04 +05:30
2026-02-06 10:41:38 +00:00
2025-09-11 18:27:19 +05:30
2025-07-15 12:26:05 +05:30
2025-03-28 00:51:17 -05:00
2026-02-25 17:21:12 +05:30
2025-09-19 18:49:33 +05:30
2026-02-25 17:21:12 +05:30
2025-08-22 18:46:19 +05:30
2025-08-22 18:46:19 +05:30
2025-08-26 16:37:43 +01:00
2025-08-22 18:46:19 +05:30
2025-08-22 18:46:19 +05:30
2024-06-24 07:55:34 -04:00
2025-09-19 18:49:33 +05:30
2025-08-22 18:46:19 +05:30
2025-08-22 18:46:19 +05:30
2025-04-15 09:45:48 +00:00
2025-08-22 18:46:19 +05:30
2025-08-22 18:46:19 +05:30
2025-02-07 11:43:28 +00:00
2024-12-12 06:37:06 -05:00
2024-08-05 15:35:08 -04:00