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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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73
src/common/displayport/inc/dp_configcaps.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -119,6 +119,12 @@ namespace DisplayPort
ITU709,
} ;
enum MainLinkChannelCoding
{
ChannelCoding8B10B = 0,
ChannelCoding128B132B,
};
#define HDCP_BCAPS_SIZE (0x1)
#define HDCP_VPRIME_SIZE (0x14)
#define HDCP_KSV_FIFO_SIZE (0xF)
@@ -162,6 +168,7 @@ namespace DisplayPort
//
virtual bool getLaneStatusClockRecoveryDone(int lane) = 0; // DPCD offset 202, 203
virtual bool getLaneStatusSymbolLock(int lane)= 0;
virtual bool getLaneStatusChannelEqualizationDone(int lane)= 0;
virtual bool getInterlaneAlignDone() = 0;
virtual bool getDownStreamPortStatusChange() = 0;
};
@@ -219,6 +226,7 @@ namespace DisplayPort
virtual AuxRetry::status setIgnoreMSATimingParamters(bool msaTimingParamIgnoreEn) = 0;
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern) = 0;
virtual AuxRetry::status setLinkQualPatternSet(LinkQualityPatternType linkQualPattern, unsigned laneCount = 0) = 0;
virtual AuxRetry::status setLinkQualPatternSet(DP2xPatternInfo& patternInfo, unsigned laneCount = 0) = 0;
};
class LinkCapabilities
@@ -230,6 +238,12 @@ namespace DisplayPort
//
virtual NvU64 getMaxLinkRate() = 0; // Maximum byte-block in Hz
virtual unsigned getMaxLaneCount() = 0; // DPCD offset 0x0002h
//
// Bit mask for sink side (sink and LTTPR) supported UHBR Link Rates.
// Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.UHBRSupportedByGpu and
// NV0073_CTRL_DFP_GET_INFO_PARAMS.UHBRSupportedByDfp
//
virtual NvU32 getUHBRSupported() = 0; // DPCD offset 0x2215h
virtual unsigned getMaxLaneCountSupportedAtLinkRate(LinkRate linkRate) = 0;
virtual bool getEnhancedFraming() = 0;
virtual bool getSupportsNoHandshakeTraining() = 0;
@@ -331,7 +345,7 @@ namespace DisplayPort
if (lttprGetRevisionMajor() > major)
return true;
if (lttprGetRevisionMinor() < major)
if (lttprGetRevisionMajor() < major)
return false;
return lttprGetRevisionMinor() >= minor;
@@ -432,7 +446,7 @@ namespace DisplayPort
// If set to HPD mode we'll always receive an HPD whenever the topology changes.
// The library supports using both modes.
//
virtual AuxRetry::status setMultistreamHotplugMode(MultistreamHotplugMode notifyType) = 0;
virtual AuxRetry::status setMultistreamHotplugMode(MultistreamHotplugMode notifyType) = 0;
//
// Interrupts
@@ -474,6 +488,10 @@ namespace DisplayPort
// DPCD offset 250 - 259
virtual void get80BitsCustomTestPattern(NvU8 *testPattern) = 0;
// DPCD offset 2230 - 2250
virtual void get264BitsCustomTestPattern(NvU8 *testPattern) = 0;
// DPCD offset 249
virtual void getSquarePatternNum(NvU8 *sqNum) = 0;
//
// Message Boxes
//
@@ -546,8 +564,12 @@ namespace DisplayPort
virtual bool clearDpTunnelingEstimatedBwStatus() = 0;
virtual bool clearDpTunnelingBwAllocationCapStatus() = 0;
virtual AuxRetry::status notifySDPErrDetectionCapability() = 0;
virtual bool isDp2xChannelCodingCapable() = 0;
virtual void setIgnoreCableIdCaps(bool bIgnore) = 0;
virtual void initialize() = 0;
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding) = 0;
virtual ~DPCDHAL() {}
};
//
@@ -652,7 +674,7 @@ namespace DisplayPort
bool bFECSupportedRepeater[NV_DPCD14_PHY_REPEATER_CNT_MAX];
// If all the LTTPRs supports FEC
bool bFECSupported;
bool bAuxlessALPMSupported; // DPCD offset F0009
} repeaterCaps;
struct
@@ -845,6 +867,10 @@ namespace DisplayPort
virtual LinkRate getMaxLinkRate();
virtual NvU32 getUHBRSupported()
{
return 0;
}
// DPCD offset 2
virtual unsigned getMaxLaneCount();
@@ -997,6 +1023,7 @@ namespace DisplayPort
virtual AuxRetry::status setIgnoreMSATimingParamters(bool msaTimingParamIgnoreEn);
virtual AuxRetry::status setLinkQualPatternSet(LinkQualityPatternType linkQualPattern, unsigned laneCount);
virtual AuxRetry::status setLinkQualPatternSet(DP2xPatternInfo& patternInfo, unsigned laneCount);
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern);
virtual AuxRetry::status setMessagingEnable(bool _uprequestEnable, bool _upstreamIsSource);
@@ -1171,6 +1198,11 @@ namespace DisplayPort
return interrupts.laneStatusIntr.laneStatus[lane].clockRecoveryDone;
}
virtual bool getLaneStatusChannelEqualizationDone(int lane)
{
return interrupts.laneStatusIntr.laneStatus[lane].channelEqualizationDone;
}
virtual bool getInterlaneAlignDone() // DPCD offset 204
{
return interrupts.laneStatusIntr.interlaneAlignDone;
@@ -1225,6 +1257,20 @@ namespace DisplayPort
}
}
// DPCD offset 2230 - 2250
virtual void get264BitsCustomTestPattern(NvU8 *testPattern)
{
DP_ASSERT(0 && "DP1x should never get this request.");
return;
}
// DPCD offset 249h
virtual void getSquarePatternNum(NvU8 *sqNum)
{
DP_ASSERT(0 && "DP1x should never get this request.");
return;
}
virtual bool getBKSV(NvU8 *bKSV);
virtual bool getBCaps(BCaps &bCaps, NvU8 * rawByte);
virtual bool getHdcp22BCaps(BCaps &bCaps, NvU8 *rawByte);
@@ -1437,6 +1483,23 @@ namespace DisplayPort
bool clearDpTunnelingEstimatedBwStatus();
bool clearDpTunnelingBwAllocationCapStatus();
virtual AuxRetry::status notifySDPErrDetectionCapability()
{
return AuxRetry::ack;
}
virtual bool isDp2xChannelCodingCapable()
{
return false;
}
virtual void setIgnoreCableIdCaps(bool bIgnore)
{
return;
}
// implement this function if DPCDHALImpl needs updated state between hotunplug/plug
virtual void initialize(){};
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding){ return AuxRetry::ack; }
virtual MainLinkChannelCoding getMainLinkChannelCoding() { return ChannelCoding8B10B; }
};
}

148
src/common/displayport/inc/dp_configcaps2x.h Normal file
View File

@@ -0,0 +1,148 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_configcaps2x.h *
* Abstraction for DP2x caps registers *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_CONFIGCAPS_2X_H
#define INCLUDED_DP_CONFIGCAPS_2X_H
#include "dp_configcaps.h"
namespace DisplayPort
{
enum CableType
{
CableTypeUnknown = 0,
CableTypePassive = 1,
CableTypeLRD = 2,
CableTypeActiveReTimer = 3,
};
struct DPCDHALImpl2x : DPCDHALImpl
{
struct
{
// 0x2206, if the sink supports 128b/132b
bool bDP2xChannelCodingSupported;
// 0x2215
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
struct
{
// 0xF0006, if the PHY Repeater supports 128b/132b
bool bDP2xChannelCodingSupported;
// 0xF0007
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
} repeaterCaps;
struct
{
bool bDP2xChannelCodingSupported;
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
} dpInTunnelingCaps;
struct
{
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
CableType cableType;
} cableCaps;
} caps2x;
struct
{
// DPCD offset 2230 - 2250
NvU8 cstm264Bits[NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN__SIZE];
struct
{
bool testRequestPhyCompliance; // DPCD offset 218
LinkQualityPatternType phyTestPattern; // DPCD offset 248
//
// Only valid when phyTestPattern is
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF
//
NvU32 sqNum; // DPCD offset 249
} testPhyCompliance2x;
} interrupts2x;
virtual AuxRetry::status notifySDPErrDetectionCapability();
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding);
virtual MainLinkChannelCoding getMainLinkChannelCoding();
void performCableIdHandshake();
virtual void setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions);
virtual bool isDp2xChannelCodingCapable();
virtual void parseAndReadCaps();
virtual LinkRate getMaxLinkRate();
virtual NvU32 getUHBRSupported();
virtual void setIgnoreCableIdCaps(bool bIgnore){ bIgnoreCableIdCaps = bIgnore; }
virtual bool parseTestRequestPhy();
virtual bool parseTestRequestTraining(NvU8 * buffer);
// DPCD offset 2230 - 2250
virtual void get264BitsCustomTestPattern(NvU8 *testPattern);
// DPCD offset 249h
virtual void getSquarePatternNum(NvU8 *sqNum);
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern);
virtual AuxRetry::status setLinkQualPatternSet(DP2xPatternInfo& patternInfo, unsigned laneCount);
// class fields that need re-initialization
bool bIgnoreCableIdCaps;
virtual void initialize()
{
setIgnoreCableIdCaps(false);
}
DPCDHALImpl2x(AuxBus * bus, Timer * timer) : DPCDHALImpl(bus, timer), bIgnoreCableIdCaps(false)
{
dpMemZero(&caps2x, sizeof(caps2x));
dpMemZero(&interrupts2x, sizeof(interrupts2x));
caps2x.bDP2xChannelCodingSupported = true;
caps2x.bUHBR_10GSupported = true;
caps2x.bUHBR_13_5GSupported = true;
caps2x.bUHBR_20GSupported = true;
caps2x.cableCaps.bUHBR_10GSupported = true;
caps2x.cableCaps.bUHBR_13_5GSupported = true;
caps2x.cableCaps.bUHBR_20GSupported = true;
};
};
}
#endif //INCLUDED_DP_CONFIGCAPS_2X_H

20
src/common/displayport/inc/dp_connector.h
View File

@@ -336,6 +336,18 @@ namespace DisplayPort
virtual bool setModeList(DisplayPort::DpModesetParams *pModeList, unsigned numModes) = 0;
virtual NvBool isSelectiveUpdateSupported(void) = 0;
virtual NvBool isEarlyRegionTpSupported(void) = 0;
virtual NvBool enableAdaptiveSyncSdp(NvBool enable) = 0;
virtual SelectiveUpdateCaps getSelectiveUpdateCaps(void) = 0;
virtual NvBool isAdaptiveSyncSdpNotSupportedInPr(void) = 0;
virtual NvBool isdscDecodeNotSupportedInPr(void) = 0;
virtual NvBool isLinkOffSupportedAfterAsSdpInPr(void) = 0;
virtual void getAlpmCaps(void) = 0;
virtual NvBool setAlpmConfig(AlpmConfig alpmcfg) = 0;
virtual NvBool getAlpmStatus(AlpmStatus *pAlpmStatus) = 0;
virtual NvBool isAuxLessAlpmSupported(void) = 0;
protected:
virtual ~Device() {}
@@ -731,6 +743,10 @@ namespace DisplayPort
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool setLaneConfig(NvU32 numLanes, NvU32 *data) = 0;
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool getDp2xLaneConfig(NvU32 *numLanes, NvU32 *data) = 0;
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool setDp2xLaneConfig(NvU32 numLanes, NvU32 *data) = 0;
virtual DP_TESTMESSAGE_STATUS sendDPTestMessage(void *pBuffer,
NvU32 requestSize,
NvU32 *pDpStatus) = 0;
@@ -752,7 +768,9 @@ namespace DisplayPort
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0;
virtual void enableDpTunnelingBwAllocationSupport() = 0;
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo) = 0;
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
const DscParams *pDscParams = NULL) = 0;
protected:
virtual ~Connector() {}

51
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -197,6 +197,8 @@ namespace DisplayPort
unsigned compoundQueryLocalLinkPBN;
NvU64 compoundQueryUsedTunnelingBw;
bool compoundQueryForceEnableFEC;
// WAR
bool bDP2XPreferNonDSCForLowPClk;
unsigned freeSlots;
unsigned maximumSlots;
@@ -262,7 +264,7 @@ namespace DisplayPort
bool bSkipLt;
// Flag to make sure that zombie gets triggred when a powerChange event happens
bool bMitigateZombie;
bool bMitigateZombie;
//
// HP Valor QHD+ N15P-Q3 EDP needs 50ms delay after D3
@@ -324,6 +326,9 @@ namespace DisplayPort
//
NvU32 LT2FecLatencyMs;
// On eDP, do not cache the source OUI if it reads 0. See bug 4793112
bool bSkipZeroOuiCache;
//
// Dual SST Partner connector object pointer
ConnectorImpl *pCoupledConnector;
@@ -384,8 +389,9 @@ namespace DisplayPort
DwnStreamPortAttribute portAttribute,
bool isCompliance = false);
void applyEdidWARs(Edid &edid, DiscoveryManager::Device device);
void applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase);
void applyEdidWARs(Edid &edid, DiscoveryManager::Device &device);
virtual void handleEdidWARs(Edid &edid, DiscoveryManager::Device &device){};
void applyRegkeyOverrides(const DP_REGKEY_DATABASE &dpRegkeyDatabase);
ResStatusNotifyMessage ResStatus;
@@ -406,13 +412,14 @@ namespace DisplayPort
bool detectSinkCountChange();
virtual bool handlePhyPatternRequest();
void applyOuiWARs();
virtual bool handleTestLinkTrainRequest();
virtual void applyOuiWARs();
bool linkUseMultistream()
{
return (linkState == DP_TRANSPORT_MODE_MULTI_STREAM);
}
void populateAllDpConfigs();
virtual void populateAllDpConfigs();
virtual LinkRates* importDpLinkRates();
//
@@ -564,7 +571,9 @@ namespace DisplayPort
virtual void notifyAttachEnd(bool modesetCancelled);
virtual void notifyDetachBegin(Group * target);
virtual void notifyDetachEnd(bool bKeepOdAlive = false);
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo);
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
const DscParams *pDscParams = NULL);
bool performIeeeOuiHandshake();
void setIgnoreSourceOuiHandshake(bool bIgnore);
@@ -599,7 +608,8 @@ namespace DisplayPort
}
bool trainLinkOptimized(LinkConfiguration lConfig);
bool trainLinkOptimizedSingleHeadMultipleSST(GroupImpl * group);
bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected, ModesetInfo queryModesetInfo);
bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected,
ModesetInfo queryModesetInfo, const DscParams *pDscParams = NULL);
bool postLTAdjustment(const LinkConfiguration &, bool force);
void populateUpdatedLaneSettings(NvU8* voltageSwingLane, NvU8* preemphasisLane, NvU32 *data);
void populateDscCaps(DSC_INFO* dscInfo, DeviceImpl * dev, DSC_INFO::FORCED_DSC_PARAMS* forcedParams);
@@ -634,6 +644,7 @@ namespace DisplayPort
bool deleteAllVirtualChannels();
void clearTimeslices();
virtual void applyTimeslotWAR(unsigned &slot_count){};
virtual bool allocateTimeslice(GroupImpl * targetGroup);
void freeTimeslice(GroupImpl * targetGroup);
void flushTimeslotsToHardware();
@@ -647,9 +658,9 @@ namespace DisplayPort
void handleDpTunnelingIrq();
void handleHdmiLinkStatusChanged();
void sortActiveGroups(bool ascending);
void configInit();
void handlePanelReplayError();
virtual void configInit();
virtual DeviceImpl* findDeviceInList(const Address &address);
virtual void disconnectDeviceList();
void notifyLongPulseInternal(bool statusConnected);
@@ -666,7 +677,7 @@ namespace DisplayPort
virtual bool isFECSupported();
virtual bool isFECCapable();
virtual NvU32 maxLinkRateSupported();
bool setPreferredLinkConfig(LinkConfiguration &lc, bool commit,
bool setPreferredLinkConfig(LinkConfiguration &lc, bool commit,
bool force = false,
LinkTrainingType trainType = NORMAL_LINK_TRAINING,
bool forcePreferredLinkConfig = false);
@@ -689,6 +700,28 @@ namespace DisplayPort
bool setTestPattern(NV0073_CTRL_DP_TESTPATTERN testPattern, NvU8 laneMask, NV0073_CTRL_DP_CSTM cstm, NvBool bIsHBR2, NvBool bSkipLaneDataOverride = false);
bool getLaneConfig(NvU32 *numLanes, NvU32 *data); // "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
bool setLaneConfig(NvU32 numLanes, NvU32 *data); // "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool getDp2xLaneConfig(NvU32 *numLanes, NvU32 *data)
{
// The function is only for Connector class 2x (or later) that supports 128b/132b channel coding.
return false;
}
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool setDp2xLaneConfig(NvU32 numLanes, NvU32 *data)
{
// The function is only for Connector class 2x (or later) that supports 128b/132b channel coding.
return false;
}
virtual void setDisableDownspread(bool _bDisableDownspread)
{
return;
}
virtual bool getDownspreadDisabled()
{
return false;
}
void getCurrentLinkConfig(unsigned &laneCount, NvU64 &linkRate); // CurrentLink Configuration
unsigned getPanelDataClockMultiplier();
unsigned getGpuDataClockMultiplier();

111
src/common/displayport/inc/dp_connectorimpl2x.h Normal file
View File

@@ -0,0 +1,111 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort********************************\
* *
* Module: dp_connectorimpl2x.cpp *
* DP connector implementation for DP2.x *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_CONNECTORIMPL2X_H
#define INCLUDED_DP_CONNECTORIMPL2X_H
#include "dp_connector.h"
#include "ctrl/ctrl0073/ctrl0073dp.h"
namespace DisplayPort
{
struct ConnectorImpl2x : public ConnectorImpl
{
virtual void configInit();
virtual void populateAllDpConfigs();
virtual LinkRates* importDpLinkRates();
virtual LinkConfiguration getMaxLinkConfig();
virtual bool train(const LinkConfiguration & lConfig, bool force,
LinkTrainingType trainType = NORMAL_LINK_TRAINING);
virtual bool allocateTimeslice(GroupImpl * targetGroup);
virtual bool checkIsModePossibleMST(GroupImpl * group);
virtual bool compoundQueryAttachMSTGeneric(Group * target,
const DpModesetParams &modesetParams, // Modeset info
CompoundQueryAttachMSTInfo * info, // local info with updates for DSC
DscParams *pDscParams = NULL, // DSC parameters
DP_IMP_ERROR *pErrorCode = NULL); // Error Status code
virtual bool notifyAttachBegin(Group *target, const DpModesetParams &modesetParams);
virtual void notifyAttachEnd(bool modesetCancelled);
virtual void notifyDetachBegin(Group *target);
virtual void notifyDetachEnd(bool bKeepOdAlive);
virtual bool beforeAddStream(GroupImpl * group, bool test = false, bool forFlushMode = false);
virtual void afterAddStream(GroupImpl * group);
virtual void beforeDeleteStream(GroupImpl * group, bool forFlushMode);
virtual void afterDeleteStream(GroupImpl * group);
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo,
const DscParams *pDscParams = NULL);
bool willLinkSupportMode(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo,
NvU32 headIndex = 0, Watermark *watermark = NULL, const DscParams *pDscParams = NULL);
virtual bool handlePhyPatternRequest();
virtual bool handleTestLinkTrainRequest();
ConnectorImpl2x(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);
bool validateLinkConfiguration(const LinkConfiguration & lConfig);
bool enableFlush();
void disableFlush(bool test = false);
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool getDp2xLaneConfig(NvU32 *numLanes, NvU32 *data);
virtual bool setDp2xLaneConfig(NvU32 numLanes, NvU32 *data);
void applyDP2xRegkeyOverrides();
virtual void applyOuiWARs();
virtual void handleEdidWARs(Edid &edid, DiscoveryManager::Device &device);
virtual void applyTimeslotWAR(unsigned &slot_count);
bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
bool bFlushSkipped;
bool bMstTimeslotBug4968411;
bool bApplyManualTimeslotBug4968411;
// Do not enable downspread while link training.
bool bDisableDownspread;
virtual void setDisableDownspread(bool _bDisableDownspread)
{
this->bDisableDownspread = _bDisableDownspread;
}
virtual bool getDownspreadDisabled()
{
return this->bDisableDownspread;
}
};
}
#endif //INCLUDED_DP_CONNECTORIMPL2X_H

13
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -172,6 +172,8 @@ namespace DisplayPort
// Panel replay Caps
PanelReplayCaps prCaps;
// ALPM caps
AlpmCaps alpmCaps;
bool bIsFakedMuxDevice;
bool bIsPreviouslyFakedMuxDevice;
bool bisMarkedForDeletion;
@@ -455,6 +457,17 @@ namespace DisplayPort
bool setPanelReplayConfig(panelReplayConfig prcfg);
bool getPanelReplayConfig(panelReplayConfig *pPrcfg);
bool getPanelReplayStatus(PanelReplayStatus *pPrStatus);
NvBool isSelectiveUpdateSupported(void);
NvBool isEarlyRegionTpSupported(void);
NvBool enableAdaptiveSyncSdp(NvBool enable);
SelectiveUpdateCaps getSelectiveUpdateCaps(void);
NvBool isAdaptiveSyncSdpNotSupportedInPr(void);
NvBool isdscDecodeNotSupportedInPr(void);
NvBool isLinkOffSupportedAfterAsSdpInPr(void);
void getAlpmCaps(void);
NvBool setAlpmConfig(AlpmConfig alpmcfg);
NvBool getAlpmStatus(AlpmStatus *pAlpmStatus);
NvBool isAuxLessAlpmSupported(void);
NvBool getDSCSupport();
bool getFECSupport();

3
src/common/displayport/inc/dp_edid.h
View File

@@ -166,6 +166,9 @@ namespace DisplayPort
bool keepLinkAlive;
bool useLegacyAddress;
bool bIgnoreDscCap; // Ignore DSC even if sink reports DSC capability
bool bDisableDownspread;
bool bSkipCableIdCheck;
bool bAllocateManualTimeslots;
}_WARFlags;
_WARFlags WARFlags;

33
src/common/displayport/inc/dp_evoadapter.h
View File

@@ -135,8 +135,8 @@ namespace DisplayPort
{
private:
NvU32 _maxLinkRateSupportedGpu;
NvU32 _minPClkForCompressed;
NvU32 _maxLinkRateSupportedDfp;
unsigned allHeadMask;
bool _hasIncreasedWatermarkLimits;
bool _hasMultistream;
bool _isPC2Disabled;
@@ -188,10 +188,13 @@ namespace DisplayPort
NvU32 displayId;
NvU32 subdeviceIndex;
unsigned allHeadMask;
NV0073_CTRL_DFP_GET_INFO_PARAMS dfpParams;
NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS dpParams;
bool _isDownspreadDisabledByRegkey;
public:
EvoMainLink(EvoInterface * provider, Timer * timer);
@@ -210,10 +213,19 @@ namespace DisplayPort
return _isPC2Disabled;
}
virtual NvU32 getMinPClkForCompressed()
{
return _minPClkForCompressed;
}
virtual NvU32 getGpuDpSupportedVersions()
{
return _gpuSupportedDpVersions;
}
virtual NvU32 getUHBRSupported()
{
return 0U;
}
virtual bool isFECSupported()
{
return _isFECSupported;
@@ -235,9 +247,9 @@ namespace DisplayPort
if ((_applyLinkBwOverrideWarRegVal || _useDfpMaxLinkRateCaps) &&
(_maxLinkRateSupportedDfp < _maxLinkRateSupportedGpu))
{
return (LINK_RATE_TO_DATA_RATE_8B_10B(_maxLinkRateSupportedDfp));
return _maxLinkRateSupportedDfp;
}
return (LINK_RATE_TO_DATA_RATE_8B_10B(_maxLinkRateSupportedGpu));
return _maxLinkRateSupportedGpu;
}
virtual bool isForceRmEdidRequired()
@@ -326,9 +338,12 @@ namespace DisplayPort
// Return the current mux state. Returns false if device is not mux capable
bool getDynamicMuxState(NvU32 *muxState);
virtual bool aquireSema();
virtual void releaseSema();
virtual bool physicalLayerSetTestPattern(PatternInfo * patternInfo);
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo *patternInfo)
{
DP_ASSERT(0 && "DP1x should never get this request.");
return false;
}
virtual void preLinkTraining(NvU32 head);
virtual void postLinkTraining(NvU32 head);
virtual NvU32 getRegkeyValue(const char *key);
@@ -354,9 +369,7 @@ namespace DisplayPort
void configureHDCPGetHDCPState(HDCPState &hdcpState);
bool rmUpdateDynamicDfpCache(NvU32 headIndex, RmDfpCache * dfpCache, NvBool bResetDfp);
virtual NvU32 streamToHead(NvU32 streamId, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
virtual NvU32 headToStream(NvU32 head, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
void configureSingleStream(NvU32 head,
NvU32 hBlankSym,
@@ -412,6 +425,10 @@ namespace DisplayPort
bool freeDisplayId(NvU32 displayId);
virtual bool queryAndUpdateDfpParams();
virtual bool queryGPUCapability();
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 sinkUhbrCaps = 0)
{
return;
}
bool getEdpPowerData(bool *panelPowerOn, bool *dpcdPowerStateD0);
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status);

176
src/common/displayport/inc/dp_evoadapter2x.h Normal file
View File

@@ -0,0 +1,176 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* List **************************************\
* *
* Module: dp_evoadapter2x.h *
* Interface for low level access to the aux bus for dp2x. *
* This is the synchronous version of the interface. *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_EVOADAPTER2X_H
#define INCLUDED_DP_EVOADAPTER2X_H
#include "dp_evoadapter.h"
#include "dp_timeout.h"
#include "dp_linkconfig.h"
// For channel equalization, total poll time is 450ms. Set it to 500ms for timer granularity
#define NV_DP2X_LT_MAX_TIME_POLL_CHNL_EQ_MS (500U)
// For channel equalization, max loop count is 20 when waiting CHANNEL_EQ_DONE set.
#define NV_DP2X_LT_MAX_LOOP_COUNT_POLL_CHNL_EQ_DONE (20U)
// For channel equalization, polling interval is 3 when waiting INTERLANE_ALIGN_DONE.
#define NV_DP2X_LT_CHNL_EQ_INTERLANE_ALIGN_POLLING_INTERVAL (3U)
// Unit definitions for Aux Read Intervals
#define NV_DP2X_LT_CHNL_EQ_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (1U)
#define NV_DP2X_LT_CHNL_EQ_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (2U)
// For phase CDS, total time is (LTTPR + 1) * 20
#define NV_DP2X_LT_MAX_POLL_TIME_CDS_MS(i) ((i+1) * 20)
#define NV_DP2X_LT_CDS_POLLING_INTERVAL 3U
//
// Total possible link configurations for DP2.x fallback table.
// Total number of link rates supported is 15:
// 3 UHBR: UHBR20, UHBR13.5, UHBR10
// 3 UHBR for internal test:
// UHBR2.5, UHBR2.7, UHBR5.0
// 4 Legacy: HBR3, HBR2, HBR, RBR
// 5 ILR: 2.16G, 2.43G, 3.24G, 4.32G, 6.75G
// Total number of lane count supported is 3 (1, 2, 4)
// Total possible link configurations => 15 * 3 = 45.
//
#define NV_DP2X_VALID_LINK_CONFIGURATION_COUNT 45U
namespace DisplayPort
{
// Simplified LinkConfiguration for fallback map
typedef struct
{
NvU32 laneCount;
// 10M unit
LinkRate linkRate;
//
// The flag indicates if the link configuration is avaiable on the setup.
// Both link count and link rate have to be supported.
//
bool bSupported;
//
// The flag indicates if the link rate can be trained with 128b/132b channel
// coding. Default false for non-UHBR link rates.
//
bool bUseDP2xChannelCoding;
} SIMPLIFIED_DP2X_LINKCONFIG;
typedef struct
{
DP2X_RESET_LINK_REASON reason;
bool bForce;
} DP2XResetParam;
class EvoMainLink2x : public EvoMainLink
{
//
// Bit mask for GPU/DFP supported UHBR Link Rates.
// Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.UHBRSupportedByGpu and
// NV0073_CTRL_DFP_GET_INFO_PARAMS.UHBRSupportedByDfp
//
NvU32 gpuUhbrCaps;
NvU32 dfpUhbrCaps;
bool bUseRgFlushSequence;
bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
// Start time of DP2.x LT Channel Eqaulization phase.
NvU64 channelEqualizationStartTimeUs;
bool pollDP2XLinkTrainingStageDone(NvU32 stage, NvU32 laneCount,
NvU32 phyRepeaterCount, NvU32 pollingInterval, bool force);
//
// Find next available link configuration in fallback mandate.
// Return false if not available
//
bool getFallbackForDP2xLinkTraining(LinkConfiguration *link);
//
// Check if the link configuration is supported on the system,
// and with correct channel encoding.
// Return false if not.
//
bool isSupportedDPLinkConfig(LinkConfiguration &link);
// Before link training start, reset DPRX link and make sure it's ready.
bool resetDPRXLink(DP2XResetParam param);
SIMPLIFIED_DP2X_LINKCONFIG fallbackMandateTable[NV_DP2X_VALID_LINK_CONFIGURATION_COUNT];
NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS ltRmParams;
public:
virtual bool queryGPUCapability();
virtual bool queryAndUpdateDfpParams();
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 uhbrCaps = 0);
virtual bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates);
void validateIlrInFallbackMap(LinkRate ilr, bool bUseDP2xChannelCoding);
virtual NvU32 maxLinkRateSupported();
virtual bool setFlushMode(FlushModePhase phase);
virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0);
virtual bool isRgFlushSequenceUsed() {return bUseRgFlushSequence;}
void applyDP2xRegkeyOverrides();
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
// Link Rate will return the value with 10M convention!
virtual void getLinkConfig(unsigned &laneCount, NvU64 & linkRate);
virtual NvU32 getUHBRSupported(void)
{
return (gpuUhbrCaps & dfpUhbrCaps);
}
virtual bool train(const LinkConfiguration & link, bool force,
LinkTrainingType linkTrainingType,
LinkConfiguration *retLink, bool bSkipLt = false,
bool isPostLtAdjRequestGranted = false,
unsigned phyRepeaterCount = 0);
bool trainDP2xChannelCoding(LinkConfiguration & link, bool force,
LinkTrainingType linkTrainingType,
LinkConfiguration *retLink,
bool bSkipLt, bool isPostLtAdjRequestGranted,
unsigned phyRepeaterCount);
EvoMainLink2x(EvoInterface *provider, Timer * timer);
virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data);
virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data);
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo *patternInfo);
};
}
#endif // INCLUDED_DP_EVOADAPTER_H

12
src/common/displayport/inc/dp_groupimpl.h
View File

@@ -74,13 +74,13 @@ namespace DisplayPort
headInFirmware(false),
bIsHeadShutdownNeeded(true),
hdcpEnabled(false),
hdcpPreviousStatus(false),
hdcpPreviousStatus(false),
bWaitForDeAllocACT(false),
dscModeRequest(DSC_MODE_NONE),
dscModeActive(DSC_MODE_NONE),
singleHeadMultiStreamID(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY),
singleHeadMultiStreamMode(DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE),
headAttached(false)
headAttached(false), timeslotAllocated(false)
{
timeslot.count = 0;
}
@@ -96,7 +96,7 @@ namespace DisplayPort
virtual Device * enumDevices(Device * previousDevice);
void updateVbiosScratchRegister(Device * lastDevice); // Update the VBIOS scratch register with last lit display
//
// Timer callback tags.
// (we pass the address of these variables as context to ::expired)
@@ -114,8 +114,12 @@ namespace DisplayPort
bool isHeadAttached() { return headAttached; }
void setHeadAttached(bool attached);
bool isTimeslotAllocated() { return timeslotAllocated; }
void setTimeslotAllocated(bool allocated) {timeslotAllocated = allocated;}
private:
bool headAttached; // True if modeset started (during NAB). Sets back to False during NDE
bool headAttached; // True if modeset started (during NAB). Sets back to False during NDE
bool timeslotAllocated; // True if timeslot is allocated for the group (beforeAddStream). Sets back to False during afterDeleteStream
};
}

198
src/common/displayport/inc/dp_linkconfig.h
View File

@@ -36,7 +36,9 @@
#include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE
#include "displayport.h"
#define NV_SUPPORTED_DP_LINK_RATES__SIZE NV_SUPPORTED_DP1X_LINK_RATES__SIZE
#include "displayport2x.h"
#define NV_SUPPORTED_DP_LINK_RATES__SIZE NV_SUPPORTED_DP2X_LINK_RATES__SIZE
extern NvU32 bSupportInternalUhbrOnFpga;
namespace DisplayPort
{
typedef NvU64 LinkRate;
@@ -66,9 +68,11 @@ namespace DisplayPort
}
}
// Only use import if element can be added at the end
// given element list needs to be sorted
bool import(NvU16 linkBw)
{
if (!IS_VALID_LINKBW_10M(linkBw))
if (!IS_VALID_DP2_X_LINKBW(linkBw))
{
DP_ASSERT(0 && "Unsupported Link Bandwidth");
return false;
@@ -84,6 +88,48 @@ namespace DisplayPort
return false;
}
// Use insert to import to the right spot in the sorted
// element list if you are not sure of where linkBw is compared
// to existing entries in the element list
bool insert(NvU16 linkBw)
{
if (!IS_VALID_DP2_X_LINKBW(linkBw))
{
DP_ASSERT(0 && "Unsupported Link Bandwidth");
return false;
}
for (int i = 0; i < entries; i++)
{
if (element[i] == linkBw)
{
// element already present, nothing to do here
return true;
}
else if (element[i] > linkBw)
{
// make space for the new element
if (entries >= NV_SUPPORTED_DP_LINK_RATES__SIZE) {
DP_ASSERT(0 && "No more space for adding additional link rate");
return false;
}
for (int j = entries-1; j >= i; j--)
{
element[j+1] = element[j];
}
entries++;
// space is made, insert linkBw to the right spot
element[i] = linkBw;
return true;
}
}
// if we are here and not returned, that means linkBw is bigger than
// the current entries, just import
return import(linkBw);
}
LinkRate getLowerRate(LinkRate rate)
{
int i;
@@ -173,7 +219,14 @@ namespace DisplayPort
EDP_3_24GHZ = 324000000,
EDP_4_32GHZ = 432000000,
HBR2 = 540000000,
HBR3 = 810000000
EDP_6_75GHZ = 675000000,
HBR3 = 810000000,
UHBR_2_50GHZ = 303030303, // 2.5G * (128 / 132) / 8
UHBR_2_70GHZ = 327272727, // 2.7G * (128 / 132) / 8
UHBR_5_00GHZ = 606060606, // 5.0G * (128 / 132) / 8
UHBR_10_0GHZ = 1212121212, // 10.0G * (128 / 132) / 8
UHBR_13_5GHZ = 1636363636, // 13.5G * (128 / 132) / 8
UHBR_20_0GHZ = 2424242424 // 20.0G * (128 / 132) / 8
};
struct HDCPState
@@ -222,6 +275,8 @@ namespace DisplayPort
bool disablePostLTRequest;
bool bEnableFEC;
bool bDisableLTTPR;
bool bDisableDownspread;
bool bIs128b132bChannelCoding;
//
// The counter to record how many times link training happens.
// Client can reset the counter by calling setLTCounter(0)
@@ -231,12 +286,16 @@ namespace DisplayPort
LinkConfiguration() :
lanes(0), peakRatePossible(0), peakRate(0), minRate(0),
enhancedFraming(false), multistream(false), disablePostLTRequest(false),
bEnableFEC(false), bDisableLTTPR(false),
bEnableFEC(false), bDisableLTTPR(false), bDisableDownspread(false),
bIs128b132bChannelCoding(false),
linkTrainCounter(0) {};
LinkConfiguration(LinkPolicy * p, unsigned lanes, LinkRate peakRate,
bool enhancedFraming, bool MST, bool disablePostLTRequest = false,
bool bEnableFEC = false, bool bDisableLTTPR = false);
bool enhancedFraming, bool MST,
bool disablePostLTRequest = false,
bool bEnableFEC = false,
bool bDisableLTTPR = false,
bool bDisableDownspread = false);
void setLTCounter(unsigned counter)
{
@@ -252,7 +311,14 @@ namespace DisplayPort
NvU64 convertLinkRateToDataRate(LinkRate linkRate) const
{
NvU64 dataRate;
dataRate = LINK_RATE_TO_DATA_RATE_8B_10B(linkRate);
if (bIs128b132bChannelCoding)
{
dataRate = LINK_RATE_TO_DATA_RATE_128B_132B(linkRate);
}
else
{
dataRate = LINK_RATE_TO_DATA_RATE_8B_10B(linkRate);
}
return dataRate;
}
@@ -260,7 +326,14 @@ namespace DisplayPort
NvU64 convertMinRateToDataRate() const
{
NvU64 dataRate;
dataRate = DP_LINK_RATE_BITSPS_TO_BYTESPS(OVERHEAD_8B_10B(minRate));
if (bIs128b132bChannelCoding)
{
dataRate = DP_LINK_RATE_BITSPS_TO_BYTESPS(DATA_BW_EFF_128B_132B(minRate));
}
else
{
dataRate = DP_LINK_RATE_BITSPS_TO_BYTESPS(OVERHEAD_8B_10B(minRate));
}
return dataRate;
}
@@ -269,22 +342,28 @@ namespace DisplayPort
return (convertLinkRateToDataRate(peakRate) * lanes);
}
NvU64 linkOverhead(NvU64 rate)
NvU64 linkOverhead(NvU64 rate10M)
{
if(IS_VALID_LINKBW_10M(rate))
NvU64 rate;
if(IS_VALID_DP2_X_LINKBW(rate10M))
{
// Converting here so that minRate from 10M is converted to bps
rate = DP_LINK_RATE_10M_TO_BPS(rate);
rate = DP_LINK_RATE_10M_TO_BPS(rate10M);
}
else
{
// Convert from data rate to bps
rate = DATA_RATE_8B_10B_TO_LINK_RATE_BPS(rate);
rate = DATA_RATE_8B_10B_TO_LINK_RATE_BPS(rate10M);
}
if(IS_DP2_X_UHBR_LINKBW(rate10M))
{
// Consider downspread only. FEC is already considered
// in 128b/132b channel encoding
return rate - 6 * rate/ 1000;
}
if(bEnableFEC)
{
// if FEC is enabled, we have to account for 3% overhead
// for FEC+downspread according to DP 1.4 spec
@@ -295,7 +374,6 @@ namespace DisplayPort
// if FEC is not enabled, link overhead comprises only of
// 0.6% downspread.
return rate - 6 * rate/ 1000;
}
}
@@ -312,6 +390,8 @@ namespace DisplayPort
disablePostLTRequest(false),
bEnableFEC(false),
bDisableLTTPR(false),
bDisableDownspread(false),
bIs128b132bChannelCoding(false),
linkTrainCounter(0)
{
//
@@ -432,6 +512,42 @@ namespace DisplayPort
minRate = linkOverhead(dp2LinkRate_8_10Gbps);
lanes = 4;
}
else if (TotalLinkPBN <= 3878)
{
peakRatePossible = dp2LinkRate_13_5Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_13_5Gbps);
lanes = 2;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else if (TotalLinkPBN <= 5746)
{
peakRatePossible = dp2LinkRate_10_0Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_10_0Gbps);
lanes = 4;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else if (TotalLinkPBN <= 7757)
{
peakRatePossible = dp2LinkRate_13_5Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_13_5Gbps);
lanes = 4;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else if (TotalLinkPBN <= 11492)
{
peakRatePossible = dp2LinkRate_20_0Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_20_0Gbps);
lanes = 4;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else
{
peakRatePossible = dp2LinkRate_1_62Gbps;
@@ -454,11 +570,19 @@ namespace DisplayPort
bool lowerConfig(bool bReduceLaneCnt = false);
void setChannelCoding();
void setChannelCoding(bool bIs128b132bChannelCoding)
{
this->bIs128b132bChannelCoding = bIs128b132bChannelCoding;
}
void setLaneRate(LinkRate newRate, unsigned newLanes)
{
peakRate = newRate;
lanes = newLanes;
minRate = linkOverhead(peakRate);
setChannelCoding();
}
unsigned pbnTotal()
@@ -466,45 +590,13 @@ namespace DisplayPort
return PBNForSlots(totalUsableTimeslots);
}
void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn)
{
base_pbn = pbnForMode(modesetInfo);
if (bEnableFEC)
{
// IF FEC is enabled, we need to consider 3% overhead as per DP1.4 spec.
base_pbn = (NvU32)(divide_ceil(base_pbn * 100, 97));
}
slots = slotsForPBN(base_pbn);
slots_pbn = PBNForSlots(slots);
}
NvU64 getBytesPerTimeslot();
NvU32 slotsForPBN(NvU32 allocatedPBN, bool usable = false)
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
NvU64 bytes_per_timeslot = getTotalDataRate() / 64;
void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn);
if (bytes_per_timeslot == 0)
return (NvU32)-1;
NvU32 slotsForPBN(NvU32 allocatedPBN, bool usable = false);
if (usable)
{
// round down to find the usable integral slots for a given value of PBN.
NvU32 slots = (NvU32)divide_floor(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
DP_ASSERT(slots <= 64);
return slots;
}
else
return (NvU32)divide_ceil(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
}
NvU32 PBNForSlots(NvU32 slots) // Rounded down
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
NvU64 bytes_per_timeslot = getTotalDataRate() / 64;
return (NvU32)(bytes_per_timeslot * slots/ bytes_per_pbn);
}
NvU32 PBNForSlots(NvU32 slots);
bool operator!= (const LinkConfiguration & right) const
{
@@ -536,5 +628,11 @@ namespace DisplayPort
}
};
#define IS_DP2X_UHBR_LINK_DATA_RATE(val) (((NvU32)(val) == dp2LinkRate_2_50Gbps) || \
((NvU32)(val) == dp2LinkRate_2_70Gbps && bSupportInternalUhbrOnFpga) || \
((NvU32)(val) == dp2LinkRate_5_00Gbps) || \
((NvU32)(val) == dp2LinkRate_10_0Gbps) || \
((NvU32)(val) == dp2LinkRate_13_5Gbps) || \
((NvU32)(val) == dp2LinkRate_20_0Gbps))
}
#endif //INCLUDED_DP_LINKCONFIG_H

50
src/common/displayport/inc/dp_mainlink.h
View File

@@ -67,6 +67,18 @@ namespace DisplayPort
LINK_QUAL_80BIT_CUST,
LINK_QUAL_HBR2_COMPLIANCE_EYE,
LINK_QUAL_CP2520PAT3,
LINK_QUAL_128B132B_TPS1,
LINK_QUAL_128B132B_TPS2,
LINK_QUAL_PRBS9,
LINK_QUAL_PRBS11,
LINK_QUAL_PRBS15,
LINK_QUAL_PRBS23,
LINK_QUAL_PRBS31,
LINK_QUAL_264BIT_CUST,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF,
};
typedef struct
@@ -84,6 +96,19 @@ namespace DisplayPort
int ctsmUpper;
} PatternInfo;
typedef struct
{
LinkQualityPatternType lqsPattern;
//
// DP CSTM Test Pattern data
// For 264 bits: ctsmData[0]-ctsmData[32]
// padding: ctsmData[33-35]
//
NvU8 ctsmData[36];
NvU8 sqNum;
} DP2xPatternInfo;
typedef struct
{
unsigned char bcaps;
@@ -99,10 +124,17 @@ namespace DisplayPort
FAST_LINK_TRAINING,
}LinkTrainingType;
typedef enum
{
FlushModePhase1,
FlushModePhase2,
} FlushModePhase;
class MainLink : virtual public Object
{
public:
virtual bool physicalLayerSetTestPattern(PatternInfo * patternInfo) = 0;
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo * patternInfo) = 0;
//
// Wrappers for existing link training RM control calls
//
@@ -174,7 +206,10 @@ namespace DisplayPort
virtual bool hasMultistream() = 0;
virtual bool isPC2Disabled() = 0;
virtual NvU32 getGpuDpSupportedVersions() = 0;
virtual NvU32 getUHBRSupported() {return 0;}
virtual bool isRgFlushSequenceUsed() {return false;}
virtual bool isStreamCloningEnabled() = 0;
virtual NvU32 getMinPClkForCompressed() = 0;
virtual NvU32 maxLinkRateSupported() = 0;
virtual bool isLttprSupported() = 0;
virtual bool isFECSupported() = 0;
@@ -191,9 +226,7 @@ namespace DisplayPort
virtual void triggerACT() = 0;
virtual void configureHDCPGetHDCPState(HDCPState &hdcpState) = 0;
virtual NvU32 streamToHead(NvU32 streamId,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY) = 0;
virtual NvU32 headToStream(NvU32 head,
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY) = 0;
virtual void configureSingleStream(NvU32 head,
@@ -246,6 +279,17 @@ namespace DisplayPort
virtual bool freeDisplayId(NvU32 displayId) = 0;
virtual bool queryGPUCapability() {return false;}
virtual bool queryAndUpdateDfpParams() = 0;
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 sinkUhbrCaps = 0) { return; }
virtual bool setFlushMode(FlushModePhase phase) { return false; }
virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0) { return false; }
virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data)
{
return false;
}
virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data)
{
return false;
}
virtual bool getEdpPowerData(bool *panelPowerOn, bool *bDPCDPowerStateD0) = 0;
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status) = 0;

30
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -35,7 +35,7 @@
// Regkey Names
#define NV_DP_REGKEY_OVERRIDE_DPCD_REV "OVERRIDE_DPCD_REV"
#define NV_DP_REGKEY_DISABLE_SSC "DISABLE_SSC"
#define NV_DP_REGKEY_DISABLE_SSC "DISABLE_SSC" // SSC (Stream Status Changed)
#define NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING "ENABLE_FAST_LINK_TRAINING"
#define NV_DP_REGKEY_DISABLE_MST "DISABLE_MST"
#define NV_DP_REGKEY_ENABLE_INBAND_STEREO_SIGNALING "ENABLE_INBAND_STEREO_SIGNALING"
@@ -49,6 +49,7 @@
#define NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP "HP_WAR_2189772"
#define NV_DP_REGKEY_HDCP_AUTH_ONLY_ON_DEMAND "DP_HDCP_AUTH_ONLY_ON_DEMAND"
#define NV_DP_REGKEY_ENABLE_MSA_OVER_MST "ENABLE_MSA_OVER_MST"
#define NV_DP_REGKEY_DISABLE_DOWNSPREAD "DISABLE_DOWNSPREAD"
// Keep link alive for SST and MST
#define NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE "DP_KEEP_OPT_LINK_ALIVE"
@@ -62,12 +63,31 @@
// Message to power down video stream before power down link (set D3)
#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY"
//
// Regkey to re-assess max link if the first assessed link config
// is lower than the panel max
//
#define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK"
//
// DSC capability of downstream device should be decided based on device's own
// and its parent's DSC capability.
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
//
// This regkey is controlling the if DPLib supports FPGA-specific Test UHBR.
// The link rates are for internal test only.
// This regkey is also used in RM. Both must be kept in sync.
//
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT "DP2X_FPGA_UHBR_SUPPORT"
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_5G NVBIT(0)
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_7G NVBIT(1)
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G NVBIT(2)
#define NV_DP2X_IGNORE_CABLE_ID_CAPS "DP2X_IGNORE_CABLE_ID_CAPS"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
@@ -75,6 +95,9 @@
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
// Bug 4793112 : On eDP panel, do not cache source OUI if it reads zero
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -106,8 +129,13 @@ struct DP_REGKEY_DATABASE
bool bBypassEDPRevCheck;
bool bDscMstCapBug3143315;
bool bPowerDownPhyBeforeD3;
bool bReassessMaxLink;
NvU32 supportInternalUhbrOnFpga;
bool bIgnoreCableIdCaps;
bool bMSTPCONCapsReadDisabled;
bool bForceDisableTunnelBwAllocation;
bool bDownspreadDisabled;
bool bSkipZeroOuiCache;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

43
src/common/displayport/inc/dp_watermark.h
View File

@@ -32,8 +32,6 @@
#include "displayport.h"
#define WAR_AUDIOCLAMPING_FREQ 48000 // Audio freq. more than 48KHz are currently clamped due to bug 925211
namespace DisplayPort
{
class LinkConfiguration;
@@ -46,16 +44,18 @@ namespace DisplayPort
NvU64 pixelClockHz; // Requested pixel clock for the mode
unsigned rasterWidth;
unsigned rasterHeight;
unsigned surfaceWidth; // RasterBlankStartX - newRasterBlankEndX
unsigned surfaceWidth; // RasterBlankStartX - RasterBlankEndX
unsigned surfaceHeight; // Active region height
unsigned depth;
unsigned rasterBlankStartX;
unsigned rasterBlankEndX;
unsigned bitsPerComponent; // Bits per component
bool bEnableDsc; // bEnableDsc=1 indicates DSC would be enabled for the mode
DSC_MODE mode; // DSC Mode
bool bEnablePassThroughForPCON;
DSC_MODE mode; // DSC Mode
DP_COLORFORMAT colorFormat;
ModesetInfo(): twoChannelAudioHz(0),
eightChannelAudioHz(0),
pixelClockHz(0),
@@ -68,14 +68,16 @@ namespace DisplayPort
rasterBlankEndX(0),
bitsPerComponent(0),
bEnableDsc(false),
bEnablePassThroughForPCON(false),
mode(DSC_SINGLE),
bEnablePassThroughForPCON(false) {}
colorFormat(dpColorFormat_Unknown) {}
ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz,
unsigned newRasterWidth, unsigned newRasterHeight,
unsigned newSurfaceWidth, unsigned newSurfaceHeight, unsigned newDepth,
unsigned newRasterBlankStartX=0, unsigned newRasterBlankEndX=0, bool newBEnableDsc = false,
DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false):
DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false,
DP_COLORFORMAT dpColorFormat = dpColorFormat_Unknown):
twoChannelAudioHz(newTwoChannelAudioHz),
eightChannelAudioHz(newEightChannelAudioHz),
pixelClockHz(newPixelClockHz),
@@ -88,8 +90,9 @@ namespace DisplayPort
rasterBlankEndX(newRasterBlankEndX),
bitsPerComponent(0),
bEnableDsc(newBEnableDsc),
bEnablePassThroughForPCON(newBEnablePassThroughForPCON),
mode(newMode),
bEnablePassThroughForPCON(newBEnablePassThroughForPCON) {}
colorFormat(dpColorFormat) {}
};
struct Watermark
@@ -103,43 +106,35 @@ namespace DisplayPort
bool isModePossibleSST
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo,
bool bUseIncreasedWatermarkLimits = false
);
bool isModePossibleMST
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo
);
bool isModePossibleSSTWithFEC
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo,
bool bUseIncreasedWatermarkLimits = false
);
bool isModePossibleMSTWithFEC
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo
);
bool dp2xIsModePossibleMSTWithFEC
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
Watermark * dpInfo
);
// Return Payload Bandwidth Number(PBN)for requested mode
unsigned pbnForMode(const ModesetInfo & modesetInfo);
unsigned pbnForMode(const ModesetInfo &modesetInfo);
}
#endif //INCLUDED_DP_WATERMARK_H

96
src/common/displayport/src/dp_configcaps.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,7 @@
#include "dp_auxdefs.h"
#include "dp_printf.h"
#include "displayport.h"
#include "dp_configcaps2x.h"
using namespace DisplayPort;
@@ -249,9 +250,24 @@ void DPCDHALImpl::parseAndReadCaps()
FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2, _YES, gpuDPSupportedVersions));
// First find MAX_LINK_BANDWIDTH based on MAX_LINK_BANDWIDTH registers
if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _1_62_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_1_62Gbps;
else if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _2_70_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_2_70Gbps;
else if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _5_40_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_5_40Gbps;
else if (FLD_TEST_DRF(_DPCD14, _MAX_LINK_BANDWIDTH, _VAL, _8_10_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_8_10Gbps;
else
{
DP_ASSERT(0 && "Unknown max link rate. Assuming DP 1.1 defaults");
caps.maxLinkRate = dp2LinkRate_2_70Gbps;
}
if (caps.eDpRevision >= NV_DPCD_EDP_REV_VAL_1_4 || this->bBypassILREdpRevCheck)
{
NvU16 linkRate = 0;
NvU16 maxILRLinkRate = 0;
if (getRawLinkRateTable((NvU8*)&caps.linkRateTable[0]))
{
// First entry must be non-zero for validation
@@ -260,30 +276,16 @@ void DPCDHALImpl::parseAndReadCaps()
bIndexedLinkrateCapable = true;
for (int i = 0; (i < NV_DPCD_SUPPORTED_LINK_RATES__SIZE) && caps.linkRateTable[i]; i++)
{
if (linkRate < caps.linkRateTable[i])
linkRate = caps.linkRateTable[i];
if (maxILRLinkRate < caps.linkRateTable[i])
maxILRLinkRate = caps.linkRateTable[i];
}
if (maxILRLinkRate) {
// If max ILR is higher than MAX_LINK_BANDWIDTH, then update overall maxLinkRate
caps.maxLinkRate = DP_MAX(caps.maxLinkRate, LINK_RATE_200KHZ_TO_10MHZ((NvU64)maxILRLinkRate));
}
if (linkRate)
caps.maxLinkRate = LINK_RATE_200KHZ_TO_10MHZ((NvU64)linkRate);
}
}
}
if (!bIndexedLinkrateCapable)
{
if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _1_62_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_1_62Gbps;
else if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _2_70_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_2_70Gbps;
else if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _5_40_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_5_40Gbps;
else if (FLD_TEST_DRF(_DPCD14, _MAX_LINK_BANDWIDTH, _VAL, _8_10_GBPS, buffer[1]))
caps.maxLinkRate = dp2LinkRate_8_10Gbps;
else
{
DP_ASSERT(0 && "Unknown max link rate. Assuming DP 1.1 defaults");
caps.maxLinkRate = dp2LinkRate_2_70Gbps;
}
}
//
// To prevent WAR being overridden.
@@ -364,8 +366,8 @@ void DPCDHALImpl::parseAndReadCaps()
if (bLttprSupported)
{
// Burst read from 0xF0000 to 0xF0007
if (AuxRetry::ack == bus.read(NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV, &buffer[0], 0x8, retries))
// Burst read from 0xF0000 to 0xF0009
if (AuxRetry::ack == bus.read(NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV, &buffer[0], 10, retries))
{
caps.repeaterCaps.revisionMinor = DRF_VAL(_DPCD14, _LT_TUNABLE_PHY_REPEATER_REV, _MINOR, buffer[0x0]);
caps.repeaterCaps.revisionMajor = DRF_VAL(_DPCD14, _LT_TUNABLE_PHY_REPEATER_REV, _MAJOR, buffer[0x0]);
@@ -419,6 +421,8 @@ void DPCDHALImpl::parseAndReadCaps()
caps.repeaterCaps.bFECSupportedRepeater[lttprIdx];
}
}
caps.repeaterCaps.bAuxlessALPMSupported =
FLD_TEST_DRF(_DPCD20, _PHY_REPEATER_ALPM_CAPS, _AUX_LESS, _SUPPORTED, buffer[9]);
}
else
@@ -1234,6 +1238,15 @@ AuxRetry::status DPCDHALImpl::setLinkQualPatternSet
}
}
AuxRetry::status DPCDHALImpl::setLinkQualPatternSet
(
DP2xPatternInfo& patternInfo,
unsigned laneCount
)
{
return setLinkQualPatternSet(patternInfo.lqsPattern, laneCount);
}
AuxRetry::status DPCDHALImpl::setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern)
{
NvU8 linkQuality = 0;
@@ -1298,13 +1311,14 @@ AuxRetry::status DPCDHALImpl::setMessagingEnable(bool _uprequestEnable, bool _up
if (_uprequestEnable)
{
bMultistream = FLD_TEST_DRF(_DPCD, _MSTM_CTRL, _EN, _YES, mstmCtrl);
bMultistream = caps.supportsMultistream;
}
else
{
bMultistream = false;
}
mstmCtrl = 0;
if (bMultistream)
mstmCtrl = FLD_SET_DRF(_DPCD, _MSTM_CTRL, _EN, _YES, mstmCtrl);
if (uprequestEnable)
@@ -1656,19 +1670,21 @@ void DPCDHALImpl::resetIntrLaneStatus()
void DPCDHALImpl::fetchLinkStatusESI()
{
NvU8 buffer[16] = {0};
NvS32 rxIndex;
NvU8 buffer[16] = {0};
NvS32 rxIndex;
MainLinkChannelCoding mainLinkChannelCoding = getMainLinkChannelCoding();
// LINK_STATUS_ESI from 0x200C to 0x200E
int bytesToRead = 3;
// Reset all laneStatus to true.
resetIntrLaneStatus();
for (rxIndex = caps.phyRepeaterCount; rxIndex >= (NvS32) NV0073_CTRL_DP_DATA_TARGET_SINK; rxIndex--)
{
if (rxIndex != NV0073_CTRL_DP_DATA_TARGET_SINK)
{
// Ignore LTTPR Link Status for 128b/132b
if (mainLinkChannelCoding == ChannelCoding128B132B)
continue;
readLTTPRLinkStatus(rxIndex, &buffer[0xC]);
}
else
@@ -1696,8 +1712,10 @@ void DPCDHALImpl::fetchLinkStatusESI()
void DPCDHALImpl::fetchLinkStatusLegacy()
{
NvU8 buffer[16] = {0};
NvS32 rxIndex;
NvU8 buffer[16] = {0};
NvS32 rxIndex;
MainLinkChannelCoding mainLinkChannelCoding = getMainLinkChannelCoding();
// LINK_STATUS from 0x202 to 0x204
int bytesToRead = 3;
@@ -1708,6 +1726,9 @@ void DPCDHALImpl::fetchLinkStatusLegacy()
{
if (rxIndex != NV0073_CTRL_DP_DATA_TARGET_SINK)
{
// Ignore LTTPR Link Status for 128b/132b
if (mainLinkChannelCoding == ChannelCoding128B132B)
continue;
readLTTPRLinkStatus(rxIndex, &buffer[2]);
}
else
@@ -1831,7 +1852,7 @@ bool DPCDHALImpl::setPowerState(PowerState newState)
NvU8 grant = 0;
// Grant extended sleep wake timeout before go D3.
grant = FLD_SET_DRF(_DPCD, _EXTENDED_DPRX_WAKE_TIMEOUT, _PERIOD_GRANTED, _YES, grant);
if (AuxRetry::ack == bus.write(NV_DPCD_EXTENDED_DPRX_WAKE_TIMEOUT, &grant, sizeof(grant)))
if (AuxRetry::ack != bus.write(NV_DPCD_EXTENDED_DPRX_WAKE_TIMEOUT, &grant, sizeof(grant)))
{
DP_PRINTF(DP_ERROR, "DisplayPort: Failed to grant extended sleep wake timeout before D3");
}
@@ -3037,6 +3058,15 @@ bool DPCDHALImpl::clearDpTunnelingBwAllocationCapStatus()
DPCDHAL * DisplayPort::MakeDPCDHAL(AuxBus * bus, Timer * timer, MainLink * main)
{
return new DPCDHALImpl(bus, timer);
NvU32 dpVersionsSupported = main->getGpuDpSupportedVersions();
if (FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED,
_DP2_0, _YES, dpVersionsSupported))
{
return new DPCDHALImpl2x(bus, timer);
}
else
{
return new DPCDHALImpl(bus, timer);
}
}

654
src/common/displayport/src/dp_configcaps2x.cpp Normal file
View File

@@ -0,0 +1,654 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort********************************\
* *
* Module: dp_configcaps2x.cpp *
* Abstraction for DP2x caps registers *
* *
\***************************************************************************/
#include "dp_internal.h"
#include "dp_auxbus.h"
#include "dp_auxdefs.h"
#include "displayport.h"
#include "dp_configcaps2x.h"
using namespace DisplayPort;
void DPCDHALImpl2x::performCableIdHandshake()
{
NvU8 byte = 0;
if (AuxRetry::ack ==
bus.read(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, &byte, sizeof byte))
{
caps2x.cableCaps.bUHBR_10GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_0_GBPS_SUPPORTED, byte) ||
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_AND_20_GBPS_SUPPORTED, byte);
caps2x.cableCaps.bUHBR_20GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_AND_20_GBPS_SUPPORTED, byte);
caps2x.cableCaps.bUHBR_13_5GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _13_5_GBPS_SUPPORTED, _YES, byte);
switch (DRF_VAL(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _CABLE_TYPE, byte))
{
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_CABLE_TYPE_UNKNOWN:
caps2x.cableCaps.cableType = CableTypeUnknown;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_PASSIVE:
caps2x.cableCaps.cableType = CableTypePassive;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_LRD:
caps2x.cableCaps.cableType = CableTypeLRD;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_ACTIVE_RETIMER:
caps2x.cableCaps.cableType = CableTypeActiveReTimer;
break;
default:
DP_PRINTF(DP_ERROR, "Unknown cable type\n");
break;
}
}
if (byte == 0)
{
caps2x.cableCaps.bUHBR_10GSupported = true;
return;
}
}
void DPCDHALImpl2x::parseAndReadCaps()
{
NvU8 buffer[16];
NvU8 byte = 0;
unsigned retries = 16;
DPCDHALImpl::parseAndReadCaps();
// 02206h
if (AuxRetry::ack == bus.read(NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING, &buffer[0], 1))
{
caps2x.bDP2xChannelCodingSupported = FLD_TEST_DRF(_DPCD20, _EXTENDED_MAIN_LINK_CHANNEL_CODING,
_ANSI_128B_132B, _YES,
buffer[0]);
if (caps2x.bDP2xChannelCodingSupported == true)
{
// 0x2215
if (AuxRetry::ack == bus.read(NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES, &buffer[0], 1))
{
caps2x.bUHBR_10GSupported =
FLD_TEST_DRF(_DPCD20,
_128B_132B_SUPPORTED_LINK_RATES,
_UHBR10,
_YES,
buffer[0]);
caps2x.bUHBR_13_5GSupported =
FLD_TEST_DRF(_DPCD20,
_128B_132B_SUPPORTED_LINK_RATES,
_UHBR13_5,
_YES,
buffer[0]);
caps2x.bUHBR_20GSupported =
FLD_TEST_DRF(_DPCD20,
_128B_132B_SUPPORTED_LINK_RATES,
_UHBR20,
_YES,
buffer[0]);
}
DP_ASSERT(caps2x.bUHBR_10GSupported && "Failed to read UHBR link rates or 128B/132B supported without UHBR10");
if (AuxRetry::ack == bus.read(NV_DPCD14_FEC_CAPABILITY, &buffer[0], 1))
{
caps.bFECSupported = FLD_TEST_DRF(_DPCD14, _FEC_CAPABILITY,
_FEC_CAPABLE,
_YES,
buffer[0]);
}
DP_ASSERT(caps.bFECSupported && "Failed to read FEC Capability or 128B/132B supported without FEC");
}
else
{
caps2x.bUHBR_10GSupported = NV_FALSE;
caps2x.bUHBR_13_5GSupported = NV_FALSE;
caps2x.bUHBR_20GSupported = NV_FALSE;
}
}
if (bLttprSupported)
{
if (AuxRetry::ack == bus.read(NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV, &buffer[0], 0x8, retries))
{
caps2x.repeaterCaps.bDP2xChannelCodingSupported =
FLD_TEST_DRF(_DPCD20,
_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING,
_128B_132B_SUPPORTED,
_YES,
buffer[6]);
caps2x.repeaterCaps.bUHBR_10GSupported =
FLD_TEST_DRF(_DPCD20,
_PHY_REPEATER_128B_132B_RATES,
_10G_SUPPORTED,
_YES,
buffer[7]);
caps2x.repeaterCaps.bUHBR_13_5GSupported =
FLD_TEST_DRF(_DPCD20,
_PHY_REPEATER_128B_132B_RATES,
_13_5G_SUPPORTED,
_YES,
buffer[7]);
caps2x.repeaterCaps.bUHBR_20GSupported =
FLD_TEST_DRF(_DPCD20,
_PHY_REPEATER_128B_132B_RATES,
_20G_SUPPORTED,
_YES,
buffer[7]);
if (buffer[7] && !caps2x.repeaterCaps.bDP2xChannelCodingSupported)
{
DP_ASSERT(0 && "LTTPR: UHBR is supported without 128b/132b Channel Encoding Supported!");
}
if (caps2x.repeaterCaps.bDP2xChannelCodingSupported)
{
DP_ASSERT(caps.repeaterCaps.bFECSupported &&
"LTTPR: UHBR is supported without FEC Support!");
}
}
}
if (!bIgnoreCableIdCaps)
{
performCableIdHandshake();
}
if (caps.dpInTunnelingCaps.bIsSupported)
{
if (AuxRetry::ack ==
bus.read(NV_DPCD20_DP_TUNNELING_MAIN_LINK_CHANNEL_CODING, &byte, sizeof byte))
{
caps2x.dpInTunnelingCaps.bDP2xChannelCodingSupported =
FLD_TEST_DRF(_DPCD20, _DP_TUNNELING_128B132B,
_DP_SUPPORTED, _YES, byte);
}
}
if (caps2x.dpInTunnelingCaps.bDP2xChannelCodingSupported)
{
if (AuxRetry::ack ==
bus.read(NV_DPCD20_DP_TUNNELING_MAIN_LINK_CHANNEL_CODING, &byte, sizeof byte))
{
caps2x.dpInTunnelingCaps.bUHBR_10GSupported =
FLD_TEST_DRF(_DPCD20, _DP_TUNNELING_128B132B_LINK_RATES, _10_0_GPBS_SUPPORTED, _YES, byte);
caps2x.dpInTunnelingCaps.bUHBR_13_5GSupported =
FLD_TEST_DRF(_DPCD20, _DP_TUNNELING_128B132B_LINK_RATES, _13_5_GPBS_SUPPORTED, _YES, byte);
caps2x.dpInTunnelingCaps.bUHBR_20GSupported =
FLD_TEST_DRF(_DPCD20, _DP_TUNNELING_128B132B_LINK_RATES, _20_0_GPBS_SUPPORTED, _YES, byte);
}
}
}
void DPCDHALImpl2x::setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions)
{
bool bSupportDp1_2 = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2,
_YES, _gpuDPSupportedVersions);
bool bSupportDp1_4 = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_4,
_YES, _gpuDPSupportedVersions);
bool bSupportDp2_0 = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP2_0,
_YES, _gpuDPSupportedVersions);
if (bSupportDp2_0)
{
DP_ASSERT(bSupportDp1_4 && bSupportDp1_2 && "GPU supports DP1.4 should also support DP1.4 and DP1.2!");
}
return DPCDHALImpl::setGpuDPSupportedVersions(_gpuDPSupportedVersions);
}
AuxRetry::status DPCDHALImpl2x::notifySDPErrDetectionCapability()
{
NvU8 config = 0;
AuxRetry::status status = AuxRetry::ack;
if (!FLD_TEST_DRF(0073_CTRL_CMD_DP,
_GET_CAPS_DP_VERSIONS_SUPPORTED,
_DP2_0, _YES, gpuDPSupportedVersions))
{
// If the GPU does not support DP2.0 features, don't do anything.
return status;
}
if (!isAtLeastVersion(1, 4) || !(caps2x.bDP2xChannelCodingSupported))
{
//
// If the root device is less then DP1.4 or does not support 128b/132b channel encoding,
// don't do anything.
//
return status;
}
if ((caps.phyRepeaterCount != 0) &&
(!caps2x.repeaterCaps.bDP2xChannelCodingSupported))
{
// If there are LTTPRs that does not support 128b/132b channel encoding, don't do anything.
return status;
}
config = FLD_SET_DRF(_DPCD20, _SDP_ERR_DETECTION_CONF, _CRC16_128B_132B_SUPPORTED,
_YES, config);
status = bus.write(NV_DPCD20_SDP_ERR_DETECTION_CONF, &config, sizeof(config));
if (AuxRetry::ack != status)
{
DP_PRINTF(DP_WARNING, "Failed to write NV_DPCD20_SDP_ERR_DETECTION_CONF");
}
return status;
}
bool DPCDHALImpl2x::isDp2xChannelCodingCapable()
{
// return false if the device does not support 128b/132b.
if (!caps2x.bDP2xChannelCodingSupported)
return false;
// return false if DP-IN Tunneling is supported but not support 128b/132b.
if (caps.dpInTunnelingCaps.bIsSupported && !caps2x.dpInTunnelingCaps.bDP2xChannelCodingSupported)
return false;
// return true if there is no LTTPR.
if (!bLttprSupported || (caps.phyRepeaterCount == 0))
return true;
// If there is any LTTPR, return false if any of the LTTPR does not support 128b/132b
if (!caps2x.repeaterCaps.bDP2xChannelCodingSupported || !lttprIsAtLeastVersion(2, 0))
{
// If there are LTTPRs that does not support 128b/132b channel encoding, it's not DP2x capable.
return false;
}
return true;
}
//
// Legacy link rates: DPCD offset 1 * 27000000
// ILRs: DPCD offset: 0x10~0x1F
// UHBR sink: DPCD offset: 0x2215
// LTTPR: DPCD offset: 0xF0007
//
LinkRate DPCDHALImpl2x::getMaxLinkRate()
{
LinkRate maxLinkRate = DPCDHALImpl::getMaxLinkRate();
NvU32 uhbrCaps = getUHBRSupported();
bool bDP2xChannelCodingSupported = isDp2xChannelCodingCapable();
if (bDP2xChannelCodingSupported)
{
if(FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_UHBR_SUPPORTED, _UHBR10_0, _YES, uhbrCaps))
{
maxLinkRate = dp2LinkRate_10_0Gbps;
}
if(FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_UHBR_SUPPORTED, _UHBR13_5, _YES, uhbrCaps))
{
maxLinkRate = dp2LinkRate_13_5Gbps;
}
if(FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_UHBR_SUPPORTED, _UHBR20_0, _YES, uhbrCaps))
{
maxLinkRate = dp2LinkRate_20_0Gbps;
}
}
return maxLinkRate;
}
//
// The function checks for sink side UHBR capabilities as a combination of
// a. Sink Caps.
// b. Cable ID Caps
// c. LTTPR Caps.
// d. DP Tunneling Caps.
//
NvU32 DPCDHALImpl2x::getUHBRSupported()
{
NvU32 uhbrCaps = 0;
bool bUHBR_10GSupported = caps2x.bUHBR_10GSupported;
bool bUHBR_13_5GSupported = caps2x.bUHBR_13_5GSupported;
bool bUHBR_20GSupported = caps2x.bUHBR_20GSupported;
if (!bIgnoreCableIdCaps)
{
bUHBR_10GSupported = bUHBR_10GSupported && caps2x.cableCaps.bUHBR_10GSupported;
bUHBR_13_5GSupported = bUHBR_13_5GSupported && caps2x.cableCaps.bUHBR_13_5GSupported;
bUHBR_20GSupported = bUHBR_20GSupported && caps2x.cableCaps.bUHBR_20GSupported;
}
if (caps.phyRepeaterCount > 0)
{
bUHBR_10GSupported = bUHBR_10GSupported && caps2x.repeaterCaps.bUHBR_10GSupported;
bUHBR_13_5GSupported = bUHBR_13_5GSupported && caps2x.repeaterCaps.bUHBR_13_5GSupported;
bUHBR_20GSupported = bUHBR_20GSupported && caps2x.repeaterCaps.bUHBR_20GSupported;
}
if (caps.dpInTunnelingCaps.bIsSupported && bIsDpTunnelBwAllocationEnabled)
{
bUHBR_10GSupported = bUHBR_10GSupported && caps2x.dpInTunnelingCaps.bUHBR_10GSupported;
bUHBR_13_5GSupported = bUHBR_13_5GSupported && caps2x.dpInTunnelingCaps.bUHBR_13_5GSupported;
bUHBR_20GSupported = bUHBR_20GSupported && caps2x.dpInTunnelingCaps.bUHBR_20GSupported;
}
if (bUHBR_10GSupported)
{
uhbrCaps = FLD_SET_DRF(0073_CTRL_CMD_DP, _GET_CAPS_UHBR_SUPPORTED, _UHBR10_0, _YES, uhbrCaps);
}
if (bUHBR_13_5GSupported)
{
uhbrCaps = FLD_SET_DRF(0073_CTRL_CMD_DP, _GET_CAPS_UHBR_SUPPORTED, _UHBR13_5, _YES, uhbrCaps);
}
if (bUHBR_20GSupported)
{
uhbrCaps = FLD_SET_DRF(0073_CTRL_CMD_DP, _GET_CAPS_UHBR_SUPPORTED, _UHBR20_0, _YES, uhbrCaps);
}
return uhbrCaps;
}
bool DPCDHALImpl2x::parseTestRequestPhy()
{
NvU8 buffer[2] = {0};
if (AuxRetry::ack != bus.read(NV_DPCD20_PHY_TEST_PATTERN, &buffer[0], 2))
{
DP_PRINTF(DP_ERROR, "DPHAL> ERROR! Test pattern request found but unable to read NV_DPCD20_PHY_TEST_PATTERN register.");
return false;
}
switch (DRF_VAL(_DPCD20, _PHY_TEST_PATTERN_SEL, _DP20, buffer[0]))
{
case NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS1:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_128B132B_TPS1;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS2:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_128B132B_TPS2;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS9:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_PRBS9;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS11:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_PRBS11;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS15:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_PRBS15;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS23:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_PRBS23;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS31:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_PRBS31;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_264_BIT_CUSTOM:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_264BIT_CUST;
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON;
interrupts2x.testPhyCompliance2x.sqNum = buffer[1];
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON;
interrupts2x.testPhyCompliance2x.sqNum = buffer[1];
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF;
interrupts2x.testPhyCompliance2x.sqNum = buffer[1];
break;
case NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF:
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF;
interrupts2x.testPhyCompliance2x.sqNum = buffer[1];
break;
default:
// now look for DP1.X test patterns
interrupts2x.testPhyCompliance2x.phyTestPattern = LINK_QUAL_DISABLED;
return DPCDHALImpl::parseTestRequestPhy();
}
if (interrupts2x.testPhyCompliance2x.phyTestPattern == LINK_QUAL_264BIT_CUST)
{
if (AuxRetry::ack != bus.read(NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN(0),
&(interrupts2x.cstm264Bits[0]),
NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN__SIZE))
{
DP_PRINTF(DP_ERROR, "DPHAL> ERROR! Request for 264bit custom pattern. Can't read from 0x%08xh.",
NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN(0));
return false;
}
}
// copy the parsed interrupt info to parent struct
interrupts.testPhyCompliance.phyTestPattern = interrupts2x.testPhyCompliance2x.phyTestPattern;
interrupts2x.testPhyCompliance2x.testRequestPhyCompliance = true;
return true;
}
bool DPCDHALImpl2x::parseTestRequestTraining(NvU8 * buffer)
{
if (buffer == NULL)
{
DP_ASSERT(0 && "Buffer invalid, bail out");
return false;
}
// 0x218, bit 4
bool bDP2xChannelCodingRequested = FLD_TEST_DRF(_DPCD20, _TEST_REQUEST,
_PHY_TEST_CHANNEL_CODING, _128B132B, buffer[0]);
if (!bDP2xChannelCodingRequested)
return DPCDHALImpl::parseTestRequestTraining(buffer);
// 0x219
switch (buffer[1])
{
case NV_DPCD20_TEST_LINK_RATE_TYPE_20_0G:
interrupts.testTraining.testRequestLinkRate = dp2LinkRate_20_0Gbps;
break;
case NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G:
case NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G_2:
interrupts.testTraining.testRequestLinkRate = dp2LinkRate_13_5Gbps;
break;
case NV_DPCD20_TEST_LINK_RATE_TYPE_10_0G:
interrupts.testTraining.testRequestLinkRate = dp2LinkRate_10_0Gbps;
break;
default:
interrupts.testTraining.testRequestLinkRate = dp2LinkRate_10_0Gbps;
DP_ASSERT(0 && "Unknown requested link rate. Assuming UHBR10");
break;
}
// 0x220.
interrupts.testTraining.testRequestLaneCount = buffer[(0x220 - 0x218)] & 0xf;
return true;
}
void DPCDHALImpl2x::get264BitsCustomTestPattern(NvU8 *testPattern)
{
int i;
for (i = 0; i < NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN__SIZE; i++)
{
testPattern[i] = interrupts2x.cstm264Bits[i];
}
}
void DPCDHALImpl2x::getSquarePatternNum(NvU8 *sqNum)
{
if (sqNum != NULL)
{
*sqNum = interrupts2x.testPhyCompliance2x.sqNum;
}
return;
}
AuxRetry::status DPCDHALImpl2x::setLinkQualPatternSet
(
DP2xPatternInfo& patternInfo,
unsigned laneCount
)
{
unsigned writeAddr = NV_DPCD20_LINK_SQUARE_PATTERN_NUM_PLUS_1;
if ((patternInfo.lqsPattern == LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON) ||
(patternInfo.lqsPattern == LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON) ||
(patternInfo.lqsPattern == LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF) ||
(patternInfo.lqsPattern == LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF))
{
if (AuxRetry::ack != bus.write(writeAddr, &(patternInfo.sqNum), sizeof (patternInfo.sqNum)))
{
DP_ASSERT(0 && "Could not set LINK_SQUARE_PATTERN_NUM_PLUS_1");
}
}
return DPCDHALImpl::setLinkQualPatternSet(patternInfo.lqsPattern, laneCount);
}
AuxRetry::status DPCDHALImpl2x::setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern)
{
NvU8 linkQuality = 0;
unsigned writeAddress = NV_DPCD20_LINK_QUAL_LANE_SET(lane);
if (caps.revisionMajor <= 0)
DP_ASSERT(0 && "Something is wrong, revision major should be > 0");
if (isAtLeastVersion(1, 2) == false)
{
DP_ASSERT(0 && "Regs only supported for DP1.2");
return AuxRetry::unsupportedRegister;
}
// check if parameter is valid
if (lane >= displayPort_LaneSupported)
{
DP_ASSERT(0 && "Unknown lane selected. Assuming Lane 0");
writeAddress = NV_DPCD20_LINK_QUAL_LANE_SET(0);
}
switch (linkQualPattern)
{
case LINK_QUAL_DISABLED:
linkQuality = FLD_SET_DRF(_DPCD, _LINK_QUAL_LANE_SET, _LQS, _NO, linkQuality);
break;
case LINK_QUAL_D10_2:
linkQuality = FLD_SET_DRF(_DPCD, _LINK_QUAL_LANE_SET, _LQS, _D10_2, linkQuality);
break;
case LINK_QUAL_SYM_ERROR:
linkQuality = FLD_SET_DRF(_DPCD, _LINK_QUAL_LANE_SET, _LQS, _SYM_ERR_MEASUREMENT_CNT, linkQuality);
break;
case LINK_QUAL_PRBS7:
linkQuality = FLD_SET_DRF(_DPCD, _LINK_QUAL_LANE_SET, _LQS, _PRBS7, linkQuality);
break;
case LINK_QUAL_80BIT_CUST:
linkQuality = FLD_SET_DRF(_DPCD, _LINK_QUAL_LANE_SET, _LQS, _80_BIT_CUSTOM, linkQuality);
break;
case LINK_QUAL_HBR2_COMPLIANCE_EYE:
linkQuality = FLD_SET_DRF(_DPCD, _LINK_QUAL_LANE_SET, _LQS, _HBR2, linkQuality);
break;
case LINK_QUAL_CP2520PAT3:
linkQuality = FLD_SET_DRF(_DPCD14, _LINK_QUAL_LANE_SET, _LQS, _CP2520PAT3, linkQuality);
break;
case LINK_QUAL_128B132B_TPS1:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _128B132B_TPS1, linkQuality);
break;
case LINK_QUAL_128B132B_TPS2:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _128B132B_TPS2, linkQuality);
break;
case LINK_QUAL_PRBS9:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _PRBS9, linkQuality);
break;
case LINK_QUAL_PRBS11:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _PRBS11, linkQuality);
break;
case LINK_QUAL_PRBS15:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _PRBS15, linkQuality);
break;
case LINK_QUAL_PRBS23:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _PRBS23, linkQuality);
break;
case LINK_QUAL_PRBS31:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _PRBS31, linkQuality);
break;
case LINK_QUAL_264BIT_CUST:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _264_BIT_CUSTOM, linkQuality);
break;
case LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON, linkQuality);
break;
case LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON, linkQuality);
break;
case LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF, linkQuality);
break;
case LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF:
linkQuality = FLD_SET_DRF(_DPCD20, _LINK_QUAL_LANE_SET, _LQS, _SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF, linkQuality);
break;
}
return bus.write(writeAddress, &linkQuality, sizeof linkQuality);
}
AuxRetry::status DPCDHALImpl2x::setMainLinkChannelCoding(MainLinkChannelCoding channelCoding)
{
NvU8 channelCodingSet = 0;
switch (channelCoding)
{
case ChannelCoding8B10B:
channelCodingSet = FLD_SET_DRF(_DPCD, _MAIN_LINK_CHANNEL_CODING_SET, _ANSI_8B_10B, _TRUE, channelCodingSet);
break;
case ChannelCoding128B132B:
channelCodingSet = FLD_SET_DRF(_DPCD, _MAIN_LINK_CHANNEL_CODING_SET, _ANSI_128B_132B, _TRUE, channelCodingSet);
break;
}
return bus.write(NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET, &channelCodingSet , sizeof channelCodingSet);
}
MainLinkChannelCoding DPCDHALImpl2x::getMainLinkChannelCoding()
{
NvU8 channelCodingSet = 0;
if (!isDp2xChannelCodingCapable())
return ChannelCoding8B10B;
if (AuxRetry::ack != bus.read(NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET, &channelCodingSet , sizeof channelCodingSet))
return ChannelCoding8B10B;
if (FLD_TEST_DRF(_DPCD, _MAIN_LINK_CHANNEL_CODING_SET, _ANSI_128B_132B, _TRUE, channelCodingSet))
return ChannelCoding128B132B;
return ChannelCoding8B10B;
}

762
src/common/displayport/src/dp_connectorimpl.cpp
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1670
src/common/displayport/src/dp_connectorimpl2x.cpp Normal file
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File diff suppressed because it is too large Load Diff

370
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1615,6 +1615,41 @@ bool DeviceImpl::isPanelReplaySupported()
return prCaps.bPanelReplaySupported;
}
NvBool DeviceImpl::isSelectiveUpdateSupported()
{
return prCaps.bSelUpdateSupported;
}
NvBool DeviceImpl::isEarlyRegionTpSupported()
{
return prCaps.bEarlyRegionTpSupported;
}
NvBool DeviceImpl::isAdaptiveSyncSdpNotSupportedInPr()
{
return prCaps.bAdaptiveSyncSdpNotSupportedInPr;
}
NvBool DeviceImpl::isdscDecodeNotSupportedInPr()
{
return prCaps.bDscDecodeNotSupportedInPr;
}
NvBool DeviceImpl::isLinkOffSupportedAfterAsSdpInPr()
{
return prCaps.bLinkOffSupportAfterAsSdpSent;
}
SelectiveUpdateCaps DeviceImpl::getSelectiveUpdateCaps()
{
return prCaps.suCaps;
}
NvBool DeviceImpl::isAuxLessAlpmSupported()
{
return alpmCaps.bAuxLessAlpmSupported;
}
void DeviceImpl::getPanelReplayCaps()
{
NvU8 buffer[10] = {0U};
@@ -1629,6 +1664,83 @@ void DeviceImpl::getPanelReplayCaps()
prCaps.bPanelReplaySupported =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY, _SUPPORTED,
_YES, buffer[0]);
prCaps.bSelUpdateSupported =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY, _SEL_UPDATE,
_YES, buffer[0]);
prCaps.bEarlyRegionTpSupported =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY, _EARLY_TRANSPORT,
_YES, buffer[0]);
size = 1U;
// Check Additional Panel replay caps register
if (AuxBus::success == this->getDpcdData(NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD,
&buffer[1], size, &sizeCompleted, &nakReason))
{
prCaps.bDscDecodeNotSupportedInPr =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY_ADD,
_DSC_DECODE_NOT_SUPPORTED_IN_PR, _YES, buffer[1]);
prCaps.bAdaptiveSyncSdpNotSupportedInPr =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY_ADD,
_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR, _YES, buffer[1]);
prCaps.bLinkOffSupportAfterAsSdpSent =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY_ADD,
_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP, _YES, buffer[1]);
prCaps.suCaps.bDscCrcOfMultipleSuSupported =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY_ADD,
_DSC_CRC_MULTIPLE_SUS_SUPPORTED, _YES, buffer[1]);
prCaps.suCaps.bSelUpdateGranularityNeeded =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY_ADD,
_PR_SEL_UPDATE_GRANULARITY_NEEDED, _YES, buffer[1]);
if (prCaps.suCaps.bSelUpdateGranularityNeeded)
{
size = 3U;
if (AuxBus::success ==
this->getDpcdData(NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY,
&buffer[2], size, &sizeCompleted, &nakReason))
{
prCaps.suCaps.selUpdateXGranularityCap = DRF_VAL(_DPCD20_PANEL, _REPLAY_SU_X_GRANULARITY,
_CAPABILITY_VAL, buffer[2]);
prCaps.suCaps.selUpdateXGranularityCap1 = DRF_VAL(_DPCD20_PANEL, _REPLAY_SU_X,
_GRANULARITY_CAPABILITY1_VAL, buffer[3]);
prCaps.suCaps.selUpdateYGranularityCap = DRF_VAL(_DPCD20_PANEL, _REPLAY_SU_Y,
_GRANULARITY_CAPABILITY_VAL, buffer[4]);
}
else
{
DP_PRINTF(DP_ERROR, "DP-DEV> Aux Read to DPCD offset 0xB2-0xB4 failed!");
}
}
prCaps.suCaps.bSuYGranularityExtendedCap =
FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CAPABILITY_ADD,
_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED, _YES, buffer[1]);
if (prCaps.suCaps.bSuYGranularityExtendedCap)
{
size = 2U;
if (AuxBus::success ==
this->getDpcdData(NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY,
&buffer[5], size, &sizeCompleted, &nakReason))
{
prCaps.suCaps.selUpdateYGranularityExtCap = DRF_VAL(_DPCD20_PANEL, _REPLAY_SU_Y,
_GRANULARITY_EXTENDED_CAPABILITY_VAL, buffer[5]);
prCaps.suCaps.selUpdateYGranularityExtCap1 = DRF_VAL(_DPCD20_PANEL, _REPLAY_SU_Y,
_GRANULARITY_EXTENDED_CAPABILITY1_VAL, buffer[6]);
}
else
{
DP_PRINTF(DP_ERROR, "DP-DEV> Aux Read to DPCD offset 0xB5 failed!");
}
}
}
else
{
DP_PRINTF(DP_ERROR, "DP-DEV> Aux Read to DPCD offset 0xB1 failed!");
}
}
else
{
@@ -1708,6 +1820,28 @@ bool DeviceImpl::setPanelReplayConfig(panelReplayConfig prcfg)
_HPD_RFB_ACTIVE_FRAME_CRC_ERROR, _NO, config);
}
if (prcfg.bEnableSelectiveUpdate)
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION,
_ENABLE_SELECTIVE_UPDATE, _YES, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION,
_ENABLE_SELECTIVE_UPDATE, _NO, config);
}
if (prcfg.bSuRegionEarlyTpEnable)
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION,
_ENABLE_SU_REGION_EARLY_TRANSPORT, _YES, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION,
_ENABLE_SU_REGION_EARLY_TRANSPORT, _NO, config);
}
if (AuxBus::success !=
this->setDpcdData(NV_DPCD20_PANEL_REPLAY_CONFIGURATION,
&config, sizeof(config), &size, &nakReason))
@@ -1715,6 +1849,61 @@ bool DeviceImpl::setPanelReplayConfig(panelReplayConfig prcfg)
return false;
}
config = 0U;
if (prcfg.bSinkRrUnlockGranted)
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SINK_RR_UNLOCK_GRANTED, _YES, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SINK_RR_UNLOCK_GRANTED, _NO, config);
}
if (prcfg.bSelUpdateYExtValEnable)
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_Y_GRANULARITY_EXTENDED_VALUE, _YES, config);
config = FLD_SET_DRF_NUM(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_Y_GRANULARITY_EXTENDED_VALUE_SELECTION, prcfg.selUpdateYExtVal, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_Y_GRANULARITY_EXTENDED_VALUE, _NO, config);
}
if (prcfg.bSuRegionScanLineIndicate)
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_REGION_SCANLINE_CAPTURE_INDICATION, _YES, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_REGION_SCANLINE_CAPTURE_INDICATION, _NO, config);
}
if (AuxBus::success !=
this->setDpcdData(NV_DPCD20_PANEL_REPLAY_CONFIGURATION2,
&config, sizeof(config), &size, &nakReason))
{
return false;
}
config = 0U;
config = FLD_SET_DRF_NUM(_DPCD20_PANEL, _REPLAY_CONFIGURATION3,
_AS_SDP_SETUP_CONFIG_PR_ACTIVE_TIME, prcfg.asSdpSetUpTimePrActive, config);
if (AuxBus::success !=
this->setDpcdData(NV_DPCD20_PANEL_REPLAY_CONFIGURATION3,
&config, sizeof(config), &size, &nakReason))
{
return false;
}
return true;
}
@@ -1750,6 +1939,41 @@ bool DeviceImpl::getPanelReplayConfig(panelReplayConfig *pPrcfg)
_HPD_RFB_ACTIVE_FRAME_CRC_ERROR, _YES, config);
pPrcfg->bEnableSelectiveUpdate = FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION,
_ENABLE_SELECTIVE_UPDATE, _YES, config);
pPrcfg->bSuRegionEarlyTpEnable = FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION,
_ENABLE_SU_REGION_EARLY_TRANSPORT, _YES, config);
if (AuxBus::success !=
this->getDpcdData(NV_DPCD20_PANEL_REPLAY_CONFIGURATION2,
&config, sizeof(config), &size, &nakReason))
{
return false;
}
pPrcfg->bSinkRrUnlockGranted = FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SINK_RR_UNLOCK_GRANTED, _YES, config);
pPrcfg->bSelUpdateYExtValEnable = FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_Y_GRANULARITY_EXTENDED_VALUE, _YES, config);
pPrcfg->selUpdateYExtVal = DRF_VAL(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_Y_GRANULARITY_EXTENDED_VALUE_SELECTION, config);
pPrcfg->bSuRegionScanLineIndicate = FLD_TEST_DRF(_DPCD20_PANEL, _REPLAY_CONFIGURATION2,
_SU_REGION_SCANLINE_CAPTURE_INDICATION, _YES, config);
if (AuxBus::success !=
this->getDpcdData(NV_DPCD20_PANEL_REPLAY_CONFIGURATION3,
&config, sizeof(config), &size, &nakReason))
{
return false;
}
pPrcfg->asSdpSetUpTimePrActive = DRF_VAL(_DPCD20_PANEL, _REPLAY_CONFIGURATION3,
_AS_SDP_SETUP_CONFIG_PR_ACTIVE_TIME, config);
return true;
}
@@ -1792,6 +2016,152 @@ bool DeviceImpl::getPanelReplayStatus(PanelReplayStatus *pPrStatus)
return false;
}
void DeviceImpl::getAlpmCaps()
{
NvU8 byte = 0U;
unsigned size = 0U;
unsigned nakReason = NakUndefined;
if (AuxBus::success ==
this->getDpcdData(NV_DPCD20_RECEIVER_ALPM_CAPABILITIES,
&byte, sizeof(byte), &size, &nakReason))
{
alpmCaps.bFwStandbySupported =
FLD_TEST_DRF(_DPCD20_RECEIVER, _ALPM_CAPABILITIES,
_FW_STANDBY_SUPPORT, _YES, byte);
alpmCaps.bAuxLessAlpmSupported =
FLD_TEST_DRF(_DPCD20_RECEIVER, _ALPM_CAPABILITIES,
_AUX_LESS_ALPM_CAP, _YES, byte);
alpmCaps.bAuxLessAlpmPhySleepSupported =
FLD_TEST_DRF(_DPCD20_RECEIVER, _ALPM_CAPABILITIES,
_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT, _YES, byte);
}
else
{
DP_PRINTF(DP_ERROR, "DP-DEV> Aux Read to DPCD offset 0x2E failed!");
}
}
NvBool DeviceImpl::setAlpmConfig(AlpmConfig alpmCfg)
{
NvU8 config = 0U;
unsigned size = 0U;
unsigned nakReason = NakUndefined;
if (alpmCfg.bEnableAlpm)
{
config = FLD_SET_DRF(_DPCD20_RECEIVER, _ALPM_CONFIGURATION,
_ENABLE_ALPM, _YES, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_RECEIVER, _ALPM_CONFIGURATION,
_ENABLE_ALPM, _NO, config);
}
if (alpmCfg.bHpdOnAlpmLockError)
{
config = FLD_SET_DRF(_DPCD20_RECEIVER, _ALPM_CONFIGURATION,
_IRQ_HPD_ON_ALPM_LOCK_ERROR, _YES, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_RECEIVER, _ALPM_CONFIGURATION,
_IRQ_HPD_ON_ALPM_LOCK_ERROR, _NO, config);
}
if (alpmCfg.bSelectedAlpmMode)
{
config = FLD_SET_DRF(_DPCD20_RECEIVER, _ALPM_CONFIGURATION,
_ALPM_SELECTED_MODE, _AUX_LESS_ALPM, config);
}
if (alpmCfg.bAcdsPeriodDuration)
{
config = FLD_SET_DRF(_DPCD20_RECEIVER, _ALPM_CONFIGURATION,
_ACDS_PERIOD_DURATION, _YES, config);
}
else
{
config = FLD_SET_DRF(_DPCD20_RECEIVER, _ALPM_CONFIGURATION,
_ACDS_PERIOD_DURATION, _NO, config);
}
if (AuxBus::success ==
this->setDpcdData(NV_DPCD20_RECEIVER_ALPM_CONFIGURATION,
&config, sizeof(config), &size, &nakReason))
{
return true;
}
return false;
}
NvBool DeviceImpl::getAlpmStatus(AlpmStatus *pAlpmStatus)
{
NvU8 byte = 0U;
unsigned size = 0U;
unsigned nakReason = NakUndefined;
if (pAlpmStatus == NULL)
{
DP_ASSERT(0);
return false;
}
if (AuxBus::success == this->getDpcdData(NV_DPCD20_RECEIVER_ALPM_STATUS,
&byte, sizeof(byte), &size, &nakReason))
{
pAlpmStatus->bAuxlessAlpmLockTimeout =
FLD_TEST_DRF(_DPCD20_RECEIVER, _ALPM_STATUS,
_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR, _YES, byte);
pAlpmStatus->bAuxlessAlpmPhySleepDetected =
FLD_TEST_DRF(_DPCD20_RECEIVER, _ALPM_STATUS,
_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED, _YES, byte);
return true;
}
return false;
}
NvBool DeviceImpl::enableAdaptiveSyncSdp(NvBool bEnable)
{
NvU8 byte = 0U;
unsigned size = 0U;
unsigned nakReason = NakUndefined;
AuxBus::status status;
status = this->getDpcdData(NV_DPCD_DOWNSPREAD_CTRL,
&byte, sizeof byte, &size, &nakReason);
if (status == AuxBus::success)
{
if (bEnable)
{
byte = FLD_SET_DRF(_DPCD, _DOWNSPREAD_CTRL,
_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE, _YES, byte);
}
else
{
byte = FLD_SET_DRF(_DPCD, _DOWNSPREAD_CTRL,
_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE, _NO, byte);
}
status = this->setDpcdData(NV_DPCD_DOWNSPREAD_CTRL,
&byte, sizeof byte, &size, &nakReason);
if (status != AuxBus::success)
{
DP_PRINTF(DP_ERROR, "DP-DEV> Aux Write to DPCD offset 0x107 failed!");
return status;
}
}
else
{
DP_PRINTF(DP_ERROR, "DP-DEV> Aux Read to DPCD offset 0x107 failed!");
return status;
}
return true;
}
bool DeviceImpl::getFECSupport()
{
NvU8 byte = 0;

89
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -40,6 +40,9 @@
#include <ctrl/ctrl0073/ctrl0073system.h>
#include <ctrl/ctrl5070/ctrl5070or.h>
#include "displayport2x.h"
#include "dp_evoadapter2x.h"
using namespace DisplayPort;
//
@@ -93,8 +96,13 @@ const struct
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT, &dpRegkeyDatabase.supportInternalUhbrOnFpga, DP_REG_VAL_U32},
{NV_DP2X_IGNORE_CABLE_ID_CAPS, &dpRegkeyDatabase.bIgnoreCableIdCaps, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
@@ -237,17 +245,8 @@ bool EvoMainLink::getEdpPowerData(bool *panelPowerOn, bool *dpcdPowerStateD0)
}
}
NvU32 EvoMainLink::streamToHead(NvU32 streamId, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier)
{
NvU32 headIndex = 0;
NvU32 maxHeads = allHeadMask;
NUMSETBITS_32(maxHeads);
headIndex = DP_MST_STREAMID_TO_HEAD(streamId, streamIdentifier, maxHeads);
return headIndex;
}
NvU32 EvoMainLink::headToStream(NvU32 head, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier)
NvU32 EvoMainLink::headToStream(NvU32 head, bool bSidebandMessageSupported,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier)
{
NvU32 streamIndex = 0;
@@ -283,6 +282,8 @@ bool EvoMainLink::queryGPUCapability()
_gpuSupportedDpVersions = dpParams.dpVersionsSupported;
_minPClkForCompressed = dpParams.minPClkForCompressed;
if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _1_62, dpParams.maxLinkRate))
_maxLinkRateSupportedGpu = dp2LinkRate_1_62Gbps; // in 10Mbps
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _2_70, dpParams.maxLinkRate))
@@ -912,6 +913,7 @@ void EvoMainLink::applyRegkeyOverrides()
_applyLinkBwOverrideWarRegVal = dpRegkeyDatabase.bLinkBwOverrideWarApplied;
_enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled;
_isMSTPCONCapsReadDisabled = dpRegkeyDatabase.bMSTPCONCapsReadDisabled;
_isDownspreadDisabledByRegkey = dpRegkeyDatabase.bDownspreadDisabled;
}
NvU32 EvoMainLink::getRegkeyValue(const char *key)
@@ -1029,7 +1031,7 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
targetIndex = phyRepeaterCount;
}
if (!this->isDownspreadSupported())
if (!this->isDownspreadSupported() || link.bDisableDownspread || _isDownspreadDisabledByRegkey)
{
// If GPU does not support downspread, disabling downspread.
dpCtrlCmd |= DRF_DEF(0073_CTRL, _DP_CMD, _USE_DOWNSPREAD_SETTING, _FORCE);
@@ -1069,6 +1071,7 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
case dp2LinkRate_3_24Gbps:
case dp2LinkRate_4_32Gbps:
case dp2LinkRate_5_40Gbps:
case dp2LinkRate_6_75Gbps:
case dp2LinkRate_8_10Gbps:
linkBw = LINK_RATE_10MHZ_TO_270MHZ(linkrate);
dpCtrlData = FLD_SET_DRF_NUM(0073_CTRL, _DP_DATA, _SET_LINK_BW,
@@ -1157,6 +1160,12 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
break;
}
if (FLD_TEST_DRF(0073_CTRL_DP, _ERR, _LINK_STATUS, _DISCONNECTED, err))
{
// Don't fallback if the device is already gone.
break;
}
if (FLD_TEST_DRF(0073_CTRL_DP, _CMD, _TRAIN_PHY_REPEATER, _YES, dpCtrlCmd) &&
FLD_TEST_DRF(0073_CTRL_DP, _ERR, _INVALID_PARAMETER, _ERR, err) &&
FLD_TEST_DRF(0073_CTRL_DP, _ERR, _TRAIN_PHY_REPEATER, _ERR, err))
@@ -1308,35 +1317,6 @@ bool EvoMainLink::getDynamicMuxState(NvU32 *muxState)
return bIsMuxCapable;
}
bool EvoMainLink::aquireSema()
{
NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS params;
dpMemZero(&params, sizeof(params));
params.subDeviceInstance = subdeviceIndex;
params.displayId = displayId;
params.owner = NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM;
NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA, &params, sizeof(params));
return code == NVOS_STATUS_SUCCESS;
}
void EvoMainLink::releaseSema()
{
NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS params;
dpMemZero(&params, sizeof(params));
params.subDeviceInstance = subdeviceIndex;
params.displayId = displayId;
params.owner = NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE;
NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA, &params, sizeof(params));
DP_USED(code);
DP_ASSERT(code == NVOS_STATUS_SUCCESS);
}
void EvoMainLink::configurePowerState(bool bPowerUp)
{
NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS params;
@@ -1368,7 +1348,8 @@ void EvoMainLink::getLinkConfig(unsigned &laneCount, NvU64 & linkRate)
if (params.linkBW != 0)
{
linkRate = ((NvU64)params.linkBW) * DP_LINK_BW_FREQ_MULTI_MBPS;
DP_ASSERT((params.dp2LinkBW == 0) && "dp2LinkBW should be zero if linkBw is not zero");
linkRate = LINK_RATE_270MHZ_TO_10MHZ((NvU64)params.linkBW);
}
else
{
@@ -1756,7 +1737,27 @@ void EvoMainLink::configureTriggerAll(NvU32 head, bool enable)
MainLink * DisplayPort::MakeEvoMainLink(EvoInterface * provider, Timer * timer)
{
MainLink *main;
main = new EvoMainLink(provider, timer);
NvU32 nvosStatus;
NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS dpParams = {0};
dpParams.subDeviceInstance = provider->getSubdeviceIndex();
nvosStatus = provider->rmControl0073(NV0073_CTRL_CMD_DP_GET_CAPS, &dpParams, sizeof dpParams);
if (nvosStatus != NVOS_STATUS_SUCCESS)
{
DP_ASSERT(0 && "Unable to get DP caps params");
return NULL;
}
if (FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED,
_DP2_0, _YES, dpParams.dpVersionsSupported))
{
main = new EvoMainLink2x(provider, timer);
}
else
{
main = new EvoMainLink(provider, timer);
}
return main;
}

1371
src/common/displayport/src/dp_evoadapter2x.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

10
src/common/displayport/src/dp_groupimpl.cpp
View File

@@ -346,11 +346,11 @@ void GroupImpl::updateVbiosScratchRegister(Device * lastDev)
//
// Helper function for attaching and detaching heads.
//
// For attach, we will assert if group already has head attached but for
// For attach, we will assert if group already has head attached but for
// some device in the group, active group did not point to current group.
// For detach, we will assert if the group does not have head attached but
// some device in group has an active group OR head is marked attached but
// not all devies in the group have the current group as active group.
// For detach, we will assert if the group does not have head attached but
// some device in group has an active group OR head is marked attached but
// not all devies in the group have the current group as active group.
// This also sets or clears dev->activeGroup for each contained
// device.
//
@@ -374,7 +374,7 @@ void GroupImpl::setHeadAttached(bool attached)
{
DP_ASSERT(di->activeGroup == NULL);
}
else
else
{
DP_ASSERT(di->activeGroup == this);
}

99
src/common/displayport/src/dp_linkconfig.cpp
View File

@@ -77,15 +77,18 @@ bool LinkConfiguration::lowerConfig(bool bReduceLaneCnt)
}
minRate = linkOverhead(peakRate);
setChannelCoding();
return lanes != laneCount_0;
}
LinkConfiguration::LinkConfiguration(LinkPolicy * p, unsigned lanes, LinkRate peakRate,
bool enhancedFraming, bool MST, bool disablePostLTRequest,
bool bEnableFEC, bool bDisableLTTPR)
: lanes(lanes), peakRatePossible(peakRate), peakRate(peakRate), enhancedFraming(enhancedFraming),
multistream(MST), disablePostLTRequest(disablePostLTRequest), bEnableFEC(bEnableFEC),
bDisableLTTPR(bDisableLTTPR), linkTrainCounter(0)
bool enhancedFraming, bool MST, bool disablePostLTRequest,
bool bEnableFEC, bool bDisableLTTPR, bool bDisableDownspread)
: lanes(lanes), peakRatePossible(peakRate), peakRate(peakRate),
enhancedFraming(enhancedFraming), multistream(MST),
disablePostLTRequest(disablePostLTRequest), bEnableFEC(bEnableFEC),
bDisableLTTPR(bDisableLTTPR), bDisableDownspread(bDisableDownspread),
linkTrainCounter(0)
{
// downrate for spread and FEC
minRate = linkOverhead(peakRate);
@@ -93,5 +96,91 @@ LinkConfiguration::LinkConfiguration(LinkPolicy * p, unsigned lanes, LinkRate pe
{
policy = *p;
}
setChannelCoding();
}
void LinkConfiguration::setChannelCoding()
{
bool b128b132bHBREnabled = ((bSupportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_7G) != 0);
if (IS_DP2_X_UHBR_LINKBW(peakRate) ||
(peakRate == dp2LinkRate_2_70Gbps && b128b132bHBREnabled))
{
bIs128b132bChannelCoding = true;
// FEC is always enabled for 128b/132b.
bEnableFEC = true;
}
else
{
bIs128b132bChannelCoding = false;
}
}
NvU64 LinkConfiguration::getBytesPerTimeslot()
{
NvU64 bytes_per_timeslot;
// spread is already considered during pbn calculation for required mode. No need to consider here
if(bIs128b132bChannelCoding)
{
// 128b/132b case
NvU64 linkRateBytes = DP_LINK_RATE_BITSPS_TO_BYTESPS(DP_LINK_RATE_10M_TO_BPS(peakRate) * lanes);
NvU64 total_data_bw = DATA_BW_EFF_128B_132B(linkRateBytes); // Unit: Bps (bytes)
bytes_per_timeslot = divide_floor(total_data_bw, 64);
}
else
{
// 8b/10b case
bytes_per_timeslot = getTotalDataRate() / 64;
}
return bytes_per_timeslot;
}
NvU32 LinkConfiguration::PBNForSlots(NvU32 slots)
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64;
NvU64 bytes_per_timeslot = getBytesPerTimeslot();
return (NvU32)(bytes_per_timeslot * slots/ bytes_per_pbn); // Rounded down
}
NvU32 LinkConfiguration::slotsForPBN(NvU32 allocatedPBN, bool usable)
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64;
NvU64 bytes_per_timeslot = getBytesPerTimeslot();
NvU32 slots;
if (bytes_per_timeslot == 0)
return (NvU32)-1;
if (usable)
{
// round down to find the usable integral slots for a given value of PBN.
slots = (NvU32)divide_floor(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
DP_ASSERT(slots <= 64);
}
else
{
slots = (NvU32)divide_ceil(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
}
return slots;
}
void LinkConfiguration::pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn)
{
base_pbn = pbnForMode(modesetInfo);
if (!bIs128b132bChannelCoding)
{
if (bEnableFEC)
{
// IF FEC is enabled, we need to consider 2.4% overhead as per DP1.4 spec.
base_pbn = (NvU32)(divide_ceil(base_pbn * 1000, 976));
}
}
slots = slotsForPBN(base_pbn);
slots_pbn = PBNForSlots(slots);
}

58
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -30,6 +30,7 @@
#include "dp_wardatabase.h"
#include "dp_edid.h"
#include "dp_connectorimpl.h"
#include "dp_connectorimpl2x.h"
#include "dp_printf.h"
using namespace DisplayPort;
@@ -93,9 +94,29 @@ void ConnectorImpl::applyOuiWARs()
}
}
void ConnectorImpl2x::applyOuiWARs()
{
switch (ouiId)
{
// Novatek Microelectronics Corp.
case 0x11EC38:
if((modelName[0] == 'N') && (modelName[1] == 'T') && (modelName[2] == '6'))
{
NvU8 portType;
if (hal->getSupportsMultistream() &&
hal->isDp2xChannelCodingCapable() &&
!hal->getDownstreamPort(&portType))
{
bMstTimeslotBug4968411 = true;
hal->setMainLinkChannelCoding(ChannelCoding128B132B);
}
}
break;
}
}
void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDenylistData)
{
unsigned ManufacturerID = this->getManufId();
unsigned ProductID = this->getProductId();
unsigned YearWeek = this->getYearWeek();
@@ -185,8 +206,8 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
if ((ProductID >= 0x0776 ) && (ProductID <= 0x0779)) // Product id's range from decimal 1910 to 1913
{
// if detailed pixel clock frequency = 106.50MHz
if ( (buffer.data[0x36] == 0x9A) &&
(buffer.data[0x37] == 0x29) )
if ((buffer.data[0x36] == 0x9A) &&
(buffer.data[0x37] == 0x29) )
{
// then change detailed pixel clock frequency to 106.54MHz to fix bug 343870
buffer.data[0x36] = 0x9E;
@@ -252,7 +273,7 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
// a "Monitor Description" of type FE = "ASCII Data String" which
// has this panel's name = "LP171WX2-A4K5".
//
if ( (buffer.data[0x71] == 0x4C) &&
if ((buffer.data[0x71] == 0x4C) &&
(buffer.data[0x72] == 0x50) &&
(buffer.data[0x73] == 0x31) &&
(buffer.data[0x74] == 0x37) &&
@@ -290,7 +311,7 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
// a "Monitor Description" of type FE = "ASCII Data String" which
// has this panel's name = "LP154WX4-TLC3".
//
if ( (buffer.data[0x71] == 0x4C) &&
if ((buffer.data[0x71] == 0x4C) &&
(buffer.data[0x72] == 0x50) &&
(buffer.data[0x73] == 0x31) &&
(buffer.data[0x74] == 0x35) &&
@@ -569,13 +590,38 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
// Asus
case 0x6D1E:
if(ProductID == 0x7707)
if (ProductID == 0x7707)
{
this->WARFlags.bIgnoreDscCap = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel incorrectly exposing DSC capability. Ignoring it.");
DP_PRINTF(DP_NOTICE, "DP-WAR> Bug 3543158");
}
break;
case 0xB306:
if (ProductID == 0x3228)
{
// ASUS PG32UQXR does not set DPCD 0x2217 to reflect correct CableID.
this->WARFlags.bSkipCableIdCheck = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel does not expose cable capability. Ignoring it. Bug 4968411");
}
break;
// Samsung
case 0x2D4C:
if (ProductID == 0x7474)
{
//
// Samsung Odyssey Neo 57 G9 needs manual allocation of timeslots when directly connected to upstream source
// Do not allocate manual timeslot when under a separate branch. This is checked with branch OUI.
//
this->WARFlags.bAllocateManualTimeslots = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel needs allocation of manual timeslot. Bug 4958974");
}
if (ProductID == 0x7256)
{
this->WARFlags.bDisableDownspread = true;
}
break;
default:
break;

21
src/common/displayport/src/dp_watermark.cpp
View File

@@ -49,6 +49,7 @@ bool DisplayPort::isModePossibleMST
{
// For MST, use downspread 0.6%
NvU64 linkFreq;
DP_ASSERT(!linkConfig.bIs128b132bChannelCoding);
linkFreq = LINK_RATE_TO_DATA_RATE_8B_10B(linkConfig.peakRate) * 994 / 1000;
// This function is for multistream only!
@@ -168,6 +169,7 @@ bool DisplayPort::isModePossibleSST
)
{
NvU64 laneDataRate;
DP_ASSERT(!linkConfig.bIs128b132bChannelCoding);
laneDataRate = linkConfig.convertMinRateToDataRate();
@@ -839,13 +841,20 @@ bool DisplayPort::isModePossibleMSTWithFEC
unsigned DisplayPort::pbnForMode(const ModesetInfo & modesetInfo)
{
// When DSC is enabled consider depth will multiplied by 16
unsigned dsc_factor = modesetInfo.bEnableDsc ? 16 : 1;
unsigned dsc_factor = 1;
if (modesetInfo.bEnableDsc)
{
if(modesetInfo.colorFormat == dpColorFormat_YCbCr422_Native)
{
dsc_factor = 32;
}
else
{
dsc_factor = 16;
}
}
//
// Calculate PBN in terms of 54/64 mbyte/sec
// round up by .6% for spread de-rate. Note: if we're not spreading our link
// this MUST still be counted. It's also to allow downstream links to be spread.
//
unsigned pbnForMode = (NvU32)(divide_ceil(modesetInfo.pixelClockHz * modesetInfo.depth * 1006 * 64 / 8,
(NvU64)54000000 * 1000 * dsc_factor));

257
src/common/inc/displayport/displayport.h
View File

@@ -129,6 +129,7 @@ typedef enum
linkBW_8_10Gbps = 0x1E,
linkBW_Supported
} DP_LINK_BANDWIDTH;
// TODO-@vduraisamy - below enum needs to be moved back to displayport2x.h
typedef enum
{
// enum value unit = 10M
@@ -140,7 +141,12 @@ typedef enum
dp2LinkRate_3_24Gbps = 0x0144, // 324
dp2LinkRate_4_32Gbps = 0x01B0, // 432
dp2LinkRate_5_40Gbps = 0x021C, // 540
dp2LinkRate_6_75Gbps = 0x02A3, // 675
dp2LinkRate_8_10Gbps = 0x032A, // 810
dp2LinkRate_5_00Gbps = 0x01F4, // 500
dp2LinkRate_10_0Gbps = 0x03E8, // 1000
dp2LinkRate_13_5Gbps = 0x0546, // 1350
dp2LinkRate_20_0Gbps = 0x07D0, // 2000
dp2LinkRate_Supported
} DP2X_LINKRATE_10M;
@@ -159,14 +165,34 @@ typedef enum
dataRate_8_10Gbps = 810000000
} DP_LINK_8B_10B_DATA_RATES;
#define IS_8B_10B_CODING(dataRate) (((NvU64)(val)== dataRate_1_62Gbps) || \
((NvU64)(val)== dataRate_2_16Gbps) || \
((NvU64)(val)== dataRate_2_43Gbps) || \
((NvU64)(val)== dataRate_2_70Gbps) || \
((NvU64)(val)== dataRate_3_24Gbps) || \
((NvU64)(val)== dataRate_4_32Gbps) || \
((NvU64)(val)== dataRate_5_40Gbps) || \
((NvU64)(val)== dataRate_8_10Gbps))
#define IS_8B_10B_CODING(dataRate) (((NvU64)(dataRate)== dataRate_1_62Gbps) || \
((NvU64)(dataRate)== dataRate_2_16Gbps) || \
((NvU64)(dataRate)== dataRate_2_43Gbps) || \
((NvU64)(dataRate)== dataRate_2_70Gbps) || \
((NvU64)(dataRate)== dataRate_3_24Gbps) || \
((NvU64)(dataRate)== dataRate_4_32Gbps) || \
((NvU64)(dataRate)== dataRate_5_40Gbps) || \
((NvU64)(dataRate)== dataRate_8_10Gbps))
typedef enum
{
// Uses 128b/132b channel encoding
// Link Data Rate = link rate * (128 / 132) / 8
// = link rate * 4 / 33
dataRate_UHBR_2_50Gbps = 303030303,
dataRate_UHBR_2_70Gbps = 327272727,
dataRate_UHBR_5_00Gbps = 606060606,
dataRate_UHBR_10_00Gbps = 1212121212,
dataRate_UHBR_13_50Gbps = 1636363636,
dataRate_UHBR_20_10Gbps = 2424242424U
} DP_LINK_128B_132B_DATA_RATES;
#define IS_128B_132B_CODING(dataRate) (((NvU64)(dataRate)== dataRate_UHBR_2_50Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_2_70Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_5_00Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_10_00Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_13_50Gbps) || \
((NvU64)(dataRate)== dataRate_UHBR_20_10Gbps))
typedef enum
{
@@ -212,9 +238,18 @@ typedef enum
{
trainingPattern_Disabled = 0x0,
trainingPattern_1 = 0x1,
// trainingPattern_128B132B_TPS1 = 0x1, (use trainingPattern_1 enum as both are same)
trainingPattern_2 = 0x2,
trainingPattern_3 = 0x3,
trainingPattern_4 = 0xB
trainingPattern_4 = 0xB,
trainingPattern_128B132B_TPS2 = 0xD,
trainingPattern_PRBS_9 = 0xE,
trainingPattern_PRBS_11 = 0xF,
trainingPattern_PRBS_15 = 0x10,
trainingPattern_PRBS_23 = 0x11,
trainingPattern_PRBS_31 = 0x12,
trainingPattern_SqNum = 0x13,
trainingPattern_CSTM_264 = 0x14
} DP_TRAININGPATTERN;
typedef enum
@@ -228,8 +263,9 @@ typedef enum
{
dpColorFormat_RGB = 0,
dpColorFormat_YCbCr444 = 0x1,
dpColorFormat_YCbCr422 = 0x2,
dpColorFormat_YCbCr422 = 0x2, // this is for simple 422
dpColorFormat_YCbCr420 = 0x3,
dpColorFormat_YCbCr422_Native = 0x4,
dpColorFormat_Unknown = 0xF
} DP_COLORFORMAT;
@@ -509,10 +545,87 @@ typedef struct VesaPsrSinkCaps
} vesaPsrSinkCaps;
#pragma pack()
typedef struct
{
//
// If True, then DSC CRC of multiple SU regions supported irrespective
// of byte counts.
// If False, then DSC CRC of multiple SU regions supported only when
// the byte count is multiple of 6.
//
NvBool bDscCrcOfMultipleSuSupported;
//
// If True, then SU coordinates need to adhere granularity specified in
// 000B2h, 000B3h, 000B4h.
// If False, then SU coordinates does not need to adhere any granularity.
//
NvBool bSelUpdateGranularityNeeded;
//
// If True, then source will use Y granularity specified in 000B5h, 000B6h
// for PR.
// If False, sink does not support Y granularity extended cap.
// Value in 000B4h shall be used for PR.
//
NvBool bSuYGranularityExtendedCap;
//
// Applicable to PR SU operation. Sets the grid pattern granularity in X axis.
// If non zero, X coordinate shall be even divisible by 000B2h, 000B3h
// If zero, no X coordinate granularity requirement exists.
//
NvU8 selUpdateXGranularityCap; // This represents 00B2h register
NvU8 selUpdateXGranularityCap1; // This represents 00B3h register
//
// Applicable to PR SU operation. Sets the grid pattern granularity in Y axis.
// If value is 00h or 01h, No restrictions to SU region Y coordinate.
// If value is 02h or higher, Y coordinate shall be evenly by divisible by 000B4h
//
NvU8 selUpdateYGranularityCap;
//
// Applicable to PR SU operation. when image compression is performed locally
// in sink device, this sets additional granularity in Y axis.
//
NvU8 selUpdateYGranularityExtCap;
NvU8 selUpdateYGranularityExtCap1;
} SelectiveUpdateCaps;
typedef struct PanelReplayCaps
{
// Indicates if Panel replay is supported or not
NvBool bPanelReplaySupported;
// Indicates if selective updates is supported or not
NvBool bSelUpdateSupported;
// Indicates if Early region transport is supported or not
NvBool bEarlyRegionTpSupported;
// Tells whether sink supports DSC decode functionality in PR.
NvBool bDscDecodeNotSupportedInPr;
//
// If true, it indicates that sink device does not support Asynchronous
// Video Timing while in a PR Active state. Source device shall keep
// transmitting Adaptive-Sync SDPs during a PR Active state.
//
NvBool bAdaptiveSyncSdpNotSupportedInPr;
//
// Applicable to PR function operation using AUX-less ALPM when both
// an Adaptive-Sync SDP v2 (HB2[4:0] = 02h) and a selective update –or–
// full frame update occurred during a video frame.
// 0 = Main-Link shall remain turned ON following the Adaptive-Sync
// SDP transmission and until after the first selective update region –or–
// full frame update transmission is complete.
// 1 = Source device may optionally turn OFF the Main-Link after the
// Adaptive-Sync SDP transmission and then turn the Main-Link back ON
// in time for the selective update –or– full frame update.
//
NvBool bLinkOffSupportAfterAsSdpSent;
SelectiveUpdateCaps suCaps;
} panelReplayCaps;
typedef struct PanelReplayConfig
@@ -540,6 +653,62 @@ typedef struct PanelReplayConfig
// CRC mismatch.
//
NvBool bHpdOnRfbActiveFrameCrcError;
// Configure selective update feature on sink.
NvBool bEnableSelectiveUpdate;
// Configure Early region transport on sink.
NvBool bSuRegionEarlyTpEnable;
//
// Applicable only during a PR Active state with AUX-less ALPM enabled.
// Sink device ignores the setting when while receiving an Adaptive-Sync
// SDP with HB2[4:0] = 02h and DB0[2] = 0. After receiving an
// Adaptive-Sync SDP with HB2[4:0] = 02h and DB0[2] = 1, the bit value
// determines the Sink device’s refresh timing.
// 0 = Sink device shall use the coasting VTotal value in the last
// Adaptive-Sync SDP received.
// 1 = Sink device evice governs the display refresh rate and ignores the
// coasting VTotal value
//
NvBool bSinkRrUnlockGranted;
//
// Applicable only to PR SU operation.
// 0 = Source device shall use the Y granularity value declared by the
// PANEL REPLAY SELECTIVE UPDATE Y GRANULARITY
// CAPABILITY register (DPCD 000B4h).
// 1 = Source device shall use a supported value listed in the
// SU Y GRANULARITY EXTENDED CAPABILITY register
// (DPCD 000B5h and 000B6h). The selected value shall be indicated
// by way of DPCD 001B1h[6:3].
//
NvBool bSelUpdateYExtValEnable;
//
// Applicable only to the PR function.
// 0 = Sink device shall capture the SU region, starting with the active
// video image scan line immediately following the first BE control link
// symbol sequence after the VSC SDP.
// 1 = Sink device shall capture the SU region, starting with the active
// video image scan line immediately following the second BE control link
// symbol sequence after the VSC SDP.
//
NvBool bSuRegionScanLineIndicate;
//
// Applicable only to PR SU operation.
// Used by the Source device to indicate which supported Y granularity
// extended capability value shall be used. Only a value declared to be
// supported by DPCD 000B5h and 000B6h may be chosen. Enabled
// when DPCD 001B1h[2] = 1, and may be used only when the SU Y
// Granularity Extended Capability Supported bit in the PANEL REPLAY
// CAPABILITY register is set (DPCD 000B1h[6] = 1).
//
NvU8 selUpdateYExtVal : 4;
//Adaptive-Sync SDP Setup Time Configuration during PR_State.
NvU8 asSdpSetUpTimePrActive: 2;
} panelReplayConfig;
// PR state
@@ -571,6 +740,68 @@ typedef struct
PanelReplayState prState;
} PanelReplayStatus;
typedef struct
{
//
// 0 = PM_State 2a (FW_STANDBY) is not supported.
// 1 = PM_State 2a (FW_STANDBY) is supported.
//
NvBool bFwStandbySupported;
//
// If Sink device reports this as TRUE then it supports AUX-less ALPM.
// PM_State 3b (ALW_SLEEP) is supported by default.
//
NvBool bAuxLessAlpmSupported;
//
// Indicates whether the Sink device supports the
// AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED debug bit in the
// RECEIVER_ALPM_ARP_STATUS register (DPCD 0200Bh[3]).
//
NvBool bAuxLessAlpmPhySleepSupported;
} AlpmCaps;
typedef struct
{
// Source will use this to configure ALPM on sink side
NvBool bEnableAlpm;
//
// when this field is enabled Sink will trigger HPD to notify source
// the event of an AUX-less ALPM lock timeout error
//
NvBool bHpdOnAlpmLockError;
// This field needs to be set to True to enable Aux less ALPM
NvBool bSelectedAlpmMode;
//
// This is duration of ACDS phase.
// The Aux less exit sequence is composed of LFPS, followed by a
// PHY Establishment period and then the AUX-less ALPM Clock and
// Data Switch(ACDS) period.
//
NvBool bAcdsPeriodDuration;
} AlpmConfig;
typedef struct
{
//
// Set by the Sink device if it does not achieve LANEx_CR_DONE,
// LANEx_CHANNEL_EQ_DONE, LANEx_SYMBOL_LOCKED, and
// INTERLANE_ALIGN_DONE, within the specified time period, after
// receiving the wake sequence signal (LFPS and Silence)
//
NvBool bAuxlessAlpmLockTimeout;
//
// Used for debug purposes. Set by the Sink device when
// two consecutive ML_PHY_SLEEP sequences are detected.
//
NvBool bAuxlessAlpmPhySleepDetected;
} AlpmStatus;
// Multiplier constant to get link frequency in KHZ
// Maximum link rate of Main Link lanes = Value x 270M.
// To get it to KHz unit, we need to multiply 270K.
@@ -588,6 +819,7 @@ typedef struct
// a * 1000(KHz) / 10 * 1000 * 1000(10Mhz)
//
#define LINK_RATE_KHZ_TO_10MHZ(a) ((a) / 10000)
#define LINK_RATE_10MHZ_TO_KHZ(a) ((a) * 10000)
#define LINK_RATE_270MHZ_TO_10MHZ(a) ((a) * 27)
#define LINK_RATE_10MHZ_TO_270MHZ(a) ((a) / 27)
@@ -599,7 +831,10 @@ typedef struct
#define DP_LINK_BW_FREQ_MULTI_MBPS 27000000
// Convert link rate in 10M to its value in bps
#define DP_LINK_RATE_10M_TO_BPS(linkRate) (linkRate * 10000000)
#define DP_LINK_RATE_10M_TO_BPS(linkRate) (linkRate * 10000000)
// Convert link rate in 270M to its value in bps
#define DP_LINK_RATE_270M_TO_BPS(linkRate) (linkRate * 270000000)
// Convert link rate from bps to Bps
#define DP_LINK_RATE_BITSPS_TO_BYTESPS(linkRate) (linkRate / 8)

190
src/common/inc/displayport/displayport2x.h Normal file
View File

@@ -0,0 +1,190 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DISPLAYPORT2X_H_
#define _DISPLAYPORT2X_H_
#include "nvmisc.h"
#include "dpcd.h"
#include "dpcd14.h"
#include "dpcd20.h"
#include "displayport.h"
/**************** Resource Manager Defines and Structures ******************\
* *
* Module: DISPLAYPORT2x.H *
* Defines DISPLAYPORT V2.x *
* *
\***************************************************************************/
//
// 4 Legacy Link Rates: RBR, HBR, HBR2, HBR3
// 5 ILRs: 2.16G, 2.43G, 3.24G, 4.32G, 6.75G
// 3 UHBRs: 10G, 13.5G, 20G
// 2 Internal Test: 2.5G, 5G Do NOT use in any other use cases.
//
#define NV_SUPPORTED_DP2X_LINK_RATES__SIZE 14
//
// For 128b/132b link rate to data rate, linkRate * 128/132 * 1/8 * 10M -> ((linkRate * 4 * 1000000) / 33)
// For 128b/132b data rate to link rate, dataRate * 132/128 * 8 * 1/10M -> ((dataRate * 33) / (4 * 10000000))
// Data rates used here are in Bytes per second.
//
#define LINK_RATE_TO_DATA_RATE_128B_132B(linkRate) ((linkRate * 4 * 10000000UL) / 33)
#define DATA_RATE_128B_132B_TO_LINK_RATE(dataRate) (NV_UNSIGNED_DIV_CEIL((dataRate * 33ULL), (4 * 10000000ULL)))
// To calculate the effective link rate with channel encoding accounted
#define OVERHEAD_128B_132B(linkRate) ((linkRate * 128) / 132)
//
// 128b/132b precise Data Bandwidth Efficiency.
// Per Spec 3.5.2.18, effective BW with 128b/132b channel coding is linkRate * 0.9671.
// This covers Phy logial layer efficiency 52/1584 and link layer efficiency of 4/65540 as well.
// Also add SSC margin of 0.5%.
// Additionally add another 0.1% for source to be slightly more conservative for DSC environments
// and provide maximum compatibility for LTTPR CDS LT sequence.
//
// (1 - 52/1584) * (1 - 4/65540) * 0.994 = 0.9612
//
#define DATA_BW_EFF_128B_132B(linkRate) ((linkRate * 9612) / 10000)
// For channel equalization, max loop count is 20 when waiting CHANNEL_EQ_DONE set.
#define NV_DP2X_MAX_LOOP_COUNT_POLL_CHNL_EQ_DONE (20U)
typedef enum
{
linkBW_6_75Gbps = 0x19
} DP2X_LINK_BANDWIDTH_270M;
// The definition here is to match HW register defines for link speed.
typedef enum
{
dp2LinkSpeedId_1_62Gbps = 0x00,
dp2LinkSpeedId_2_70Gbps = 0x01,
dp2LinkSpeedId_5_40Gbps = 0x02,
dp2LinkSpeedId_8_10Gbps = 0x03,
dp2LinkSpeedId_2_16Gbps = 0x04,
dp2LinkSpeedId_2_43Gbps = 0x05,
dp2LinkSpeedId_3_24Gbps = 0x06,
dp2LinkSpeedId_4_32Gbps = 0x07,
dp2LinkSpeedId_6_75Gbps = 0x08,
dp2LinkSpeedId_10_0Gbps = 0x12,
dp2LinkSpeedId_13_5Gbps = 0x13,
dp2LinkSpeedId_20_0Gbps = 0x14,
dp2LinkSpeedId_UHBR_1_62Gbps = 0x1C,
dp2LinkSpeedId_UHBR_5_00Gbps = 0x1D,
dp2LinkSpeedId_UHBR_2_70Gbps = 0x1E,
dp2LinkSpeedId_UHBR_2_50Gbps = 0x1F,
dp2LinkSpeedId_Supported
} DP2X_LINK_SPEED_INDEX;
typedef enum
{
dp2xTxFFEPresetId_0 = 0,
dp2xTxFFEPresetId_1 = 1,
dp2xTxFFEPresetId_2 = 2,
dp2xTxFFEPresetId_3 = 3,
dp2xTxFFEPresetId_4 = 4,
dp2xTxFFEPresetId_5 = 5,
dp2xTxFFEPresetId_6 = 6,
dp2xTxFFEPresetId_7 = 7,
dp2xTxFFEPresetId_8 = 8,
dp2xTxFFEPresetId_9 = 9,
dp2xTxFFEPresetId_10 = 10,
dp2xTxFFEPresetId_11 = 11,
dp2xTxFFEPresetId_12 = 12,
dp2xTxFFEPresetId_13 = 13,
dp2xTxFFEPresetId_14 = 14,
dp2xTxFFEPresetId_15 = 15,
dp2xTxFFEPresetId_Supported
} DP2X_TXFFE_PRESET_INDEX;
// Link Training stages for 128b/132b channel coding.
typedef enum
{
DP2X_LT_Set_ResetLink = 0,
DP2X_LT_Poll_ResetLink = 1,
DP2X_LT_Set_PreLT = 2,
DP2X_LT_Set_ChnlEq = 3,
DP2X_LT_Poll_ChnlEq_Done = 4,
DP2X_LT_Poll_ChnlEq_InterlaneAlign = 5,
DP2X_LT_Set_CDS = 6,
DP2X_LT_Poll_CDS = 7,
DP2X_LT_Set_PostLT = 8,
DP2X_LT_StageSupported
} DP2X_LT_STAGES;
typedef enum
{
DP2X_ResetLinkForPreLT,
DP2X_ResetLinkForFallback,
DP2X_ResetLinkForChannelCoding
} DP2X_RESET_LINK_REASON;
//
// Multiplier constant to get link frequency (multiplier of 10MHz) in MBps with 128b/132b channel coding.
// a * 10 * 1000 * 1000(10Mhz) * (128 / 132)(128b/132b) / 8(Byte)
//
#define DP_LINK_BW_FREQ_MULTI_10M_TO_MBPS (10 * 1000 * 1000 * 128 / (132 * 8))
//
// Multiplier constant to get DP2X link frequency in KHZ
// Maximum link rate of Main Link lanes = Value x 10M.
// To get it to KHz unit, we need to multiply 10K.
//
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_10MHZ_TO_KHZ (10*1000)
//
// Multiplier constant to get link frequency (multiplier of 270MHz) in MBps
// a * 10 * 1000 * 1000(10Mhz) * (8 / 10)(8b/10b) / 8(Byte)
// = a * 1000000
//
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_10MHZ_TO_10HZ (1000*1000)
#define IS_STANDARD_DP2_X_LINKBW(val) (((NvU32)(val)==dp2LinkRate_1_62Gbps) || \
((NvU32)(val)==dp2LinkRate_2_70Gbps) || \
((NvU32)(val)==dp2LinkRate_5_40Gbps) || \
((NvU32)(val)==dp2LinkRate_8_10Gbps))
#define IS_INTERMEDIATE_DP2_X_LINKBW(val) (((NvU32)(val)==dp2LinkRate_2_16Gbps) || \
((NvU32)(val)==dp2LinkRate_2_43Gbps) || \
((NvU32)(val)==dp2LinkRate_3_24Gbps) || \
((NvU32)(val)==dp2LinkRate_4_32Gbps) || \
((NvU32)(val)==dp2LinkRate_6_75Gbps))
#define IS_DP2_X_UHBR_LINKBW(val) (((NvU32)(val)==dp2LinkRate_2_50Gbps) || \
((NvU32)(val)==dp2LinkRate_5_00Gbps) || \
((NvU32)(val)==dp2LinkRate_10_0Gbps) || \
((NvU32)(val)==dp2LinkRate_13_5Gbps) || \
((NvU32)(val)==dp2LinkRate_20_0Gbps))
#define IS_VALID_DP2_X_LINKBW(val) (IS_STANDARD_DP2_X_LINKBW(val) || \
IS_INTERMEDIATE_DP2_X_LINKBW(val) || \
IS_DP2_X_UHBR_LINKBW(val))
#define IS_LEGACY_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
((NvU32)(val)==linkBW_2_43Gbps) || \
((NvU32)(val)==linkBW_3_24Gbps) || \
((NvU32)(val)==linkBW_4_32Gbps) || \
((NvU32)(val)==linkBW_6_75Gbps))
#endif // #ifndef _DISPLAYPORT2X_H_

27
src/common/inc/displayport/dpcd.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -447,6 +447,9 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LESS_THAN_0_5 (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE 6:6 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_NO (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_YES (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED 7:7 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_FALSE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */
@@ -915,16 +918,20 @@ number of Downstream ports will be limited to 32.
// 00283h - 002BFh: RESERVED. Read all 0s.
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS (0x000002C0) /* R-XUR */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED 0:0 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS (0x000002C0) /* R-XUR */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED 0:0 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1 /* R-XUF */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO (0x00000000) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES (0x00000001) /* R-XUV */
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_VC_PAYLOAD_ID_SLOT0_5_0 7:2 /* R-XUF */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT(i) (0x000002C1+(i)) /* R--1A */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT__SIZE 63 /* R---S */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT1 (0x000002C1) /* R-XUR */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT1_VC_PAYLOAD_ID_SLOT0_6 7:7 /* R-XUF */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT(i) (0x000002C1+(i)) /* R--1A */
#define NV_DPCD_VC_PAYLOAD_ID_SLOT__SIZE 63 /* R---S */
// Source Device-Specific Field, Burst write for 00300h-0030Bh
// 6 hex digits: 0x300~0x302.

372
src/common/inc/displayport/dpcd20.h
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@@ -48,6 +48,12 @@
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0 /* R-XUF */
@@ -68,6 +74,12 @@
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR 5:5 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE 6:6 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT 7:7 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS (0x00002020) /* R-XUR */
@@ -110,6 +122,321 @@
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LINK_BANDWIDTH_SET (0x00000100) /* RWXUR */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL 7:0 /* RWXUF */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_10_0 (0x00000001) /* RWXUV */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_20_0 (0x00000002) /* RWXUV */
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_13_5 (0x00000004) /* RWXUV */
// UHBR-128B/132B specific
#define NV_DPCD20_128B_132B_TRAINING_PATTERN (0x00000102) /* RWXUR */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT 3:0 /* RWXUF */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_NONE (0x00000000) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS1 (0x00000001) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2 (0x00000002) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2_CDS (0x00000003) /* RWXUV */
// Bit 7:4 are reserved for 128b/132b. Driver should keep them 0
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_RESERVED 7:4 /* RWXUF */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_RESERVED_ZERO (0x00000000) /* RWXUV */
#define NV_DPCD20_TRAINING_LANE_SET(i) (0x00000103+(i)) /* RW-1A */
#define NV_DPCD20_TRAINING_LANE_SET__SIZE 4 /* RW--S */
#define NV_DPCD20_TRAINING_LANE_SET_TX_FFE_PRESET_VALUE 3:0 /* RWXUF */
#define NV_DPCD20_TRAINING_LANE0_SET (0x00000103) /* RWXUR */
#define NV_DPCD20_LINK_QUAL_LANE_SET(i) (0x0000010B+(i)) /* RW-1A */
#define NV_DPCD20_LINK_QUAL_LANE_SET__SIZE 4 /* RW--S */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS 6:0 /* RWXUF */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_128B132B_TPS1 (0x00000008) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_128B132B_TPS2 (0x00000010) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS9 (0x00000018) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS11 (0x00000020) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS15 (0x00000028) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS23 (0x00000030) /* RWXUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS31 (0x00000038) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_264_BIT_CUSTOM (0x00000040) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON (0x00000048) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON (0x00000049) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF (0x0000004A) /* R-XUV */
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF (0x0000004B) /* R-XUV */
#define NV_DPCD20_LINK_SQUARE_PATTERN_NUM_PLUS_1 (0x0000010F) /* RWXUR */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF (0x00000121) /* RWXUR */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED 0:0 /* RWXUF */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUV */
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED (0x00000204) /* R-XUR */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED 4:4 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_SINK_STATUS (0x00000205) /* R-XUR */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_TEST_REQUEST (0x00000218) /* R-XUR */
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING 4:4 /* R-XUF */
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_8B10B (0x00000000) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_128B132B (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ 5:5 /* R-XUF */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO 6:6 /* R-XUF */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_LINK_RATE (0x00000219) /* R-XUR */
#define NV_DPCD20_TEST_LINK_RATE_TYPE 7:0 /* R-XUF */
#define NV_DPCD20_TEST_LINK_RATE_TYPE_10_0G (0x00000001) /* R-XUV */
#define NV_DPCD20_TEST_LINK_RATE_TYPE_20_0G (0x00000002) /* R-XUV */
#define NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G (0x00000004) /* R-XUV */
// Bug 4953977: Unigraf UCD323 uses the wrong value to request test link training.
// WAR to add off-spec value
#define NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G_2 (0x00000003) /* R-XUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_PHY_TEST_PATTERN (0x00000248) /* R-XUR */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_DP20 6:0 /* R-XUF */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS1 (0x00000008) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS2 (0x00000010) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS9 (0x00000018) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS11 (0x00000020) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS15 (0x00000028) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS23 (0x00000030) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS31 (0x00000038) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_264_BIT_CUSTOM (0x00000040) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON (0x00000048) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON (0x00000049) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF (0x0000004A) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF (0x0000004B) /* R-XUV */
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_LTTPR_CLOCK_SWITCH 7:7 /* R-XUF */
#define NV_DPCD20_PHY_SQUARE_PATTERN_NUM_PLUS_1 (0x00000249) /* R-XUR */
// 0x2230 - 0x2250 = 33 bytes
#define NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN(i) (0x00002230+(i)) /* R--1A */
#define NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN__SIZE 33 /* R---S */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX (0x00002251) /* R-XUR */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP 0:0 /* R-XUF */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP_NOT_SUPPORTED (0x00000000) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL (0x00002252) /* R-XUR */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE 0:0 /* R-XUF */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION 2:1 /* R-XUF */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_15 (0x00000000) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_30 (0x00000001) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_60 (0x00000002) /* R-XUV */
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_120 (0x00000003) /* R-XUV */
// Field definition for 0x0206/0x0207h (ADJUST_REQUEST_LANEX), only used only with 128b/132b for DP2.0+
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEX_TX_FFE_PRESET_VALUE 3:0 /* R-XUF */
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_TX_FFE_PRESET_VALUE 7:4 /* R-XUF */
// Field definition for 0x0200E (LANE_ALIGN_STATUS_UPDATED_ESI), used only when DP2.0+ 128b/132b is enabled.
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED 4:4 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
// Field definition for 0x0200F (SINK_STATUS_ESI), used only when DP2.0+ 128b/132b is enabled.
#define NV_DPCD20_SINK_STATUS_ESI (0x0000200F) /* R-XUR */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING (0x00002206) /* R-XUR */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B 0:0 /* R-XUF */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B 1:1 /* R-XUF */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES (0x00002215) /* R-XUR */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10 0:0 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20 1:1 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5 2:2 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_YES (0x00000001) /* R-XUV */
//
// The interval is (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) * INTERVAL_UNIT.
// The maximum is 256 ms.
//
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL (0x00002216) /* R-XUR */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT 7:7 /* R-XUF */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_MAX_MS 256
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING (0x000F0006) /* RWXUR */
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUF */
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES (0x000F0007) /* R-XUR */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED 1:1 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1 1:1 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2 2:2 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3 3:3 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4 4:4 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5 5:5 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6 6:6 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7 7:7 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS (0x000F0009) /* R-XUR */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS 0:0 /* R-XUF */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS_NOT_SUPPORTED (0x00000000) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_PHY_REPEATER_TOTAL_LTTPR_CNT (0x000F000A) /* RWXUR */
#define NV_DPCD20_PHY_REPEATER_TOTAL_LTTPR_CNT_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD (0x000000B1) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR 3:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED 4:4 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED 5:5 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED 6:6 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP 7:7 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY (0x000000B2) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY1 (0x000000B3) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY1_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_CAPABILITY (0x000000B4) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_CAPABILITY_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY (0x000000B5) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY1 (0x000000B6) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY1_VAL 7:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2 (0x000001B1) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_SELECTION 6:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION 7:7 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION3 (0x0000011A) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION3_AS_SDP_SETUP_CONFIG_PR_ACTIVE_TIME 7:6 /* R-XUF */
//
// Adding DPCD registers for EDP ALPM.
//
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES (0x0000002E) /* R-XUR */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT 1:1 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP 2:2 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT 3:3 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION (0x00000116) /* R-XUR */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM 0:0 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR 1:1 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE 2:2 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE_AUX_WAKE_ALPM (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE_AUX_LESS_ALPM (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION 3:3 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS (0x0000200B) /* R-XUR */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR 0:0 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR 2:2 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED 3:3 /* R-XUF */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED_YES (0x00000001) /* R-XUV */
//
// Adding DPCD registers for DP Tunneling feature.
@@ -179,6 +506,22 @@
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_TWO (0x00000002) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_FOUR (0x00000004) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_MAIN_LINK_CHANNEL_CODING (0x000E002B) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES (0x000E002C) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED 1:1 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DPTX_BW_ALLOCATION_MODE_CONTROL (0x000E0030) /* R-XUR */
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ 6:6 /* R-XUF */
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ_NO (0x00000000) /* R-XUV */
@@ -187,4 +530,33 @@
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_YES (0x00000001) /* R-XUV */
// DPCD Registers for Cable ID
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX (0x00000110) /* R-XUR */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY 1:0 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_UHBR_NOT_CAPABLE (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_10_0_GBPS_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_10_AND_20_GBPS_SUPPORTED (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE 5:3 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_CABLE_TYPE_UNKNOWN (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_PASSIVE (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_LRD (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_ACTIVE_RETIMER (0x00000003) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX (0x00002217) /* R-XUR */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY 1:0 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_UHBR_NOT_CAPABLE (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_10_0_GBPS_SUPPORTED (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_10_AND_20_GBPS_SUPPORTED (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE 5:3 /* R-XUF */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_CABLE_TYPE_UNKNOWN (0x00000000) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_PASSIVE (0x00000001) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_LRD (0x00000002) /* R-XUV */
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_ACTIVE_RETIMER (0x00000003) /* R-XUV */
#endif // #ifndef _DISPLAYPORT20_H_

22
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r565_00
#define NV_BUILD_BRANCH r571_57
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r565_00
#define NV_PUBLIC_BRANCH r571_57
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r565/r565_00-213"
#define NV_BUILD_CHANGELIST_NUM (35186646)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r571_57-275"
#define NV_BUILD_CHANGELIST_NUM (35438409)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r565/r565_00-213"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35186646)
#define NV_BUILD_NAME "rel/gpu_drv/r570/r571_57-275"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35438409)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r565_00-169"
#define NV_BUILD_CHANGELIST_NUM (35186646)
#define NV_BUILD_BRANCH_VERSION "r571_57-35"
#define NV_BUILD_CHANGELIST_NUM (35438409)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "566.31"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35186646)
#define NV_BUILD_BRANCH_BASE_VERSION R565
#define NV_BUILD_NAME "572.13"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35438409)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

3
src/common/inc/nvCpuIntrinsics.h
View File

@@ -285,8 +285,7 @@ static NV_FORCEINLINE int __NVatomicDecrement_LSE(int volatile *location)
//
// for (__NVbsfFirst(&index, &mask, maskInit); mask; __NVbsfNext(&index, &mask)) { ... }
//
// These operations are implemented using gcc/MSVC builtins/intrinsics. A test program to verify the correct
// functionality of these routines is available at //sw/pvt/ddadap/bitscantest.c
// These operations are implemented using gcc/MSVC builtins/intrinsics.
//
// The scan process provides the next valid "index". In __NVbsfNext() the bit corresponding to the passed in
// (1 << index) will be masked out.

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "565.77"
#define NV_VERSION_STRING "570.86.15"
#else

2
src/common/inc/nvVer.h
View File

@@ -3,7 +3,7 @@
#define NV_COMPANY_NAME_STRING_SHORT "NVIDIA"
#define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation"
#define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL
#define NV_COPYRIGHT_YEAR "2024"
#define NV_COPYRIGHT_YEAR "2025"
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \

5
src/common/inc/nvlog_defs.h
View File

@@ -102,9 +102,10 @@ struct _NVLOG_BUFFER
#define NVLOG_MAX_BUFFERS_v11 16
#define NVLOG_MAX_BUFFERS_v12 256
#define NVLOG_MAX_BUFFERS_v13 3840
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v12
#define NVLOG_LOGGER_VERSION 12 // v1.2
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v13
#define NVLOG_LOGGER_VERSION 13 // v1.3
// Due to this file's peculiar location, NvPort may or may not be includable
typedef struct PORT_SPINLOCK PORT_SPINLOCK;

71
src/common/inc/swref/published/ampere/ga100/dev_nv_pcfg_xve_regmap.h Normal file
View File

@@ -0,0 +1,71 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __dev_nv_pcfg_xve_regmap_h__
#define __dev_nv_pcfg_xve_regmap_h__
#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000
/*
* <prefix>_MAP has 1 bit set for each dword register.
* <prefix>_COUNT has total number of set bits in <prefix>_MAP.
*/
#define NV_PCFG_XVE_REGISTER_VALID_COUNT 445
#define NV_PCFG_XVE_REGISTER_VALID_MAP { \
/* 0x00088000 */ 0xFFF1FFFF, 0x139FFF9F, \
/* 0x00088100 */ 0x1FBA3C7F, 0x00000000, \
/* 0x00088200 */ 0x03F00000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA1F, 0x00000000, \
/* 0x00088700 */ 0x0001FFFF, 0x00000000, \
/* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \
/* 0x00088900 */ 0xFFFFFFFF, 0x000FFFFF, \
/* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \
/* 0x00088B00 */ 0x00000000, 0xFFFFF000, \
/* 0x00088C00 */ 0x0007BFE7, 0xFFFFFFFC, \
/* 0x00088D00 */ 0xFFFFFFFF, 0x7FFF3FFF, \
/* 0x00088E00 */ 0x000007FF, 0x00000000, \
/* 0x00088F00 */ 0x00000000, 0xFC000000 }
#define NV_PCFG_XVE_REGISTER_WR_COUNT 321
#define NV_PCFG_XVE_REGISTER_WR_MAP { \
/* 0x00088000 */ 0x3EF193FA, 0x1187C505, \
/* 0x00088100 */ 0x1FBA0828, 0x00000000, \
/* 0x00088200 */ 0x03200000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x80007EC0, 0x3F075007, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA10, 0x00000000, \
/* 0x00088700 */ 0x0001FFFF, 0x00000000, \
/* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \
/* 0x00088900 */ 0xFFFC7804, 0x000FFFFF, \
/* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \
/* 0x00088B00 */ 0x00000000, 0xF8A54000, \
/* 0x00088C00 */ 0x00003C01, 0x3FFFFFFC, \
/* 0x00088D00 */ 0xFFFFFFFC, 0x739B2C3F, \
/* 0x00088E00 */ 0x000007F8, 0x00000000, \
/* 0x00088F00 */ 0x00000000, 0xFC000000 }
#endif // {__dev_nv_pcfg_xve_regmap_h__}

1
src/common/inc/swref/published/blackwell/gb100/dev_pcfg_pf0.h
View File

@@ -257,5 +257,6 @@
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_PRI_ERROR_2ND 29:29 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_DEVICE_LOCKDOWN 30:30 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUNCTION_LOCKDOWN 31:31 /* R-IVF */
#define NV_PF0_PF_RESIZABLE_BAR_CAPABILITY 0x0000019c /* R--4R */
#endif // __gb100_dev_pcfg_pf0_h__

49
src/common/inc/swref/published/blackwell/gb100/dev_riscv_pri.h
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@@ -1,49 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_riscv_pri_h__
#define __gb100_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM 2:2 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ITCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM 3:3 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DTCM_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_ICACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE 5:5 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_DCACHE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE 6:6 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_RVCORE_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_REG_NO_FAULT 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM 12:12 /* R-IVF */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_FAULTED 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_FAULT_CONTAINMENT_SRCSTAT_MPURAM_NO_FAULT 0x00000000 /* R-I-V */
#endif // __gb100_dev_riscv_pri_h__

37
src/common/inc/swref/published/blackwell/gb10b/dev_boot.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_boot_h__
#define __gb10b_dev_boot_h__
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#endif // __gb10b_dev_boot_h__

29
src/common/inc/swref/published/blackwell/gb10b/dev_ce.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_ce_h__
#define __gb10b_dev_ce_h__
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 2 /* */
#endif // __gb10b_dev_ce_h__

64
src/common/inc/swref/published/blackwell/gb10b/dev_fault.h Normal file
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@@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_fault_h__
#define __gb10b_dev_fault_h__
#define NV_PFAULT_CLIENT_HUB_PD1 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC1 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC2 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC3 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_SCC1 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB1 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_SCC2 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB2 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_SCC3 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB3 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD1 0x00000046 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD2 0x00000047 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD3 0x00000048 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE1 0x00000049 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE2 0x0000004A /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE3 0x0000004B /* */
#define NV_PFAULT_CLIENT_HUB_PD2 0x0000004C /* */
#define NV_PFAULT_CLIENT_HUB_PD3 0x0000004D /* */
#define NV_PFAULT_CLIENT_HUB_ESC0 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC1 0x00000064 /* */
#define NV_PFAULT_CLIENT_HUB_ESC2 0x00000065 /* */
#define NV_PFAULT_CLIENT_HUB_ESC3 0x00000066 /* */
#define NV_PFAULT_CLIENT_HUB_ESC4 0x00000067 /* */
#define NV_PFAULT_CLIENT_HUB_ESC5 0x00000068 /* */
#define NV_PFAULT_CLIENT_HUB_ESC6 0x00000069 /* */
#define NV_PFAULT_CLIENT_HUB_ESC7 0x0000006a /* */
#define NV_PFAULT_CLIENT_HUB_ESC8 0x0000006b /* */
#define NV_PFAULT_CLIENT_HUB_ESC9 0x0000006c /* */
#define NV_PFAULT_CLIENT_HUB_ESC10 0x0000006d /* */
#define NV_PFAULT_CLIENT_HUB_ESC11 0x0000006e /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE0 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER2 0x0000007C /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER3 0x0000007D /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER4 0x0000007E /* */
#define NV_PFAULT_CLIENT_HUB_NVENC3 0x0000007F /* */
#endif // __gb10b_dev_fault_h__

37
src/common/inc/swref/published/blackwell/gb10b/dev_fbhub.h Normal file
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@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_fb_h__
#define __gb10b_dev_fb_h__
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO 0x008a1d58 /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xffffff00 /* RW--V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI 0x008a1d5c /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000fffff /* RW--V */
#endif // __gb10b_dev_fb_h__

30
src/common/inc/swref/published/blackwell/gb10b/dev_perf.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_perf_h__
#define __gb10b_dev_perf_h__
#define NV_PERF_PMASYS_CBLOCK_BPC_CONFIG_SECURE__SIZE_1 3 /* */
#define NV_PERF_PMASYS_CHANNEL_OUTBASE__SIZE_2 2 /* */
#endif // __gb10b_dev_perf_h__

30
src/common/inc/swref/published/blackwell/gb10b/dev_ram.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_ram_h__
#define __gb10b_dev_ram_h__
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (19+1*32):(0+1*32) /* RWXUF */
#endif // __gb10b_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_xtl_ep_pcfg_gpu_h__
#define __gb10b_dev_xtl_ep_pcfg_gpu_h__
/* This file is autogenerated. Do not edit */
#define NV_EP_PCFG_GPU 0xFFF:0x000 /* RW--D */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2 0x00000084 /* R--4R */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES 3:0 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B 0x00000003 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B_AND_C 0x00000006 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B_AND_C 0x00000007 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B_AND_C_AND_D 0x0000000E /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B_AND_C_AND_D 0x0000000F /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_NOT_SUPP 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE 4:4 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING 5:5 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING 6:6 /* R-CVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_NOT_SUPPORTED 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM 11:11 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER 13:12 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS 15:14 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER 16:16 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED 0x00000001 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER 17:17 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED 0x00000001 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF 19:18 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_MSG_SGNL 0x00000001 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_WAKE_SGNL 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_MSG_WAKE_SGNL 0x00000003 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT 20:20 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX 21:21 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX 23:22 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_4 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_1 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_2 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_3 0x00000003 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION 25:24 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED_DSM 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED_DSM_FF 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_RESERVED 0x00000003 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ 26:26 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS 31:31 /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_NOT_SUPPORTED 0x00000000 /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC 0x000002B4 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC__SAFETY "parity" /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR 15:0 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_OVERRIDEABLE 0 /* */
#endif // __gb10b_dev_xtl_ep_pcfg_gpu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_hwproject_h__
#define __gb10b_hwproject_h__
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 41
#endif // __gb10b_hwproject_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_pri_nv_xal_ep_h__
#define __gb10b_pri_nv_xal_ep_h__
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#define NV_XAL_EP_BAR0_WINDOW_BASE 24:0 /* RWIUF */
#define NV_XAL_EP_BAR0_WINDOW_BASE_0 0x0000000 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x0000010 /* */
#endif // __gb10b_pri_nv_xal_ep_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_boot_h__
#define __gb202_dev_boot_h__
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_POD 0:0 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUSE_SCPM 1:1 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_SEQUENCE_TOO_BIG 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRE_IFF_CRC_CHECK_FAILED 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_POST_IFF_CRC_CHECK_FAILED 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_ECC_UNCORRECTABLE_ERROR 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_CMD_FORMAT_ERROR 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_IFF_PRI_ERROR 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_SCPM 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_DCLS 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_EMP 12:12 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_UNCORRECTABLE_ERROR 13:13 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FSP_L5_WDT 14:14 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_SCPM 15:15 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 16:16 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 17:17 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 18:18 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 19:19 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 20:20 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 21:21 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_XTAL_CTFDC 22:22 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_XTAL_FMON 23:23 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_CLOCK_GPC_FMON 24:24 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 30:30 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 31:31 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_INTERRUPT 32:32 /* R-XUF */
#endif // __gb202_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_ce_h__
#define __gb202_dev_ce_h__
#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */
#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */
#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
#endif // __gb202_dev_ce_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_ce_base_h__
#define __gb202_dev_ce_base_h__
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 4
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 4
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gb202_dev_ce_base_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_fault_h__
#define __gb202_dev_fault_h__
#define NV_PFAULT /* ----G */
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 55 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 6 /* */
#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF1 11 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF2 12 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF3 13 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF4 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF5 15 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF6 16 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF7 17 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF8 18 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF9 19 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE 20 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE1 21 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE2 22 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE3 23 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE4 24 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE5 25 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE6 26 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE7 27 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 30 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 31 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 32 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC5 33 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC6 34 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC7 35 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 36 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG1 37 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG2 38 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG3 39 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG4 40 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG5 41 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG6 42 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG7 43 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 65 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 65 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 66 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 67 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 68 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 69 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 70 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 71 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 72 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 73 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 74 /* */
#define NV_PFAULT_MMU_ENG_ID_CE10 75 /* */
#define NV_PFAULT_MMU_ENG_ID_CE11 76 /* */
#define NV_PFAULT_MMU_ENG_ID_CE12 77 /* */
#define NV_PFAULT_MMU_ENG_ID_CE13 78 /* */
#define NV_PFAULT_MMU_ENG_ID_CE14 79 /* */
#define NV_PFAULT_MMU_ENG_ID_CE15 80 /* */
#define NV_PFAULT_MMU_ENG_ID_CE16 81 /* */
#define NV_PFAULT_MMU_ENG_ID_CE17 82 /* */
#define NV_PFAULT_MMU_ENG_ID_CE18 83 /* */
#define NV_PFAULT_MMU_ENG_ID_CE19 84 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 44 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 45 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 46 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC3 47 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 48 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST0 85 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST1 86 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST2 87 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST3 88 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST4 89 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST5 90 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST6 91 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST7 92 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST8 93 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST9 94 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST10 95 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST11 96 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST12 97 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST13 98 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST14 99 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST15 100 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST16 101 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST17 102 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST18 103 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST19 104 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST20 105 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST21 106 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST22 107 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST23 108 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST24 109 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST25 110 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST26 111 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST27 112 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST28 113 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST29 114 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST30 115 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST31 116 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST32 117 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST33 118 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST34 119 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST35 120 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST36 121 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST37 122 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST38 123 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST39 124 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST40 125 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST41 126 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST42 127 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST43 128 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST44 129 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 257 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 258 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 259 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 260 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 261 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 262 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 263 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 264 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 265 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 266 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 267 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 268 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 269 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 270 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 271 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 272 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 273 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 274 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 275 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 276 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 277 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 278 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 279 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 280 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 281 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 282 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 283 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 284 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 285 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 286 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 287 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 288 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 289 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 290 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 291 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 292 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 293 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 294 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 295 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 296 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 297 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 298 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 299 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 300 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 301 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 302 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 303 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 304 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 305 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 306 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 307 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 308 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 309 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 310 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 311 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 312 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 313 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 314 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 315 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 316 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 317 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 318 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 319 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 320 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 321 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 322 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 323 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 324 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 325 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 326 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 327 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 328 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 329 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 330 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 331 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 332 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 333 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 334 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 335 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 336 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 337 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 338 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 339 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 340 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 341 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 342 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 343 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 344 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 345 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 346 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 347 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 348 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 349 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 350 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 351 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 352 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 353 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 354 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 355 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 356 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 357 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 358 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 359 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 360 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 361 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 362 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 363 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 364 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 365 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 366 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 367 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 368 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 369 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 370 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 371 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 372 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 373 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 374 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 375 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 376 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 377 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 378 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 379 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 380 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 381 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 382 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 383 /* */
#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */
#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */
#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */
#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */
#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */
#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */
#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */
#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */
#define NV_PFAULT_FAULT_TYPE_CC_VIOLATION 0x0000000b /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */
#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */
#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */
#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */
#define NV_PFAULT_CLIENT_HUB_PD1 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC1 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC2 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC3 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_SCC1 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB1 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_SCC2 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB2 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_SCC3 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB3 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD1 0x00000046 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD2 0x00000047 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD3 0x00000048 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE1 0x00000049 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE2 0x0000004A /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE3 0x0000004B /* */
#define NV_PFAULT_CLIENT_HUB_PD2 0x0000004C /* */
#define NV_PFAULT_CLIENT_HUB_PD3 0x0000004D /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_2 0x00000072 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_3 0x00000073 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC0 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC1 0x00000064 /* */
#define NV_PFAULT_CLIENT_HUB_ESC2 0x00000065 /* */
#define NV_PFAULT_CLIENT_HUB_ESC3 0x00000066 /* */
#define NV_PFAULT_CLIENT_HUB_ESC4 0x00000067 /* */
#define NV_PFAULT_CLIENT_HUB_ESC5 0x00000068 /* */
#define NV_PFAULT_CLIENT_HUB_ESC6 0x00000069 /* */
#define NV_PFAULT_CLIENT_HUB_ESC7 0x0000006a /* */
#define NV_PFAULT_CLIENT_HUB_ESC8 0x0000006b /* */
#define NV_PFAULT_CLIENT_HUB_ESC9 0x0000006c /* */
#define NV_PFAULT_CLIENT_HUB_ESC10 0x0000006d /* */
#define NV_PFAULT_CLIENT_HUB_ESC11 0x0000006e /* */
#define NV_PFAULT_CLIENT_HUB_FSP 0x00000079 /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_GSPLITE0 0x0000007B /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER2 0x0000007C /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER3 0x0000007D /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER4 0x0000007E /* */
#define NV_PFAULT_CLIENT_HUB_NVENC3 0x0000007F /* */
#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */
#endif // __gb202_dev_fault_h__

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src/common/inc/swref/published/blackwell/gb202/dev_fsp_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_fsp_addendum_h__
#define __gb202_dev_fsp_addendum_h__
#define NV_GFW_FSP_UCODE_VERSION NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(1)
#define NV_GFW_FSP_UCODE_VERSION_FULL 11:0
#define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8
#define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0
#endif // __gb202_dev_fsp_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_fsp_pri_h__
#define __gb202_dev_fsp_pri_h__
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x008f0320+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gb202_dev_fsp_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_mmu_h__
#define __gb202_dev_mmu_h__
#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */
#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */
#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */
#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */
#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */
#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */
#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */
#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#endif // __gb202_dev_mmu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_ram_h__
#define __gb202_dev_ram_h__
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
#define NV_RAMRL_ENTRY_CHAN_RUNQUEUE_SELECTOR_RUNQUEUE1 0x00000001 /* */
#define NV_RAMRL_ENTRY_BASE_SHIFT 8 /* */
#endif // __gb202_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_runlist_h__
#define __gb202_dev_runlist_h__
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */
#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */
#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */
#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */
#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */
#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */
#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */
#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */
#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
#define NV_RUNLIST_PREEMPT 0x014 /* RW-4R */
#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */
#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */
#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */
#endif // __gb202_dev_runlist_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_therm_h__
#define __gb202_dev_therm_h__
#define NV_THERM_I2CS_SCRATCH 0x00ad00bc /* RW-4R */
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
#endif // __gb202_dev_therm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_therm_addendum_h__
#define __gb202_dev_therm_addendum_h__
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
#endif // __gb202_dev_therm_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_vm_h__
#define __gb202_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_DOORBELL_VECTOR 11:0 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_ID 22:16 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL 30:30 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL_DISABLE 0x0 /* -W--V */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL_ENABLE 0x1 /* -W--V */
#endif // __gb202_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_xtl_ep_pcfg_gpu_h__
#define __gb202_dev_xtl_ep_pcfg_gpu_h__
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_1 0x000002B4 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2 0x000002B8 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_IFF_POS 31:25 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_IFF_POS_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_IFF_POS_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_BAR_FIREWALL_ENGAGE 24:24 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_BAR_FIREWALL_ENGAGE_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_2_BAR_FIREWALL_ENGAGE_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2 0x00000084 /* R--4R */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_SUPPORTED 0x00000001 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 0x00000088 /* RW-4R */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* RWIVF */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_DEFAULT 0x00000000 /* RWI-V */
#endif // __gb202_dev_xtl_ep_pcfg_gpu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GB202_KIND_MACROS_H_INCLUDED
#define GB202_KIND_MACROS_H_INCLUDED
#define KIND_INVALID(k) ( ((k) ==NV_MMU_CLIENT_KIND_INVALID))
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_COMPRESSIBLE(k) ( ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_DISALLOWS_PLC(k) ( !((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_S8Z24)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define KIND_Z(k) ( ((k) >=NV_MMU_CLIENT_KIND_Z16 && (k) <= NV_MMU_CLIENT_KIND_Z24S8))
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))
#endif // GB202_KIND_MACROS_H_INCLUDED

30
src/common/inc/swref/published/blackwell/gb202/pri_nv_xal_ep.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_pri_nv_xal_ep_h__
#define __gb202_pri_nv_xal_ep_h__
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#endif // __gb202_pri_nv_xal_ep_h__

23
src/common/inc/swref/published/disp/v03_00/dev_disp.h
View File

@@ -114,11 +114,34 @@
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_RESET 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_RESET 0x00000001 /* -W--V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN 0x00611858 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH(i) (0+(i)):(0+(i)) /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH__SIZE_1 32 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_INIT 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_NOT_PENDING 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_PENDING 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_RESET 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER 0x0061185C /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE 0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_INIT 0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_RESET 0x00000001 /* -W--V */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(i) (0x0061611C+(i)*2048) /* RW-4A */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE 31:0 /* RWIUF */

46
src/common/inc/swref/published/disp/v04_01/dev_disp.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v04_01_dev_disp_h__
#define __v04_01_dev_disp_h__
#define NV_PDISP 0x006F1FFF:0x00610000 /* RW--D */
#define NV_PDISP_FE_EVT_DISPATCH 0x00611A00 /* R--4R */
#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN 26:26 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN 0x00611868 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH(i) (0+(i)):(0+(i)) /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH__SIZE_1 32 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_INIT 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_NOT_PENDING 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_PENDING 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_RESET 0x00000001 /* */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM 9:9 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_PENDING 0x00000001 /* R---V */
#endif // __v04_01_dev_disp_h__

40
src/common/inc/swref/published/disp/v05_01/dev_disp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,6 +23,7 @@
#ifndef __v05_01_dev_disp_h__
#define __v05_01_dev_disp_h__
#define NV_PDISP_POSTCOMP_LOADV_COUNTER(i) (0x0061A11C+(i)*1024) /* RW-4A */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE 31:0 /* RWIUF */
@@ -30,4 +31,41 @@
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING(i) (0x00611EF0+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_INTR_RETRIGGER(i) (0x00611F30+(i)*4) /* RW-4A */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER 0:0 /* RWIVF */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER_NONE 0x00000000 /* RWI-V */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER_TURE 0x00000001 /* -W--T */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP(i) (0x006405E8+(i)*4) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP__SIZE_1 8 /* */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MAX 7:0 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MAX__PRODCHK 0 /* */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MAX_INIT 0x00000077 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MIN 15:8 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MIN__PRODCHK 0 /* */
#define NV_PDISP_FE_SW_HEAD_CLK_CAP_PCLK_MIN_INIT 0x00000019 /* RWI-V */
#define NV_PDISP_RG_IN_LOADV_COUNTER(i) (0x00616320+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_IN_LOADV_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE 31:0 /* RWIUF */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE__PRODCHK 0 /* */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PDISP_RG_CRASHLOCK_COUNTER(i) (0x00616484+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_CRASHLOCK_COUNTER__SIZE_1 8 /* */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V 31:16 /* RWIUF */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V__PRODCHK 0 /* */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_RG_CRASHLOCK_COUNTER_V_ZERO 0x00000000 /* RW--V */
#endif // __v05_01_dev_disp_h__

2
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h
View File

@@ -117,4 +117,6 @@
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM 15:15 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_L1_PM_SS_CONTROL_1_REGISTER 0x00000298 /* RW-4R */
#define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CAP 0x00000138 /* R--4R */
#endif // __gh100_dev_xtl_ep_pcfg_gpu_h__

6
src/common/inc/swref/published/hopper/gh100/hwproject.h
View File

@@ -20,7 +20,13 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GH100_HWPROJECT_H_INCLUDED
#define GH100_HWPROJECT_H_INCLUDED
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52
#define NV_XPL_BASE_ADDRESS 540672
#define NV_XTL_BASE_ADDRESS 593920
#define NV_FBPA_PRI_STRIDE 16384
#endif // GH100_HWPROJECT_H_INCLUDED

19
src/common/inc/swref/published/nv_arch.h
View File

@@ -48,7 +48,9 @@
#define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170)
#define GPU_ARCHITECTURE_HOPPER GPU_ARCHITECTURE(_CLASSIC, 0x0180)
#define GPU_ARCHITECTURE_ADA GPU_ARCHITECTURE(_CLASSIC, 0x0190)
#define GPU_ARCHITECTURE_BLACKWELL GPU_ARCHITECTURE(_CLASSIC, 0x01A0)
#define GPU_ARCHITECTURE_BLACKWELL_GB1XX GPU_ARCHITECTURE(_CLASSIC, 0x01A0)
#define GPU_ARCHITECTURE_BLACKWELL_GB2XX GPU_ARCHITECTURE(_CLASSIC, 0x01B0)
#define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040)
#define GPU_ARCHITECTURE_T13X GPU_ARCHITECTURE(_TEGRA, 0x0013)
@@ -93,6 +95,7 @@
#define GPU_IMPLEMENTATION_GA106 0x06
#define GPU_IMPLEMENTATION_GA107 0x07
#define GPU_IMPLEMENTATION_GA102F 0x0F
#define GPU_IMPLEMENTATION_GH100 0x00
#define GPU_IMPLEMENTATION_AD102 0x02
#define GPU_IMPLEMENTATION_AD103 0x03
@@ -103,6 +106,20 @@
#define GPU_IMPLEMENTATION_GB100 0x00
#define GPU_IMPLEMENTATION_GB102 0x02
#define GPU_IMPLEMENTATION_GB10B 0x0B
#define GPU_IMPLEMENTATION_GB202 0x02
#define GPU_IMPLEMENTATION_GB203 0x03
#define GPU_IMPLEMENTATION_GB204 0x04
#define GPU_IMPLEMENTATION_GB205 0x05
#define GPU_IMPLEMENTATION_GB206 0x06
#define GPU_IMPLEMENTATION_GB207 0x07
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00

8
src/common/inc/swref/published/nv_ref.h
View File

@@ -133,6 +133,7 @@
#define NV_PMC_BOOT_0_ARCHITECTURE_GH100 0x00000018 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_AD100 0x00000019 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GB100 0x0000001A /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GB200 0x0000001B /* R---V */
#define NV_PMC_BOOT_1 0x00000004 /* R--4R */
#define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */
@@ -152,11 +153,18 @@
#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE 29:24 /* */
#define NV_PMC_BOOT_42_CHIP_ID 29:20 /* R-XVF */
#define NV_PMC_BOOT_42_ARCHITECTURE_GM100 0x00000011 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GM200 0x00000012 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GP100 0x00000013 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV100 0x00000014 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV110 0x00000015 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_TU100 0x00000016 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GH100 0x00000018 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AD100 0x00000019 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GB100 0x0000001A /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GB200 0x0000001B /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AMODEL 0x0000001F /* */
#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* */

3
src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,4 +25,5 @@
#define __ls10_ptop_discovery_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SOE_0 0x00840000 /* */
#endif // __ls10_ptop_discovery_ip_h__

4
src/common/inc/swref/published/turing/tu102/kind_macros.h
View File

@@ -21,7 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#define _kind_macros_orig_H_
#ifndef TU102_KIND_MACROS_H_INCLUDED
#define TU102_KIND_MACROS_H_INCLUDED
#define KIND_INVALID(k) ( ((k) ==NV_MMU_CLIENT_KIND_INVALID))
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
@@ -32,3 +33,4 @@
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))
#endif // TU102_KIND_MACROS_H_INCLUDED

91
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -48,6 +48,12 @@
#include "class/clc670.h"
#include "class/clc67d.h"
#include "class/clc770.h"
#include "class/clc870.h"
#include "class/clc87d.h"
#include "class/clc970.h"
#include "class/clc97d.h"
#include "class/clca70.h"
#include "class/clca7d.h"
#include "hdmi_spec.h"
@@ -181,6 +187,36 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NVC770_DISPLAY, // displayClass
NVC67D_CORE_CHANNEL_DMA // coreDmaClass
},
[NVHDMIPKT_C871_CLASS] = {// Index 9==NVHDMIPKT_C871_CLASS
NVHDMIPKT_C871_CLASS, // classId
NVHDMIPKT_C671_CLASS, // parentClassId
NV_FALSE, // isRootClass
initializeHdmiPktInterfaceC871, // initInterface
hdmiConstructorC871, // constructor
hdmiDestructorC871, // destructor
NVC870_DISPLAY, // displayClass
NVC87D_CORE_CHANNEL_DMA // coreDmaClass
},
[NVHDMIPKT_C971_CLASS] = {// Index 10==NVHDMIPKT_C971_CLASS
NVHDMIPKT_C971_CLASS, // classId
NVHDMIPKT_C871_CLASS, // parentClassId
NV_FALSE, // isRootClass
initializeHdmiPktInterfaceC971, // initInterface
hdmiConstructorC971, // constructor
hdmiDestructorC971, // destructor
NVC970_DISPLAY, // displayClass
NVC97D_CORE_CHANNEL_DMA // coreDmaClass
},
[NVHDMIPKT_CA71_CLASS] = {// Index 11==NVHDMIPKT_CA71_CLASS
NVHDMIPKT_CA71_CLASS, // classId
NVHDMIPKT_C971_CLASS, // parentClassId
NV_FALSE, // isRootClass
initializeHdmiPktInterfaceCA71, // initInterface
hdmiConstructorCA71, // constructor
hdmiDestructorCA71, // destructor
NVCA70_DISPLAY, // displayClass
NVCA7D_CORE_CHANNEL_DMA // coreDmaClass
},
};
/********************************** HDMI Library interfaces *************************************/
@@ -262,6 +298,61 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle,
pPacket);
}
/*
* NvHdmiPkt_PacketRead
*/
NVHDMIPKT_RESULT
NvHdmiPkt_PacketRead(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
NvU32 bufferLen,
NvU8 *const pOutPktBuffer)
{
if (libHandle == NVHDMIPKT_INVALID_HANDLE)
{
return NVHDMIPKT_LIBRARY_INIT_FAIL;
}
NVHDMIPKT_CLASS* pClass = fromHdmiPktHandle(libHandle);
if ((pOutPktBuffer == NULL) || (bufferLen == 0))
{
return NVHDMIPKT_INVALID_ARG;
}
return pClass->hdmiPacketRead(pClass,
subDevice,
head,
packetReg,
bufferLen,
pOutPktBuffer);
}
/*
* NvHdmiPkt_SetupAdvancedInfoframe
*/
NVHDMIPKT_RESULT
NvHdmiPkt_SetupAdvancedInfoframe(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
ADVANCED_INFOFRAME const *pInfoframe)
{
if (libHandle == NVHDMIPKT_INVALID_HANDLE)
{
return NVHDMIPKT_LIBRARY_INIT_FAIL;
}
NVHDMIPKT_CLASS* pClass = fromHdmiPktHandle(libHandle);
return pClass->programAdvancedInfoframe(pClass,
subDevice,
head,
packetReg,
pInfoframe);
}
NVHDMIPKT_RESULT
NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,

96
src/common/modeset/hdmipacket/nvhdmipkt.h
View File

@@ -57,6 +57,8 @@ typedef enum
NVHDMIPKT_ERR_GENERAL = 5,
NVHDMIPKT_INSUFFICIENT_BANDWIDTH = 6,
NVHDMIPKT_RETRY = 7,
NVHDMIPKT_INSUFFICIENT_BUFFER = 8,
NVHDMIPKT_DSC_PPS_ERROR = 9
} NVHDMIPKT_RESULT;
// NVHDMIPKT_TYPE: HDMI Packet Enums
@@ -75,7 +77,11 @@ typedef enum _NVHDMIPKT_TYPE
NVHDMIPKT_TYPE_SHARED_GENERIC4 = 9,
NVHDMIPKT_TYPE_SHARED_GENERIC5 = 10,
NVHDMIPKT_TYPE_SHARED_GENERIC6 = 11,
NVHDMIPKT_INVALID_PKT_TYPE = 12
NVHDMIPKT_TYPE_SHARED_GENERIC7 = 12,
NVHDMIPKT_TYPE_SHARED_GENERIC8 = 13,
NVHDMIPKT_TYPE_SHARED_GENERIC9 = 14,
NVHDMIPKT_TYPE_SHARED_GENERIC10 = 15,
NVHDMIPKT_INVALID_PKT_TYPE = 16
} NVHDMIPKT_TYPE;
// Hdmi packet TransmitControl defines. These definitions reflect the
@@ -173,6 +179,23 @@ typedef enum _NVHDMIPKT_TC
DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VBLANK)),
} NVHDMIPKT_TC;
typedef enum _INFOFRAME_CTRL_RUN_MODE
{
INFOFRAME_CTRL_RUN_MODE_ALWAYS = 0,
INFOFRAME_CTRL_RUN_MODE_ONCE,
INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS,
INFOFRAME_CTRL_RUN_MODE_FID_ONCE,
INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER
} INFOFRAME_CTRL_RUN_MODE;
typedef enum _INFOFRAME_CTRL_LOC
{
INFOFRAME_CTRL_LOC_VBLANK = 0,
INFOFRAME_CTRL_LOC_VSYNC,
INFOFRAME_CTRL_LOC_LINE,
INFOFRAME_CTRL_LOC_LOADV
} INFOFRAME_CTRL_LOC;
// RM client handles. Used when client chooses that hdmi library make RM calls.
// NOTE: NVHDMIPKT_RM_CALLS_INTERNAL macro should be define to use it.
typedef struct tagNVHDMIPKT_RM_CLIENT_HANDLES
@@ -260,6 +283,39 @@ typedef struct _tagNVHDMIPKT_CALLBACK
} NVHDMIPKT_CALLBACK;
/************************************************************************************************
* runMode - specify one of the modes of operation*
* location - vsync/line/vblank *
* flipId - client to provide if FID mode of operation, 0 otherwise *
* lineNum - if infoframe is sent at line border specify lineNum. 0 is default *
* *
* T239 chip more infoframe support *
************************************************************************************************/
typedef struct tagADVANCED_INFOFRAME
{
INFOFRAME_CTRL_RUN_MODE runMode;
INFOFRAME_CTRL_LOC location;
NvU32 flipId;
NvU32 lineNum;
NvU32 numAdditionalInfoframes;
NvU32 packetLen; // client is expected to fill in 9 DWs for each infoframe, leaving unused bytes 0
NvU8 const * pPacket; // (4 bytes header, 32 bytes max payload per infoframe) For SIZE > 0, pPacket is
// continuous array of multiple infoframes each 9DW in size
// flags
NvU32 isLargeInfoframe : 1; // set if client wants SIZE > 0. Default 0 = normal infoframe
NvU32 lineIdReversed : 1; // set if client wants line Id reversed. Default 0 = not reversed
NvU32 crcOverride : 1; // set if client uses CRC override. Default 0 = CRC override not used
NvU32 asSdpOverride : 1; // set if client wants to enable AS SDP override in infoframe HW
NvU32 hwChecksum : 1; // set if client wants HW checksum. Default 0 = SW checksum
NvU32 matchFidMethodArmState : 1; // set if client wants HW to send infoframe when FID method's ARM state matches. Default 0 = send only when FID method Active state
NvU32 winMethodCyaBroadcast : 1; // set if client will set up CYA reg for SF to decode directly. Default 0 = private precalc decode (SF decodes from precalc)
NvU32 highAudioPriority : 1; // set if client wants high priority for audio. Default 0 = audio low priority
NvU32 reserved : 24;
} ADVANCED_INFOFRAME;
/*********************** HDMI Library interface to write hdmi ctrl/packet ***********************/
typedef void* NvHdmiPkt_Handle;
#define NVHDMIPKT_INVALID_HANDLE ((NvHdmiPkt_Handle)0)
@@ -307,6 +363,44 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle,
NvU8 const *const pPacket);
/************************************************************************************************
* NvHdmiPkt_PacketRead - Returns HDMI NVHDMIPKT_RESULT. *
* *
* Parameters: *
* libHandle - Hdmi library handle, provided on initializing the library. *
* subDevice - Sub Device ID. *
* head - Head number. *
* packetReg - One of the NVHDMIPKT_TYPE types. *
* bufferLen - Size of the client provided read out buffer *
* pOutPktBuffer - buffer into which read packet data is to be written. *
************************************************************************************************/
NVHDMIPKT_RESULT
NvHdmiPkt_PacketRead(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
NvU32 bufferLen,
NvU8 *const pOutPktBuffer);
/************************************************************************************************
* NvHdmiPkt_SetupAdvancedInfoframe - Returns HDMI NVHDMIPKT_RESULT. *
* *
* Parameters: *
* libHandle - Hdmi library handle, provided on initializing the library. *
* subDevice - Sub Device ID. *
* head - Head number. *
* packetType - One of the NVHDMIPKT_TYPE types. *
* pInfoframe - details about infoframe to be programmed - run mode/loc/etc and pkt bytes *
************************************************************************************************/
NVHDMIPKT_RESULT
NvHdmiPkt_SetupAdvancedInfoframe(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
ADVANCED_INFOFRAME const *pInfoframe);
/***************************** Interface to initialize HDMI Library *****************************/
/************************************************************************************************

30
src/common/modeset/hdmipacket/nvhdmipkt_0073.c
View File

@@ -359,6 +359,33 @@ hdmiClearFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
return NVHDMIPKT_SUCCESS;
}
NVHDMIPKT_RESULT
hdmiPacketReadDummy(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
NvU32 bufferLen,
NvU8 *const pOutPktBuffer)
{
NvHdmiPkt_Print(pThis, "ERROR - Dummy function hdmiPacketReadDummy called. "
"Should never be called.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_SUCCESS;
}
NVHDMIPKT_RESULT
programAdvancedInfoframeDummy(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
const ADVANCED_INFOFRAME* pInfoframe)
{
NvHdmiPkt_Print(pThis, "ERROR - Dummy function programAdvancedInfoframeDummy called. "
"Should never be called.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_SUCCESS;
}
/*
* initializeHdmiPktInterface0073
*/
@@ -389,4 +416,7 @@ initializeHdmiPktInterface0073(NVHDMIPKT_CLASS* pClass)
pClass->hdmiSetFRLConfig = hdmiSetFRLConfigDummy;
pClass->hdmiClearFRLConfig = hdmiClearFRLConfigDummy;
// More (generic) infoframe support on T239+
pClass->hdmiPacketRead = hdmiPacketReadDummy;
pClass->programAdvancedInfoframe = programAdvancedInfoframeDummy;
}

3
src/common/modeset/hdmipacket/nvhdmipkt_9171.c
View File

@@ -828,4 +828,7 @@ initializeHdmiPktInterface9171(NVHDMIPKT_CLASS* pClass)
pClass->hdmiSetFRLConfig = hdmiSetFRLConfigDummy;
pClass->hdmiClearFRLConfig = hdmiClearFRLConfigDummy;
// T239+
pClass->hdmiPacketRead = hdmiPacketReadDummy;
pClass->programAdvancedInfoframe = programAdvancedInfoframeDummy;
}

12
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -360,7 +360,12 @@ static void populateDscCaps(HDMI_SRC_CAPS const * const pSrcCaps,
pDscInfo->sinkCaps.algorithmRevision.versionMajor = 1;
pDscInfo->sinkCaps.algorithmRevision.versionMinor = 2;
pDscInfo->sinkCaps.peakThroughputMode0 = peakThroughput;
pDscInfo->sinkCaps.peakThroughputMode1 = peakThroughput * 2;
// Per DSC v1.2 spec, native 422/420 per-slice peak throughput is approximately twice of RGB/444 peak throughput
// HDMI has only one throughput cap reporting, no separate 422/420 throughput cap unlike for DP, so just double 444's value here.
pDscInfo->sinkCaps.peakThroughputMode1 = (peakThroughput == DSC_DECODER_PEAK_THROUGHPUT_MODE0_340) ?
DSC_DECODER_PEAK_THROUGHPUT_MODE1_650 : // closest approximation to 680Mhz
DSC_DECODER_PEAK_THROUGHPUT_MODE1_800;
}
// Fill in mode related info for DSC lib
@@ -790,7 +795,7 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
(pClientCtrl->forceBppx16 && ((pClientCtrl->bitsPerPixelX16 < bppMinX16) || (pClientCtrl->bitsPerPixelX16 > bppMaxX16))) ||
(pClientCtrl->forceBppx16 && !pSinkCaps->pHdmiForumInfo->dsc_All_bpp))
{
return NVHDMIPKT_FAIL;
return NVHDMIPKT_INVALID_ARG;
}
bTryUncompressedMode = (bCanUseDSC && (pClientCtrl->enableDSC ||
@@ -1185,8 +1190,9 @@ frlQuery_Success:
{
NvHdmiPkt_Print(pThis, "ERROR - DSC PPS calculation failed.");
NvHdmiPkt_Assert(0);
result = NVHDMIPKT_FAIL;
result = NVHDMIPKT_DSC_PPS_ERROR;
}
if (pDscScratchBuffer != NULL)
{
pThis->callback.free(pThis->cbHandle, pDscScratchBuffer);

641
src/common/modeset/hdmipacket/nvhdmipkt_C871.c Normal file
View File

@@ -0,0 +1,641 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_C871.c
*
*/
#include "nvhdmipkt_common.h"
/*
* Purpose: Provides packet write functions for HDMI library for T23+ chips
*/
#include "nvhdmipkt_class.h"
#include "nvhdmipkt_internal.h"
#include "hdmi_spec.h"
#include "class/clc871.h"
#include "ctrl/ctrl0073/ctrl0073specific.h"
#define NVHDMIPKT_C871_MAX_PKT_BYTES_AVI 21 // 3 bytes header + 18 bytes payload
extern void hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 packetLen,
NvU8 const *const pPacket);
/*
* translatePacketTypeC871
*/
static NvU32
translatePacketTypeC871(NVHDMIPKT_CLASS* pThis,
NVHDMIPKT_TYPE packetType)
{
NvU32 typeC871 = NVHDMIPKT_INVALID_PKT_TYPE; // initialize to an invalid type enum
switch (packetType)
{
case NVHDMIPKT_TYPE_AVI_INFOFRAME:
typeC871 = NVC871_SF_HDMI_INFO_IDX_AVI_INFOFRAME;
break;
case NVHDMIPKT_TYPE_GENERAL_CONTROL:
typeC871 = NVC871_SF_HDMI_INFO_IDX_GCP;
break;
case NVHDMIPKT_TYPE_AUDIO_INFOFRAME:
default:
NvHdmiPkt_Print(pThis, "ERROR - translatePacketType wrong packet type for class C871: %0x.",
packetType);
NvHdmiPkt_Assert(0);
break;
}
return typeC871;
}
/*
* hdmiWriteAviPacketC871
*/
static void
hdmiWriteAviPacketC871(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 packetLen,
NvU8 const *const pPacket)
{
NvU32 data = 0;
if (packetLen > NVHDMIPKT_C871_MAX_PKT_BYTES_AVI)
{
NvHdmiPkt_Print(pThis, "ERROR - input AVI packet length incorrect. Write will be capped to max allowable bytes");
NvHdmiPkt_Assert(0);
}
data = REG_RD32(pBaseReg, NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(head));
data = FLD_SET_DRF_NUM(C871, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB14, pPacket[17], data);
data = FLD_SET_DRF_NUM(C871, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB15, pPacket[18], data);
data = FLD_SET_DRF_NUM(C871, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB16, pPacket[19], data);
data = FLD_SET_DRF_NUM(C871, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB17, pPacket[20], data);
REG_WR32(pBaseReg, NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(head), data);
// the lower 17 bytes remain the same as in 9171 class, call 9171 packet write function to program them
hdmiWriteAviPacket9171(pThis,
pBaseReg,
head,
17, // HB0-2 and PB0-14
pPacket);
return;
}
/*
* hdmiWriteGeneralCtrlPacketC871
*/
static void
hdmiWriteGeneralCtrlPacketC871(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 packetLen,
NvU8 const *const pPacket)
{
NvU32 data = 0;
// orIndexer info is ignored.
data = REG_RD32(pBaseReg, NVC871_SF_HDMI_GCP_SUBPACK(head));
data = FLD_SET_DRF_NUM(C871, _SF_HDMI_GCP_SUBPACK, _SB0, pPacket[3], data);
data = FLD_SET_DRF_NUM(C871, _SF_HDMI_GCP_SUBPACK, _SB1, pPacket[4], data);
data = FLD_SET_DRF_NUM(C871, _SF_HDMI_GCP_SUBPACK, _SB2, pPacket[5], data);
REG_WR32(pBaseReg, NVC871_SF_HDMI_GCP_SUBPACK(head), data);
return;
}
/*
* hdmiPacketWriteC871
*/
static NVHDMIPKT_RESULT
hdmiPacketWriteC871(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 displayId,
NvU32 head,
NVHDMIPKT_TYPE packetType,
NVHDMIPKT_TC transmitControl,
NvU32 packetLen,
NvU8 const *const pPacketIn)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase;
NvU32 pktTypeC871 = pThis->translatePacketType(pThis, packetType);
NvU32 tc = pThis->translateTransmitControl(pThis, transmitControl);
NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS params = {0};
// packetIn can be of varying size. Use a fixed max size buffer for programing hw units to prevent out of bounds access
NvU8 pPacket[NVHDMIPKT_CTAIF_MAX_PKT_BYTES] = {0};
if (pBaseReg == 0 || head >= NVC871_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 ||
packetLen == 0 || pPacketIn == 0 || pktTypeC871 == NVHDMIPKT_INVALID_PKT_TYPE)
{
result = NVHDMIPKT_INVALID_ARG;
NvHdmiPkt_Print(pThis, "Invalid arg");
goto hdmiPacketWriteC871_exit;
}
if (packetLen > NVHDMIPKT_CTAIF_MAX_PKT_BYTES)
{
NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d Packet write will be capped to max allowable bytes", packetLen);
packetLen = NVHDMIPKT_CTAIF_MAX_PKT_BYTES;
NvHdmiPkt_Assert(0);
}
// input packet looks ok to use, copy over the bytes
NVMISC_MEMCPY(pPacket, pPacketIn, packetLen);
// acquire mutex
pThis->callback.acquireMutex(pThis->cbHandle);
// Disable this packet type.
pThis->hdmiWritePacketCtrl(pThis, pBaseReg, head, pktTypeC871, tc, NV_TRUE);
// write the packet
switch (pktTypeC871)
{
case NVC871_SF_HDMI_INFO_IDX_AVI_INFOFRAME:
pThis->hdmiWriteAviPacket(pThis, pBaseReg, head, packetLen, pPacket);
break;
case NVC871_SF_HDMI_INFO_IDX_GCP:
// Check whether the GCP packet is AVMute DISABLE or AvMute ENABLE
// Enable HDMI only on GCP unmute i.e. AVMUTE DISABLE
if (pPacket[HDMI_PKT_HDR_SIZE] == HDMI_GENCTRL_PACKET_MUTE_DISABLE)
{
// Enable HDMI.
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = (NvU8)subDevice;
params.displayId = displayId;
params.bEnable = NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "ERROR - RM call to enable hdmi ctrl failed.");
NvHdmiPkt_Assert(0);
result = NVHDMIPKT_FAIL;
}
}
pThis->hdmiWriteGeneralCtrlPacket(pThis, pBaseReg, head, packetLen, pPacket);
break;
default:
result = NVHDMIPKT_INVALID_ARG;
break;
}
// Enable this infoframe.
pThis->hdmiWritePacketCtrl(pThis, pBaseReg, head, pktTypeC871, tc, NV_FALSE);
// release mutex
pThis->callback.releaseMutex(pThis->cbHandle);
hdmiPacketWriteC871_exit:
return result;
}
NvBool
isInfoframeOffsetAvailable(NvU32* pBaseReg,
NvU32 head,
NvU32 requestedInfoframe)
{
NvU32 regAddr, regData = 0;
NvU32 ifIndex, size;
NvBool bResult = NV_TRUE;
for (ifIndex = 0; ifIndex < NVC871_SF_GENERIC_INFOFRAME_CTRL__SIZE_2; ifIndex++)
{
regAddr = NVC871_SF_GENERIC_INFOFRAME_CTRL(head, ifIndex);
regData = REG_RD32(pBaseReg, regAddr);
size = DRF_VAL(C871, _SF_GENERIC_INFOFRAME_CTRL, _SIZE, regData);
// if an infoframe is enabled and it's occupying the offset the requested infoframe would use,
// we cannot allow programming this requested infoframe
if (FLD_TEST_DRF(C871, _SF_GENERIC_INFOFRAME_CTRL, _ENABLE, _YES, regData) && (size > 0))
{
if ((ifIndex + size) > requestedInfoframe)
{
bResult = NV_FALSE;
break;
}
}
}
return bResult;
}
/*
* disableInfoframeC871
*/
NVHDMIPKT_RESULT
disableInfoframeC871(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 ifIndex)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_TIMEOUT;
NvU32 regAddr, regData;
regAddr = NVC871_SF_GENERIC_INFOFRAME_CTRL(head, ifIndex);
regData = REG_RD32(pBaseReg, regAddr);
// if infoframe is already disabled nothing to do
if (FLD_TEST_DRF(C871, _SF_GENERIC_INFOFRAME_CTRL, _ENABLE, _NO, regData))
{
return NVHDMIPKT_SUCCESS;
}
// engage timer callbacks to wait for HW register status change if timer callbacks are provided
NvBool bWaitForIdle = NV_FALSE;
if ((pThis->callback.setTimeout != 0) && (pThis->callback.checkTimeout != 0))
{
// wait until BUSY _NO if timer could be engaged successfully
bWaitForIdle = (pThis->callback.setTimeout(pThis->cbHandle, NVHDMIPKT_STATUS_READ_TIMEOUT_IN_us) == NV_TRUE);
}
// write ENABLE_NO
regData = FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_CTRL, _ENABLE, _NO, regData);
REG_WR32(pBaseReg, regAddr, regData);
// if timer callbacks are available poll for disable done
if (bWaitForIdle)
{
regData = REG_RD32(pBaseReg, regAddr);
while(FLD_TEST_DRF(C871, _SF_GENERIC_INFOFRAME_CTRL, _BUSY, _YES, regData))
{
if (pThis->callback.checkTimeout(pThis->cbHandle) == NV_TRUE)
{
// timeout waiting for infoframe to get disabled
NvHdmiPkt_Print(pThis, "MoreInfoframe: timeout waiting for infoframe to get disabled");
goto disableInfoframe_exit;
}
regData = REG_RD32(pBaseReg, regAddr);
}
NvHdmiPkt_Assert(FLD_TEST_DRF(C871, _SF_GENERIC_INFOFRAME_CTRL, _BUSY, _NO, regData));
}
else
{
NvHdmiPkt_Print(pThis, "MoreInfoframe: Clients must ideally provide timer callbacks to wait for enable/disable infoframes");
NvHdmiPkt_Assert(0);
}
result = NVHDMIPKT_SUCCESS;
disableInfoframe_exit:
return result;
}
/*
* programAdvancedInfoframeC871
*/
static NVHDMIPKT_RESULT
programAdvancedInfoframeC871(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
const ADVANCED_INFOFRAME *pInfoframe)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase;
if ((packetReg < NVHDMIPKT_TYPE_SHARED_GENERIC1) || (packetReg >= NVHDMIPKT_INVALID_PKT_TYPE))
{
return NVHDMIPKT_INVALID_ARG;
}
NvU32 ifIndex = packetReg - NVHDMIPKT_TYPE_SHARED_GENERIC1;
NvU32 ifNum, dwordNum;
NvU32 regAddr = 0;
NvU32 regData = 0;
NvU32 numOfInfoframes = pInfoframe->isLargeInfoframe ? (pInfoframe->numAdditionalInfoframes + 1) : 1;
if (NV_FALSE == isInfoframeOffsetAvailable(pBaseReg, head, ifIndex))
{
NvHdmiPkt_Print(pThis, "MoreInfoframe: Client requested overwriting an active infoframe");
}
// acquire mutex
pThis->callback.acquireMutex(pThis->cbHandle);
// disable and wait for infoframe HW unit to be ready
result = disableInfoframeC871(pThis, pBaseReg, head, ifIndex);
if (result != NVHDMIPKT_SUCCESS)
{
return result;
}
// write DATA_CTRL
regData = 0;
regAddr = NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL(head);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_DATA_CTRL, _OFFSET, ifIndex, regData);
REG_WR32(pBaseReg, regAddr, regData);
// send header + payload
NvHdmiPkt_Assert(pInfoframe->packetLen == (9 * sizeof(NvU32) * numOfInfoframes));
for (ifNum = 0; ifNum < numOfInfoframes; ifNum++)
{
const NvU8 *pPayload = pInfoframe->pPacket + (ifNum * 9 * sizeof(NvU32));
for (dwordNum = 0; dwordNum < 9; dwordNum++) // each infoframe is 9 DWORDs including the header
{
regData = 0;
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE0, pPayload[4*dwordNum + 0], regData);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE1, pPayload[4*dwordNum + 1], regData);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE2, pPayload[4*dwordNum + 2], regData);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE3, pPayload[4*dwordNum + 3], regData);
REG_WR32(pBaseReg, NVC871_SF_GENERIC_INFOFRAME_DATA(head), regData);
}
}
// write GENERIC_CONFIG
regData = 0;
regAddr = NVC871_SF_GENERIC_INFOFRAME_CONFIG(head, ifIndex);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_CONFIG, _FID, pInfoframe->flipId, regData);
if (pInfoframe->location == INFOFRAME_CTRL_LOC_LINE)
{
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_CONFIG, _LINE_ID, pInfoframe->lineNum, regData);
regData = (pInfoframe->lineIdReversed) ?
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_CONFIG, _LINE_ID_REVERSED, _YES, regData) :
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_CONFIG, _LINE_ID_REVERSED, _NO, regData);
}
regData = (pInfoframe->crcOverride) ?
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_CONFIG, _CRC_OVERRIDE, _YES, regData) :
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_CONFIG, _CRC_OVERRIDE, _NO, regData);
regData = (pInfoframe->matchFidMethodArmState) ?
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_CONFIG, _MTD_STATE_CTRL, _ARM, regData) : // send Infoframe at LOC when matching FID found at channel's FID method's ARM state
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_CONFIG, _MTD_STATE_CTRL, _ACT, regData); // default is when FID method is at ACTIVE state
// write reg
REG_WR32(pBaseReg, regAddr, regData);
// ENABLE_YES to GENERIC_CTRL
regData = 0;
regAddr = NVC871_SF_GENERIC_INFOFRAME_CTRL(head, ifIndex);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_CTRL, _RUN_MODE, pInfoframe->runMode, regData);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_CTRL, _LOC, pInfoframe->location, regData);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_CTRL, _OFFSET, ifIndex, regData);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_CTRL, _SIZE, pInfoframe->numAdditionalInfoframes, regData);
regData = FLD_SET_DRF (C871, _SF_GENERIC_INFOFRAME_CTRL, _ENABLE, _YES, regData);
// write reg
REG_WR32(pBaseReg, regAddr, regData);
NvHdmiPkt_Print(pThis, "MoreInfoframe: Sent infoframe of length %d bytes, transmit ctrl 0x%x at offset %d head=%x subdev=%d",
pInfoframe->packetLen, regData, ifIndex, head, subDevice);
// setup MSC_CTRL
regData = 0;
regAddr = NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL(head);
regData = pInfoframe->winMethodCyaBroadcast ?
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_MISC_CTRL, _WIN_CHN_SEL, _PUBLIC, regData) :
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_MISC_CTRL, _WIN_CHN_SEL, _PRIVATE, regData) ;
regData = pInfoframe->highAudioPriority ?
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_MISC_CTRL, _AUDIO_PRIORITY, _HIGH, regData) :
FLD_SET_DRF(C871, _SF_GENERIC_INFOFRAME_MISC_CTRL, _AUDIO_PRIORITY, _LOW, regData);
// write reg
REG_WR32(pBaseReg, regAddr, regData);
// release mutex
pThis->callback.releaseMutex(pThis->cbHandle);
return result;
}
/*
* hdmiWritePacketCtrlC871
*/
static NVHDMIPKT_RESULT
hdmiWritePacketCtrlLegacyPktsC871(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 pktTypeC871,
NvU32 transmitControl,
NvBool bDisable)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_INVALID_ARG;
NvU32 regOffset = 0;
NvU32 hdmiCtrl = 0;
if (pBaseReg == 0 || head >= NVC871_SF_HDMI_INFO_CTRL__SIZE_1)
{
return result;
}
switch (pktTypeC871)
{
case NVC871_SF_HDMI_INFO_IDX_AVI_INFOFRAME:
case NVC871_SF_HDMI_INFO_IDX_GCP:
regOffset = NVC871_SF_HDMI_INFO_CTRL(head, pktTypeC871);
hdmiCtrl = REG_RD32(pBaseReg, regOffset);
hdmiCtrl = (bDisable == NV_TRUE) ?
(FLD_SET_DRF(C871, _SF_HDMI_INFO_CTRL, _ENABLE, _DIS, hdmiCtrl)) :
(transmitControl);
REG_WR32(pBaseReg, regOffset, hdmiCtrl);
result = NVHDMIPKT_SUCCESS;
break;
default:
NvHdmiPkt_Assert(0 && "Invalid pkt type!");
break;
}
return result;
}
/*
* hdmiPacketReadC871
*/
static NVHDMIPKT_RESULT
hdmiPacketReadC871(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
NvU32 bufferLen,
NvU8 *const pOutPktBuffer)
{
NvU32 ifIndex, ifNum, dw, regAddr, regData, numOfInfoframes;
NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase;
if ((packetReg < NVHDMIPKT_TYPE_SHARED_GENERIC1) || (packetReg >= NVHDMIPKT_INVALID_PKT_TYPE))
{
return NVHDMIPKT_INVALID_ARG;
}
ifIndex = packetReg - NVHDMIPKT_TYPE_SHARED_GENERIC1;
// write infoframe Offset to DATA_CTRL
regData = 0;
regAddr = NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL(head);
regData = FLD_SET_DRF_NUM(C871, _SF_GENERIC_INFOFRAME_DATA_CTRL, _OFFSET, ifIndex, regData);
REG_WR32(pBaseReg, regAddr, regData);
// read size of infoframe programmed at this Offset
regAddr = NVC871_SF_GENERIC_INFOFRAME_CTRL(head, ifIndex);
regData = REG_RD32(pBaseReg, regAddr);
numOfInfoframes = DRF_VAL(C871, _SF_GENERIC_INFOFRAME_CTRL, _SIZE, regData) + 1; // total size is 1 more than SIZE field
NvU32 remainingBufSize = bufferLen;
NvU8 *pBuffer = pOutPktBuffer;
for (ifNum = 0; ifNum < numOfInfoframes; ifNum++)
{
if (remainingBufSize == 0)
{
NvHdmiPkt_Assert(0 && "MoreInfoframe: Buffer size insufficient to copy read packet data");
result = NVHDMIPKT_INSUFFICIENT_BUFFER;
break;
}
// a temporary buffer to read a 36 byte chunk of this infoframe
NvU8 pktBytes[9 * sizeof(NvU32)];
for (dw = 0; dw < 9; dw++) // each infoframe is 9 DWORDs including the header
{
regData = REG_RD32(pBaseReg, NVC871_SF_GENERIC_INFOFRAME_DATA(head));
pktBytes[dw*4 + 0] = DRF_VAL(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE0, regData);
pktBytes[dw*4 + 1] = DRF_VAL(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE1, regData);
pktBytes[dw*4 + 2] = DRF_VAL(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE2, regData);
pktBytes[dw*4 + 3] = DRF_VAL(C871, _SF_GENERIC_INFOFRAME_DATA, _BYTE3, regData);
}
NvU32 bytesCopied = (remainingBufSize > 36) ? 36 : remainingBufSize;
NVMISC_MEMCPY(pBuffer, &pktBytes, bytesCopied);
// move out buffer ptr by the copied bytes
pBuffer += bytesCopied;
// reduce remaining buffer size by the amount we copied
remainingBufSize = remainingBufSize - bytesCopied;
}
return result;
}
/*
* hdmiPacketCtrlC871
*/
static NVHDMIPKT_RESULT
hdmiPacketCtrlC871(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 displayId,
NvU32 head,
NVHDMIPKT_TYPE packetType,
NVHDMIPKT_TC transmitControl)
{
NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase;
NvU32 tc = pThis->translateTransmitControl(pThis, transmitControl);
if ((pBaseReg == 0) || (head >= NVC871_SF_GENERIC_INFOFRAME_CTRL__SIZE_1) ||
(packetType >= NVHDMIPKT_INVALID_PKT_TYPE))
{
return NVHDMIPKT_INVALID_ARG;
}
if ((packetType == NVHDMIPKT_TYPE_VENDOR_SPECIFIC_INFOFRAME) ||
(packetType == NVHDMIPKT_TYPE_GENERIC))
{
NvHdmiPkt_Print(pThis, "Generic and VSI registers removed in C871 HW. Call NvHdmiPkt_SetupAdvancedInfoframe to use one of the generic registers!");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_INVALID_ARG;
}
if (packetType >= NVHDMIPKT_TYPE_SHARED_GENERIC1 && packetType <= NVHDMIPKT_TYPE_SHARED_GENERIC10)
{
// client is only expected to call packet ctrl interface to disable the infoframe, no support for other packet ctrl options
// to reprogram/change run mode of a packet, call NvHdmiPkt_SetupAdvancedInfoframe interface
NvHdmiPkt_Assert(FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _ENABLE, _DIS, transmitControl));
return disableInfoframeC871(pThis, pBaseReg, head, (packetType - NVHDMIPKT_TYPE_SHARED_GENERIC1));
}
NvU32 pktTypeC871 = pThis->translatePacketType(pThis, packetType);
return pThis->hdmiWritePacketCtrl(pThis, pBaseReg, head, pktTypeC871, tc, NV_FALSE);
}
// non-HW - class utility/maintenance functions
/*
* hdmiConstructorC871
*/
NvBool
hdmiConstructorC871(NVHDMIPKT_CLASS* pThis)
{
NvBool result = NV_TRUE;
return result;
}
/*
* hdmiDestructorC871
*/
void
hdmiDestructorC871(NVHDMIPKT_CLASS* pThis)
{
return;
}
/*
* initializeHdmiPktInterfaceC871
*/
void
initializeHdmiPktInterfaceC871(NVHDMIPKT_CLASS* pClass)
{
// Update SF_USER data
pClass->dispSfUserClassId = NVC871_DISP_SF_USER;
pClass->dispSfUserSize = sizeof(NvC871DispSfUserMap);
pClass->translatePacketType = translatePacketTypeC871;
pClass->hdmiWriteAviPacket = hdmiWriteAviPacketC871;
pClass->hdmiWriteGeneralCtrlPacket = hdmiWriteGeneralCtrlPacketC871;
pClass->hdmiPacketWrite = hdmiPacketWriteC871;
pClass->hdmiPacketCtrl = hdmiPacketCtrlC871;
pClass->hdmiWritePacketCtrl = hdmiWritePacketCtrlLegacyPktsC871;
// generic infoframe (shareable by DP and HDMI)
pClass->hdmiPacketRead = hdmiPacketReadC871;
pClass->programAdvancedInfoframe = programAdvancedInfoframeC871;
}

204
src/common/modeset/hdmipacket/nvhdmipkt_C971.c Normal file
View File

@@ -0,0 +1,204 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_C971.c
*
*/
#include "nvhdmipkt_common.h"
/*
* Purpose: Provides packet write functions for HDMI library for NVD5.0 chips
*/
#include "nvhdmipkt_class.h"
#include "nvhdmipkt_internal.h"
#include "class/clc971.h"
/*
* programAdvancedInfoframeC971
*/
static NVHDMIPKT_RESULT
programAdvancedInfoframeC971(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
const ADVANCED_INFOFRAME *pInfoframe)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase;
if ((packetReg < NVHDMIPKT_TYPE_SHARED_GENERIC1) || (packetReg >= NVHDMIPKT_INVALID_PKT_TYPE))
{
return NVHDMIPKT_INVALID_ARG;
}
NvU32 ifIndex = packetReg - NVHDMIPKT_TYPE_SHARED_GENERIC1;
NvU32 ifNum, dwordNum;
NvU32 regAddr = 0;
NvU32 regData = 0;
NvU32 numOfInfoframes = pInfoframe->isLargeInfoframe ? (pInfoframe->numAdditionalInfoframes + 1) : 1;
if (NV_FALSE == isInfoframeOffsetAvailable(pBaseReg, head, ifIndex))
{
NvHdmiPkt_Print(pThis, "MoreInfoframe: Client requested overwriting an active infoframe");
}
NvHdmiPkt_Assert((pInfoframe->crcOverride == 0) &&
"CRC Override bit not supported in Nvd 5.0");
NvHdmiPkt_Assert((pInfoframe->winMethodCyaBroadcast == 0) &&
"window channel priv reg control not supported in Nvd5.0");
NvHdmiPkt_Assert((pInfoframe->location != INFOFRAME_CTRL_LOC_LOADV) &&
"LoadV location not supported in Nvd5.0");
// acquire mutex
pThis->callback.acquireMutex(pThis->cbHandle);
// disable and wait for infoframe HW unit to be ready
// Note, C971 HW provides Clear option for SENT field, so we don't have to disable
// just to make sure new data sending is successful. But we disable Infoframe
// before reprogramming to avoid corrupting a payload that is actively being sent
result = disableInfoframeC871(pThis, pBaseReg, head, ifIndex);
if (result != NVHDMIPKT_SUCCESS)
{
return result;
}
// write SENT bit to clear the SENT field
regAddr = NVC971_SF_GENERIC_INFOFRAME_CTRL(head, ifIndex);
regData = REG_RD32(pBaseReg, regAddr);
regData = FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_CTRL, _SENT, _CLEAR, regData);
REG_WR32(pBaseReg, regAddr, regData);
// write DATA_CTRL
regData = 0;
regAddr = NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL(head);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_DATA_CTRL, _OFFSET, ifIndex, regData);
REG_WR32(pBaseReg, regAddr, regData);
// send header + payload
NvHdmiPkt_Assert(pInfoframe->packetLen == (9 * sizeof(NvU32) * numOfInfoframes));
for (ifNum = 0; ifNum < numOfInfoframes; ifNum++)
{
const NvU8 *pPayload = pInfoframe->pPacket + (ifNum * 9 * sizeof(NvU32));
for (dwordNum = 0; dwordNum < 9; dwordNum++) // each infoframe is 9 DWORDs including the header
{
regData = 0;
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_DATA, _BYTE0, pPayload[4*dwordNum + 0], regData);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_DATA, _BYTE1, pPayload[4*dwordNum + 1], regData);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_DATA, _BYTE2, pPayload[4*dwordNum + 2], regData);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_DATA, _BYTE3, pPayload[4*dwordNum + 3], regData);
REG_WR32(pBaseReg, NVC971_SF_GENERIC_INFOFRAME_DATA(head), regData);
}
}
// write GENERIC_CONFIG
regData = 0;
regAddr = NVC971_SF_GENERIC_INFOFRAME_CONFIG(head, ifIndex);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_CONFIG, _FID, pInfoframe->flipId, regData);
if (pInfoframe->location == INFOFRAME_CTRL_LOC_LINE)
{
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_CONFIG, _LINE_ID, pInfoframe->lineNum, regData);
regData = (pInfoframe->lineIdReversed) ?
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_CONFIG, _LINE_ID_REVERSED, _YES, regData) :
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_CONFIG, _LINE_ID_REVERSED, _NO, regData);
}
regData = (pInfoframe->asSdpOverride) ?
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_CONFIG, _AS_SDP_OVERRIDE_EN, _YES, regData) :
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_CONFIG, _AS_SDP_OVERRIDE_EN, _NO, regData);
regData = (pInfoframe->matchFidMethodArmState) ?
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_CONFIG, _MTD_STATE_CTRL, _ARM, regData) :
// send Infoframe at LOC when matching FID found at channel's FID method's ARM state
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_CONFIG, _MTD_STATE_CTRL, _ACT, regData);
// default is when FID method is at ACTIVE state
// write reg
REG_WR32(pBaseReg, regAddr, regData);
// ENABLE_YES to GENERIC_CTRL
regData = 0;
regAddr = NVC971_SF_GENERIC_INFOFRAME_CTRL(head, ifIndex);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_CTRL, _RUN_MODE, pInfoframe->runMode, regData);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_CTRL, _LOC, pInfoframe->location, regData);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_CTRL, _OFFSET, ifIndex, regData);
regData = FLD_SET_DRF_NUM(C971, _SF_GENERIC_INFOFRAME_CTRL, _SIZE, pInfoframe->numAdditionalInfoframes, regData);
regData = FLD_SET_DRF (C971, _SF_GENERIC_INFOFRAME_CTRL, _ENABLE, _YES, regData);
// write reg
REG_WR32(pBaseReg, regAddr, regData);
NvHdmiPkt_Print(pThis, "MoreInfoframe: Sent infoframe of length %d bytes, transmit ctrl 0x%x at offset %d head=%x subdev=%d",
pInfoframe->packetLen, regData, ifIndex, head, subDevice);
// setup MSC_CTRL
regData = 0;
regAddr = NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL(head);
regData = pInfoframe->highAudioPriority ?
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_MISC_CTRL, _AUDIO_PRIORITY, _HIGH, regData) :
FLD_SET_DRF(C971, _SF_GENERIC_INFOFRAME_MISC_CTRL, _AUDIO_PRIORITY, _LOW, regData);
// write reg
REG_WR32(pBaseReg, regAddr, regData);
// release mutex
pThis->callback.releaseMutex(pThis->cbHandle);
return result;
}
// non-HW - class utility/maintenance functions
/*
* hdmiConstructorC971
*/
NvBool
hdmiConstructorC971(NVHDMIPKT_CLASS* pThis)
{
NvBool result = NV_TRUE;
return result;
}
/*
* hdmiDestructorC971
*/
void
hdmiDestructorC971(NVHDMIPKT_CLASS* pThis)
{
return;
}
/*
* initializeHdmiPktInterfaceC971
*/
void
initializeHdmiPktInterfaceC971(NVHDMIPKT_CLASS* pClass)
{
// Update SF_USER data
pClass->dispSfUserClassId = NVC971_DISP_SF_USER;
pClass->dispSfUserSize = sizeof(NvC971DispSfUserMap);
// generic infoframe (shareable by DP and HDMI)
pClass->programAdvancedInfoframe = programAdvancedInfoframeC971;
}

65
src/common/modeset/hdmipacket/nvhdmipkt_CA71.c Normal file
View File

@@ -0,0 +1,65 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_CA71.c
*
*/
#include "nvhdmipkt_common.h"
/*
* Purpose: Provides packet write functions for HDMI library for NVD5.0 chips
*/
#include "nvhdmipkt_class.h"
#include "nvhdmipkt_internal.h"
#include "class/clca71.h"
// non-HW - class utility/maintenance functions
/*
* hdmiConstructorCA71
*/
NvBool
hdmiConstructorCA71(NVHDMIPKT_CLASS* pThis)
{
NvBool result = NV_TRUE;
return result;
}
/*
* hdmiDestructorCA71
*/
void
hdmiDestructorCA71(NVHDMIPKT_CLASS* pThis)
{
return;
}
/*
* initializeHdmiPktInterfaceCA71
*/
void
initializeHdmiPktInterfaceCA71(NVHDMIPKT_CLASS* pClass)
{
// Update SF_USER data
pClass->dispSfUserClassId = NVCA71_DISP_SF_USER;
pClass->dispSfUserSize = sizeof(NvCA71DispSfUserMap);
}

18
src/common/modeset/hdmipacket/nvhdmipkt_class.h
View File

@@ -48,6 +48,9 @@ typedef enum
NVHDMIPKT_C571_CLASS = 6, // TU102
NVHDMIPKT_C671_CLASS = 7, // GA102, T234D
NVHDMIPKT_C771_CLASS = 8, // AD10X
NVHDMIPKT_C871_CLASS = 9, // T239
NVHDMIPKT_C971_CLASS = 10, // NVD5.0
NVHDMIPKT_CA71_CLASS = 11,
NVHDMIPKT_INVALID_CLASS // Not to be used by client, and always the last entry here.
} NVHDMIPKT_CLASS_ID;
@@ -85,6 +88,21 @@ struct tagNVHDMIPKT_CLASS
NvU32 packetLen,
NvU8 const *const pPacket);
NVHDMIPKT_RESULT
(*hdmiPacketRead) (NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
NvU32 bufferLen,
NvU8 *const pOutPktBuffer);
NVHDMIPKT_RESULT
(*programAdvancedInfoframe) (NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
const ADVANCED_INFOFRAME* pInfoframe);
// HW functions - that read/write registers
NvBool
(*hdmiReadPacketStatus) (NVHDMIPKT_CLASS* pThis,

15
src/common/modeset/hdmipacket/nvhdmipkt_common.h
View File

@@ -51,7 +51,9 @@ typedef struct tagNVHDMIPKT_MEM_MAP NVHDMIPKT_MEM_MAP;
#define REG_WR32(reg, offset, data) ((*(((volatile NvU32*)(reg)) + ((offset)/4))) = (data))
#define NVHDMIPKT_INVALID_SUBDEV (0xFFFFFFFF)
#if !defined (WINNT) && !defined(NVHDMIPKT_NVKMS)
#define NVHDMIPKT_DONT_USE_TIMER
#endif
#define NVHDMIPKT_STATUS_READ_TIMEOUT_IN_us (1*1000*1000) /* us - micro second */
// Disp SF User memory map and handle structure
@@ -110,4 +112,17 @@ extern NVHDMIPKT_RESULT hdmiClearFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId);
extern NVHDMIPKT_RESULT hdmiPacketReadDummy(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
NvU32 bufferLen,
NvU8 *const pOutPktBuffer);
extern NVHDMIPKT_RESULT programAdvancedInfoframeDummy(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
NvU32 head,
NVHDMIPKT_TYPE packetReg,
const ADVANCED_INFOFRAME* pInfoframe);
#endif //_NVHDMIPKT_COMMON_H_

16
src/common/modeset/hdmipacket/nvhdmipkt_internal.h
View File

@@ -45,6 +45,9 @@ extern void initializeHdmiPktInterface9571(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterfaceC371(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterfaceC671(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterfaceC771(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterfaceC871(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterfaceC971(NVHDMIPKT_CLASS*);
extern void initializeHdmiPktInterfaceCA71(NVHDMIPKT_CLASS*);
extern NvBool hdmiConstructor0073(NVHDMIPKT_CLASS*);
extern void hdmiDestructor0073 (NVHDMIPKT_CLASS*);
@@ -62,5 +65,18 @@ extern NvBool hdmiConstructorC671(NVHDMIPKT_CLASS*);
extern void hdmiDestructorC671 (NVHDMIPKT_CLASS*);
extern NvBool hdmiConstructorC771(NVHDMIPKT_CLASS*);
extern void hdmiDestructorC771 (NVHDMIPKT_CLASS*);
extern NvBool hdmiConstructorC871(NVHDMIPKT_CLASS*);
extern void hdmiDestructorC871 (NVHDMIPKT_CLASS*);
extern NvBool isInfoframeOffsetAvailable(NvU32* pBaseReg,
NvU32 head,
NvU32 requestedInfoframe);
extern NVHDMIPKT_RESULT disableInfoframeC871(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 ifIndex);
extern NvBool hdmiConstructorC971(NVHDMIPKT_CLASS*);
extern void hdmiDestructorC971 (NVHDMIPKT_CLASS*);
extern NvBool hdmiConstructorCA71(NVHDMIPKT_CLASS*);
extern void hdmiDestructorCA71 (NVHDMIPKT_CLASS*);
#endif //_NVHDMIPKT_INTERNAL_H_

11
src/common/modeset/timing/nvt_cvt.c
View File

@@ -49,7 +49,7 @@ const NvU32 NVT_CVT_H_SYNC_PER = 8; // HSYNC percentage (8%)
const NvU32 NVT_CVT_RB_HBLANK_CELLS = 20; // 160 fixed hblank for RB
const NvU32 NVT_CVT_RB_HFPORCH_CELLS = 6; // 48 fixed hfporch for RB
const NvU32 NVT_CVT_RB_HSYNCW_CELLS = 4; // 32 fixed hsyncwidth for RB
const NvU32 NVT_CVT_RB_MIN_VBLANK = 23; // 460 lines (or 460 us?) [1000000:460 = 50000:23]
const NvU32 NVT_CVT_RB_MIN_VBLANK = 23; // 460 line s (or 460 us?) [1000000:460 = 50000:23]
const NvU32 NVT_CVT_MIN_V_BPORCH = 6; // Minimum vertical back porch.
@@ -154,6 +154,7 @@ NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
pT->etc.status = NVT_STATUS_CVT;
// For 1, 2, 3, 4 in Computation of common parameters
// H_PIXELS_RND = ROUNDDOWN(H_PIXELS / CELL_GRAN_RND,0) * CELL_GRAN_RND
if ((width % NVT_CVT_CELL_GRAN)!=0)
{
@@ -178,7 +179,8 @@ NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
dwIdealDutyCycle_DEN = dwHPeroidEstimate_DEN;
dwIdealDutyCycle_NUM = NVT_CVT_C_PRIME * dwHPeroidEstimate_DEN - NVT_CVT_M_PRIME_D_20 * dwHPeriodEstimate_NUM;
if (dwIdealDutyCycle_NUM < dwIdealDutyCycle_DEN * 20)
if (dwIdealDutyCycle_NUM < dwIdealDutyCycle_DEN * 20 ||
(NVT_CVT_C_PRIME * dwHPeroidEstimate_DEN < NVT_CVT_M_PRIME_D_20 * dwHPeriodEstimate_NUM))
{
dwIdealDutyCycle_NUM=20;
dwIdealDutyCycle_DEN=1;
@@ -211,7 +213,8 @@ NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
pT->VFrontPorch = (NvU16)(NVT_CVT_V_PORCH);
pT->VSyncWidth = getCVTVSync(dwXCells * NVT_CVT_CELL_GRAN, height);
pT->pclk = dwPClk;
pT->pclk = dwPClk;
pT->pclk1khz = (dwPClk << 3) + (dwPClk << 1); // *10
pT->HSyncPol = NVT_H_SYNC_NEGATIVE;
pT->VSyncPol = NVT_V_SYNC_POSITIVE;
@@ -411,6 +414,7 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10
pT->VSyncWidth = NVT_CVT_RB2_V_SYNC_WIDTH;
pT->VFrontPorch = (NvU16)(act_vbi_lines - NVT_CVT_RB2_V_SYNC_WIDTH - NVT_CVT_RB2_MIN_V_BPORCH);
pT->pclk = (act_pixel_freq_khz + 5) / 10; //convert to 10Khz
pT->pclk1khz = act_pixel_freq_khz;
pT->HSyncPol = NVT_H_SYNC_POSITIVE;
pT->VSyncPol = NVT_V_SYNC_NEGATIVE;
pT->HBorder = pT->VBorder = 0; // not supported
@@ -610,6 +614,7 @@ NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width,
pT->VSyncWidth = NVT_CVT_RB3_V_SYNC_WIDTH;
pT->VFrontPorch = (NvU16)(act_v_blank_lines - NVT_CVT_RB3_V_SYNC_WIDTH - v_back_porch);
pT->pclk = ((NvU32)act_pixel_freq_khz + 5) / 10; //convert to 10Khz
pT->pclk1khz = act_pixel_freq_khz;
pT->HSyncPol = NVT_H_SYNC_POSITIVE;
pT->VSyncPol = NVT_V_SYNC_NEGATIVE;
pT->HBorder = pT->VBorder = 0; // not supported

14
src/common/modeset/timing/nvt_displayid20.c
View File

@@ -1552,9 +1552,9 @@ parseDisplayId20Timing7Descriptor(
pDescriptor = (const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *)pVoidDescriptor;
// pclk is in 1Khz
pTiming->pclk = ((pDescriptor->pixel_clock[2] << 16 |
pDescriptor->pixel_clock[1] << 8 |
pDescriptor->pixel_clock[0]) + 1);
pTiming->pclk1khz = ((pDescriptor->pixel_clock[2] << 16 |
pDescriptor->pixel_clock[1] << 8 |
pDescriptor->pixel_clock[0]) + 1);
pTiming->HBorder = 0;
pTiming->VBorder = 0;
@@ -1637,17 +1637,17 @@ parseDisplayId20Timing7Descriptor(
pTiming->etc.aspect = 0;
}
pTiming->etc.rr = NvTiming_CalcRR(pTiming->pclk,
pTiming->etc.rr = NvTiming_CalcRR(pTiming->pclk1khz,
pTiming->interlaced,
pTiming->HTotal,
pTiming->VTotal) / 10;
pTiming->etc.rrx1k = NvTiming_CalcRRx1k(pTiming->pclk,
pTiming->etc.rrx1k = NvTiming_CalcRRx1k(pTiming->pclk1khz,
pTiming->interlaced,
pTiming->HTotal,
pTiming->VTotal) / 10;
// pclk change to 10k
pTiming->pclk /= 10;
// pclk change to 10kHz
pTiming->pclk = pTiming->pclk1khz / 10;
pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count);

8
src/common/modeset/timing/nvt_dmt.c
View File

@@ -37,13 +37,13 @@ PUSH_SEGMENTS
// DMT table 2-1
// Macro to declare a TIMING initializer for given parameters without border
#define DMT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rr,pclk,id) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT,id),"VESA DMT"}}
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,((pclk<<3)+(pclk<<1)),{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT,id),"VESA DMT"}}
#define DMTRB_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rr,pclk,id) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT_RB,id),"VESA DMT/RB"}}
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,((pclk<<3)+(pclk<<1)),{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT_RB,id),"VESA DMT/RB"}}
#define DMTRB_2_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rr,pclk,id) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT_RB_2,id),"VESA DMT/RB2"}}
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,((pclk<<3)+(pclk<<1)),{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT_RB_2,id),"VESA DMT/RB2"}}
DATA_SEGMENT(PAGE_DATA)
@@ -56,7 +56,7 @@ static NVT_TIMING DMT[] =
DMT_TIMING ( 720, 36, 72, 936,'-', 400, 1, 3, 446,'+', 85, 3550, 0x03),
DMT_TIMING ( 640, 8, 96, 800,'-', 480, 2, 2, 525,'-', 60, 2518, 0x04),
// 640x480x72Hz (VESA) - this entry have borders
{640,8,16,40,832,NVT_H_SYNC_NEGATIVE,480,8,1,3,520,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,3150,{0,72,72000,0,1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT,5),"VESA DMT"}},
{640,8,16,40,832,NVT_H_SYNC_NEGATIVE,480,8,1,3,520,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,3150,31500,{0,72,72000,0,1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT,5),"VESA DMT"}},
DMT_TIMING ( 640, 16, 64, 840,'-', 480, 1, 3, 500,'-', 75, 3150, 0x06),
DMT_TIMING ( 640, 56, 56, 832,'-', 480, 1, 3, 509,'-', 85, 3600, 0x07),
DMT_TIMING ( 800, 24, 72,1024,'+', 600, 1, 2, 625,'+', 56, 3600, 0x08),

138
src/common/modeset/timing/nvt_dsc_pps.c
View File

@@ -33,6 +33,7 @@
#include "nvt_dsc_pps.h"
#include "nvmisc.h"
#include "displayport/displayport.h"
#include "displayport/displayport2x.h"
#include "nvctassert.h"
#include <stddef.h>
@@ -104,6 +105,7 @@ typedef struct
NvU32 multi_tile; // 1 = Multi-tile architecture, 0 = dsc single or dual mode without multi-tile
NvU32 peak_throughput_mode0; // peak throughput supported by the sink for 444 and simple 422 modes.
NvU32 peak_throughput_mode1; // peak throughput supported by the sink for native 422 and 420 modes.
NvU32 eDP; // 1 = connector type is eDP, 0 otherwise.
} DSC_INPUT_PARAMS;
//output pps parameters after calculation
@@ -989,7 +991,6 @@ DSC_PpsCalcBase
out->pps_identifier = 0;
ENUM3_CHECK("bits_per_component", in->bits_per_component, 8, 10, 12);
out->bits_per_component = in->bits_per_component;
RANGE_CHECK("bits_per_pixelx16", in->bits_per_pixel, 8 * BPP_UNIT, (out->bits_per_component * 3) * BPP_UNIT);
out->bits_per_pixel = in->bits_per_pixel;
RANGE_CHECK("linebuf_depth", in->linebuf_depth, DSC_DECODER_LINE_BUFFER_BIT_DEPTH_MIN, DSC_DECODER_LINE_BUFFER_BIT_DEPTH_MAX);
out->linebuf_depth = in->linebuf_depth;
@@ -1598,22 +1599,74 @@ DSC_PpsCheckSliceHeight(DSC_OUTPUT_PARAMS *out)
* NVT_STATUS_ERR if unsuccessful;
*/
static NVT_STATUS
Dsc_PpsCalcHeight(DSC_OUTPUT_PARAMS *out)
Dsc_PpsCalcHeight
(
const DSC_INPUT_PARAMS *in,
DSC_OUTPUT_PARAMS *out
)
{
if(out->slice_height == 0)
//
// From Blackwell and later, eDP we will try to use smallest slice height
// if client has not asked for a specific slice height. Multi-tile is enabled
// from Blackwell and so here we will use that condition for deciding on
// slice height calculation. Minimum slice height will help with power savings
// when eDP1.5 Selective Update is enabled.
//
if (in->multi_tile && in->eDP)
{
NvU32 i;
for (i = 1 ; i <= 16; i++)
if (out->slice_height == 0U)
{
out->slice_height = out->pic_height / i;
if (out->pic_height != out->slice_height * i )
continue;
// Minimum area of slice should be 15000 as per VESA spec
out->slice_height = (NvU32)NV_CEIL(15000U,(out->slice_width));
while (out->pic_height > out->slice_height)
{
if (out->pic_height % out->slice_height == 0U)
{
if (DSC_PpsCheckSliceHeight(out) == NVT_STATUS_SUCCESS)
{
return NVT_STATUS_SUCCESS;
}
else
{
out->slice_height++;
}
}
else
{
out->slice_height++;
}
if (DSC_PpsCheckSliceHeight(out) == NVT_STATUS_SUCCESS)
return NVT_STATUS_SUCCESS;
if (out->pic_height == out->slice_height)
{
if(DSC_PpsCheckSliceHeight(out) == NVT_STATUS_SUCCESS)
{
return NVT_STATUS_SUCCESS;
}
else
{
return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR;
}
}
}
}
}
else
{
if(out->slice_height == 0)
{
NvU32 i;
for (i = 1 ; i <= 16; i++)
{
out->slice_height = out->pic_height / i;
if (out->pic_height != out->slice_height * i )
continue;
if (DSC_PpsCheckSliceHeight(out) == NVT_STATUS_SUCCESS)
return NVT_STATUS_SUCCESS;
}
// Error! can't find valid slice_height
return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR;
}
// Error! can't find valid slice_height
return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR;
}
RANGE_CHECK("slice_height", out->slice_height, 8, out->pic_height);
@@ -1677,7 +1730,7 @@ DSC_PpsCalc
if (ret != NVT_STATUS_SUCCESS) return ret;
ret = DSC_PpsCalcRcInitValue(out);
if (ret != NVT_STATUS_SUCCESS) return ret;
ret = Dsc_PpsCalcHeight(out);
ret = Dsc_PpsCalcHeight(in, out);
if (ret != NVT_STATUS_SUCCESS) return ret;
ret = DSC_PpsCalcRcParam(out);
return ret;
@@ -1842,9 +1895,14 @@ _validateInput
(pDscInfo->forcedDscParams.sliceCount != 1U) &&
(pDscInfo->forcedDscParams.sliceCount != 2U) &&
(pDscInfo->forcedDscParams.sliceCount != 4U) &&
(pDscInfo->forcedDscParams.sliceCount != 8U))
(pDscInfo->forcedDscParams.sliceCount != 8U) &&
(pDscInfo->forcedDscParams.sliceCount != 10U) &&
(pDscInfo->forcedDscParams.sliceCount != 12U) &&
(pDscInfo->forcedDscParams.sliceCount != 16U) &&
(pDscInfo->forcedDscParams.sliceCount != 20U) &&
(pDscInfo->forcedDscParams.sliceCount != 24U))
{
// ERROR - Forced Slice Count has to be 1/2/4/8.
// ERROR - Forced Slice Count has to be 1/2/4/8/10/12/16/20/24.
return NVT_STATUS_DSC_SLICE_ERROR;
}
@@ -2013,7 +2071,7 @@ _validateInput
return NVT_STATUS_INVALID_PARAMETER;
}
if (!IS_VALID_LINKBW(pWARData->dpData.linkRateHz / DP_LINK_BW_FREQ_MULTI_MBPS))
if (!IS_VALID_DP2_X_LINKBW(pWARData->dpData.linkRateHz))
{
// ERROR - Incorrect DP Link rate info sent with WAR data
return NVT_STATUS_INVALID_PARAMETER;
@@ -2084,7 +2142,6 @@ DSC_GeneratePPSWithSliceCountMask
NvU32 sliceArrayCount;
NvU32 i;
DSC_INFO localDscInfo;
NvU32* ppsOut = NULL;
NVT_STATUS status;
DSC_GENERATE_PPS_OPAQUE_WORKAREA scratchBuffer;
@@ -2166,27 +2223,19 @@ DSC_GeneratePPSWithSliceCountMask
//
if (possibleSliceCountMask)
{
NvU32 minSliceCountOut = 0;
localDscInfo = *pDscInfo;
for(i = 0U ; i < sliceArrayCount; i++)
{
if (possibleSliceCountMask & DSC_SliceCountMaskforSliceNum(validSliceNum[i]))
{
ppsOut = NULL;
// Use the forced bits per pixel, if any
NvU32 bitsPerPixelX16Local = *pBitsPerPixelX16;
localDscInfo.forcedDscParams.sliceCount = validSliceNum[i];
if (localDscInfo.forcedDscParams.sliceCount == minSliceCount)
{
//
// We need to return PPS with minimum slice count if client
// has not forced any slice count even though we generate
// pps with all other possible slice counts to validate them.
//
ppsOut = pps;
}
status = DSC_GeneratePPS(&localDscInfo, pModesetInfo, pWARData,
availableBandwidthBitsPerSecond, &scratchBuffer,
ppsOut, pBitsPerPixelX16);
NULL, &bitsPerPixelX16Local);
if (status == NVT_STATUS_SUCCESS)
{
//
@@ -2200,9 +2249,30 @@ DSC_GeneratePPSWithSliceCountMask
// corresponding bit index.
//
validSliceCountMask |= NVBIT32((validSliceNum[i]) - 1U);
if ((minSliceCountOut == 0) || (minSliceCountOut > validSliceNum[i]))
{
minSliceCountOut = validSliceNum[i];
}
}
}
}
if (minSliceCountOut != 0)
{
//
// We need to return PPS with minimum slice count if client
// has not forced any slice count even though we generate
// pps with all other possible slice counts to validate them.
//
localDscInfo.forcedDscParams.sliceCount = minSliceCountOut;
status = DSC_GeneratePPS(&localDscInfo, pModesetInfo, pWARData,
availableBandwidthBitsPerSecond, &scratchBuffer,
pps, pBitsPerPixelX16);
if (status != NVT_STATUS_SUCCESS)
{
return status;
}
}
}
else
{
@@ -2390,7 +2460,14 @@ DSC_GeneratePPS
dscOverhead = minSliceCount * 2U;
dataRate = pWARData->dpData.linkRateHz;
if(pWARData->dpData.bIs128b132bChannelCoding)
{
dataRate = LINK_RATE_TO_DATA_RATE_128B_132B(pWARData->dpData.linkRateHz);
}
else
{
dataRate = LINK_RATE_TO_DATA_RATE_8B_10B(pWARData->dpData.linkRateHz);
}
if ((pWARData->dpData.hBlank * dataRate / pModesetInfo->pixelClockHz) <
(protocolOverhead + dscOverhead + 3U))
{
@@ -2408,6 +2485,7 @@ DSC_GeneratePPS
in->bits_per_pixel = i;
}
}
in->eDP = (pWARData->dpData.bIsEdp == NV_TRUE) ? 1 : 0;
}
//

4
src/common/modeset/timing/nvt_dsc_pps.h
View File

@@ -253,11 +253,13 @@ typedef struct
NvU32 laneCount;
DSC_DP_MODE dpMode;
NvU32 hBlank;
NvBool bIsEdp;
NvBool bIs128b132bChannelCoding;
}dpData;
} WAR_DATA;
typedef struct {
NvU8 data[496U]; // total size of DSC_IN/OUTPUT_PARAMS
NvU8 data[500U]; // total size of DSC_IN/OUTPUT_PARAMS
} DSC_GENERATE_PPS_OPAQUE_WORKAREA;
/*

11
src/common/modeset/timing/nvt_edid.c
View File

@@ -38,7 +38,7 @@ PUSH_SEGMENTS
// Macro to declare a TIMING initializer for given parameters without border
#define EST_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rr,pclk,format) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,{0,rr,set_rrx1k(pclk,ht,vt),0,1,{0},{0},{0},{0},format,"VESA Established"}}
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,((pclk<<3)+(pclk<<1)),{0,rr,set_rrx1k(pclk,ht,vt),0,1,{0},{0},{0},{0},format,"VESA Established"}}
DATA_SEGMENT(PAGE_DATA)
#if !defined(NV_WSA)
@@ -53,12 +53,12 @@ static const NVT_TIMING EDID_EST[] =
{
EST_TIMING( 720, 0, 0, 720,'-', 400, 0,0, 400,'-',70, 0,NVT_STATUS_EDID_EST), // 720x400x70Hz (IBM, VGA)
EST_TIMING( 720, 0, 0, 720,'-', 400, 0,0, 400,'-',88, 0,NVT_STATUS_EDID_EST), // 720x400x88Hz (IBM, XGA2)
{640,0,16,96,800,NVT_H_SYNC_NEGATIVE,480,0,10,2,525,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,2518,{0,60,60000,0,1,{0},{0},{0},{0},NVT_STATUS_EDID_EST,"EDID_Established"}},
{640,0,16,96,800,NVT_H_SYNC_NEGATIVE,480,0,10,2,525,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,2518,25180,{0,60,60000,0,1,{0},{0},{0},{0},NVT_STATUS_EDID_EST,"EDID_Established"}},
EST_TIMING( 640, 0, 0, 640,'-', 480, 0,0, 480,'-',67, 0,NVT_STATUS_EDID_EST), // 640x480x67Hz (Apple, Mac II)
// 640x480x72Hz (VESA) - this entry have borders
{640,8,16,40,832,NVT_H_SYNC_NEGATIVE,480,8,1,3,520,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,3150,{0,72,72000,0,1,{0},{0},{0},{0},NVT_STATUS_EDID_EST,"EDID_Established"}},
{640,8,16,40,832,NVT_H_SYNC_NEGATIVE,480,8,1,3,520,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,3150,31500,{0,72,72000,0,1,{0},{0},{0},{0},NVT_STATUS_EDID_EST,"EDID_Established"}},
EST_TIMING( 640,16, 64, 840,'-', 480, 1,3, 500,'-',75, 3150,NVT_STATUS_EDID_EST), // 640x480x75Hz (VESA)
EST_TIMING( 800,24, 72,1024,'+', 600, 1,2, 625,'+',56, 3600,NVT_STATUS_EDID_EST), // 800x600x56Hz (VESA)
EST_TIMING( 800,40,128,1056,'+', 600, 1,4, 628,'+',60, 4000,NVT_STATUS_EDID_EST), // 800x600x60Hz (VESA)
@@ -564,7 +564,8 @@ NVT_STATUS parseEdidDetailedTimingDescriptor(NvU8 *p, NVT_TIMING *pT)
pT->VSyncWidth = (NvU16)((pDTD->bDTVerticalSync & 0x0F) + ((pDTD->bDTHorizVertSyncOverFlow & 0x03) << 4));
// pixel clock
pT->pclk = (NvU32)pDTD->wDTPixelClock;
pT->pclk = (NvU32)pDTD->wDTPixelClock;
pT->pclk1khz = (NvU32)((pT->pclk << 3) + (pT->pclk << 1));
// sync polarities
if ((pDTD->bDTFlags & 0x18) == 0x18)
@@ -2964,7 +2965,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion)
CommonEDIDBuffer[0x7F] = 0;
CommonEDIDBuffer[0xFF] = 0;
// We also need to zero out any "EDID Other Monitor Descriptors" (http://en.wikipedia.org/wiki/Extended_display_identification_data)
// We also need to zero out any "EDID Other Monitor Descriptors" (https://en.wikipedia.org/wiki/Extended_display_identification_data)
for (edidBufferIndex = 54; edidBufferIndex <= 108; edidBufferIndex += 18)
{
if (CommonEDIDBuffer[edidBufferIndex] == 0 && CommonEDIDBuffer[edidBufferIndex+1] == 0)

52
src/common/modeset/timing/nvt_edidext_861.c
View File

@@ -38,15 +38,15 @@ PUSH_SEGMENTS
#define EIA_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rrx1k,ip,aspect,rep,format) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\
0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_EDID_861STn(format),"CEA-861B:#"#format""}}
0,0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_EDID_861STn(format),"CEA-861B:#"#format""}}
#define NVT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rrx1k,ip,aspect,rep,format,name) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\
0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_TYPE_NV_PREDEFINEDn(format),name}}
0,0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_TYPE_NV_PREDEFINEDn(format),name}}
#define HDMI_EXT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rrx1k,ip,aspect,rep,format,name) \
{hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\
0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_HDMI_EXTn(format),name}}
0,0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_HDMI_EXTn(format),name}}
#define RID_MODE(hv, hsp, vv, vsp, ip, aspect, rid) \
{hv, (hsp)=='-', vv, (vsp)=='-',(ip)=='i'? NVT_INTERLACED:NVT_PROGRESSIVE,((1?aspect)<<16)|(0?aspect), rid}
@@ -261,7 +261,7 @@ static const NVT_TIMING EIA861B[]=
EIA_TIMING( 7680,2352,176,10800,'+',4320,16,20,4400,'+', 50000,'p', 16:9,0x1,198),// 7680 x 4320p @50 (Format 198)
EIA_TIMING( 7680, 552,176, 9000,'+',4320,16,20,4400,'+', 59940,'p', 16:9,0x1,199),// 7680 x 4320p @59.94/60 (Format 199)
EIA_TIMING( 7680,2112,176,10560,'+',4320,16,20,4500,'+',100000,'p', 16:9,0x1,200),// 7680 x 4320p @100 (Format 200)
EIA_TIMING( 7680, 352,176, 8000,'+',4320,16,20,4500,'+',119880,'p', 16:9,0x1,201),// 7680 x 4320p @119.88/120 (Format 201)
EIA_TIMING( 7680, 352,176, 8800,'+',4320,16,20,4500,'+',119880,'p', 16:9,0x1,201),// 7680 x 4320p @119.88/120 (Format 201)
EIA_TIMING( 7680,2552,176,11000,'+',4320,16,20,4500,'+', 23976,'p', 64:27,0x1,202),// 7680 x 4320p @23.98/24 (Format 202)
EIA_TIMING( 7680,2352,176,10800,'+',4320,16,20,4400,'+', 25000,'p', 64:27,0x1,203),// 7680 x 4320p @25 (Format 203)
EIA_TIMING( 7680, 552,176, 9000,'+',4320,16,20,4400,'+', 29970,'p', 64:27,0x1,204),// 7680 x 4320p @29.97/30 (Format 204)
@@ -269,12 +269,12 @@ static const NVT_TIMING EIA861B[]=
EIA_TIMING( 7680,2352,176,10800,'+',4320,16,20,4400,'+', 50000,'p', 64:27,0x1,206),// 7680 x 4320p @50 (Format 206)
EIA_TIMING( 7680, 552,176, 9000,'+',4320,16,20,4400,'+', 59940,'p', 64:27,0x1,207),// 7680 x 4320p @59.94/60 (Format 207)
EIA_TIMING( 7680,2112,176,10560,'+',4320,16,20,4500,'+',100000,'p', 64:27,0x1,208),// 7680 x 4320p @100 (Format 208)
EIA_TIMING( 7680, 352,176, 8800,'+',4500,16,20,4950,'+',119880,'p', 64:27,0x1,209),// 7680 x 4320p @119.88/120 (Format 209)
EIA_TIMING( 7680, 352,176, 8800,'+',4320,16,20,4500,'+',119880,'p', 64:27,0x1,209),// 7680 x 4320p @119.88/120 (Format 209)
EIA_TIMING(10240,1492,176,12500,'+',4320,16,20,4950,'+', 23976,'p', 64:27,0x1,210),//10240 x 4320p @23.98/24 (Format 210)
EIA_TIMING(10240,2492,176,13500,'+',4320,16,20,4400,'+', 25000,'p', 64:27,0x1,211),//10240 x 4320p @25 (Format 211)
EIA_TIMING(10240, 288,176,11000,'+',4320,16,20,4500,'+', 29970,'p', 64:27,0x1,212),//10240 x 4320p @29.97/30 (Format 212)
EIA_TIMING(10240,1492,176,12500,'+',4320,16,20,4950,'+', 47950,'p', 64:27,0x1,213),//10240 x 4320p @47.95/48 (Format 213)
EIA_TIMING(10240,2492,176,13500,'+',4320,16,20,4400,'+', 44000,'p', 64:27,0x1,214),//10240 x 4320p @50 (Format 214)
EIA_TIMING(10240,2492,176,13500,'+',4320,16,20,4400,'+', 50000,'p', 64:27,0x1,214),//10240 x 4320p @50 (Format 214)
EIA_TIMING(10240, 288,176,11000,'+',4320,16,20,4500,'+', 59940,'p', 64:27,0x1,215),//10240 x 4320p @59.94/60 (Format 215)
EIA_TIMING(10240,2192,176,13200,'+',4320,16,20,4500,'+',100000,'p', 64:27,0x1,216),//10240 x 4320p @100 (Format 216)
EIA_TIMING(10240, 288,176,11000,'+',4320,16,20,4500,'+',119880,'p', 64:27,0x1,217),//10240 x 4320p @119.88/120 (Format 217)
@@ -649,7 +649,8 @@ void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861,
}
// calculate the pixel clock
newTiming.pclk = RRx1kToPclk(&newTiming);
newTiming.pclk = RRx1kToPclk(&newTiming);
newTiming.pclk1khz = (newTiming.pclk << 3) + (newTiming.pclk << 1); // *10
if ((vic <= 64) && (pVic[i] & NVT_CTA861_VIDEO_NATIVE_MASK))
{
@@ -790,7 +791,8 @@ void parseCta861VideoFormatDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawIn
pInfo->hdmiForumInfo.dc_48bit_420);
}
newTiming.etc.flag |= NVT_FLAG_CTA_OVT_TIMING;
newTiming.etc.aspect = RID[pVFDOneByte->rid].aspect;
newTiming.etc.flag |= NVT_FLAG_CTA_OVT_TIMING;
if (pExt861->vfdb[vfdb_idx].info.ntsc)
{
newTiming.etc.flag |= NVT_FLAG_CTA_OVT_FRR_TIMING;
@@ -924,7 +926,8 @@ void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861,
}
// calculate the pixel clock
newTiming.pclk = RRx1kToPclk(&newTiming);
newTiming.pclk = RRx1kToPclk(&newTiming);
newTiming.pclk1khz = (newTiming.pclk << 3) + (newTiming.pclk << 1); // *10
// From CTA-861-F: By default, Y420VDB SVDs, when present in the EDID, shall be less preferred than all regular Video Data Block SVDs.
// So it should use normal VIC code without native flag.
@@ -2161,7 +2164,8 @@ NVT_STATUS NvTiming_EnumCEA861bTiming(NvU32 ceaFormat, NVT_TIMING *pT)
*pT = EIA861B[ceaFormat - 1];
// calculate the pixel clock
pT->pclk = RRx1kToPclk (pT);
pT->pclk = RRx1kToPclk (pT);
pT->pclk1khz = (pT->pclk << 3) + (pT->pclk << 1); // *10
NVT_SET_CEA_FORMAT(pT->etc.status, ceaFormat);
NVT_SNPRINTF((char *)pT->etc.name, sizeof(pT->etc.name), "CTA-861G:#%3d:%dx%dx%3d.%03dHz/%s", (int)ceaFormat, (int)pT->HVisible, (int)((pT->interlaced ? 2 : 1)*pT->VVisible), (int)pT->etc.rrx1k/1000, (int)pT->etc.rrx1k%1000, (pT->interlaced ? "I":"P"));
@@ -2270,7 +2274,8 @@ NVT_STATUS NvTiming_CalcCEA861bTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32
*pT = EIA861B[i];
// calculate the pixel clock
pT->pclk = RRx1kToPclk (pT);
pT->pclk = RRx1kToPclk (pT);
pT->pclk1khz = (pT->pclk << 3) + (pT->pclk << 1); // *10
NVT_SET_CEA_FORMAT(pT->etc.status, NVT_GET_TIMING_STATUS_SEQ(pT->etc.status));
@@ -2336,8 +2341,8 @@ NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_V
ridIdx = 10 * (pTiming->etc.name[10] - '0') + (pTiming->etc.name[11] - '0');
}
if (ridIdx > NVT_CTA861_RID_1280x720p_16x9 &&
ridIdx < NVT_CTA861_RID_20480x8640p_64x27)
if (ridIdx >= NVT_CTA861_RID_1280x720p_16x9 &&
ridIdx < NVT_CTA861_RID_EXCEED_RESOLUTION)
{
pCtrl->rid = ridIdx;
}
@@ -2472,7 +2477,7 @@ NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_V
}
else
{
// default to no data, to cover other non-cea modes
// default to no data if there is no match, to cover other non-cta modes
pCtrl->pic_aspect_ratio = NVT_VIDEO_INFOFRAME_BYTE2_M1M0_NO_DATA;
}
}
@@ -2839,13 +2844,13 @@ NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, N
nvt_nvu8_set_bits(pInfoFrame->Header.version, NVT_HDMI_VS_HB1_VALUE, NVT_HDMI_VS_HB1_MASK, NVT_HDMI_VS_HB1_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Header.length, NVT_HDMI_VS_HB2_VALUE, NVT_HDMI_VS_HB2_MASK, NVT_HDMI_VS_HB2_SHIFT);
if (pCtrl->HDMIRevision == 14)
if (pCtrl->VSIFVersion == NVT_VSIF_VERSION_H14B_VSIF)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_1_4, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_1_4, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_1_4, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT);
}
else if (pCtrl->HDMIRevision >= 20)
else if (pCtrl->VSIFVersion == NVT_VSIF_VERSION_HF_VSIF)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_2_0, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_2_0, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT);
@@ -3106,7 +3111,7 @@ void NvTiming_ConstructAdaptiveSyncSDP(
NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK,
NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT);
nvt_nvu8_set_bits(pSdp->payload.db4, pCtrl->targetRefreshRate & 0x1,
nvt_nvu8_set_bits(pSdp->payload.db4, (pCtrl->targetRefreshRate & 0x300) >> 8,
NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK,
NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT);
}
@@ -3158,7 +3163,8 @@ NVT_STATUS NvTiming_EnumNvPsfTiming(NvU32 nvPsfFormat, NVT_TIMING *pT)
*pT = PSF_TIMING[nvPsfFormat - 1];
// calculate the pixel clock
pT->pclk = RRx1kToPclk (pT);
pT->pclk = RRx1kToPclk (pT);
pT->pclk1khz = (pT->pclk << 3) + (pT->pclk << 1); // *10
return NVT_STATUS_SUCCESS;
}
@@ -3267,7 +3273,9 @@ void NvTiming_GetHDMIStereoTimingFrom2DTiming(const NVT_TIMING *pTiming, NvU8 St
}
}
// calculate the pixel clock
pExtTiming->timing.pclk = RRx1kToPclk (&(pExtTiming->timing));
pExtTiming->timing.pclk = RRx1kToPclk (&(pExtTiming->timing));
pExtTiming->timing.pclk1khz = (pExtTiming->timing.pclk << 3) + (pExtTiming->timing.pclk << 1); // *10;
return;
}
@@ -3491,7 +3499,8 @@ void parseEdidHDMILLCTiming(NVT_EDID_INFO *pInfo, VSDB_DATA *pVsdb, NvU32 *pMapS
sizeof(newTiming));
// Fill in the pixel clock
newTiming.pclk = RRx1kToPclk(&newTiming);
newTiming.pclk = RRx1kToPclk(&newTiming);
newTiming.pclk1khz = (newTiming.pclk << 3) + (newTiming.pclk << 1); // *10
if (!assignNextAvailableTiming(pInfo, &newTiming))
{
@@ -3638,7 +3647,8 @@ NVT_STATUS NvTiming_EnumHdmiVsdbExtendedTiming(NvU32 hdmi_vic, NVT_TIMING *pT)
return NVT_STATUS_ERR;
}
*pT = HDMI_EXT_4Kx2K_TIMING[hdmi_vic - 1];
pT->pclk = RRx1kToPclk(pT);
pT->pclk = RRx1kToPclk(pT);
pT->pclk1khz = (pT->pclk << 3) + (pT->pclk << 1); // *10
return NVT_STATUS_SUCCESS;
}

1
src/common/modeset/timing/nvt_ovt.c
View File

@@ -264,6 +264,7 @@ NVT_STATUS NvTiming_CalcOVT(NvU32 width, NvU32 height, NvU32 refreshRate, NVT_TI
pT->VSyncWidth = (NvU16)NVT_OVT_V_SYNC_WIDTH;
pT->VFrontPorch = (NvU16)(vBlank - vSyncPosition);
pT->pclk = (NvU32)(pixelClockRate /*Hz*/ / 1000 + 5) / 10; //convert to 10Khz
pT->pclk1khz = (NvU32)(pixelClockRate /*Hz*/ / 1000); //convert to 1Khz
pT->HSyncPol = NVT_H_SYNC_POSITIVE;
pT->VSyncPol = NVT_V_SYNC_POSITIVE;
pT->HBorder = pT->VBorder = 0; // not supported

36
src/common/modeset/timing/nvt_tv.c
View File

@@ -37,24 +37,24 @@ CONS_SEGMENT(PAGE_CONS)
static const NVT_TIMING TV_TIMING[] =
{
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,240, 0,10,6,262, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1407, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_NTSC_M, "SDTV:NTSC_M"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,240, 0,10,6,262, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1407, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_NTSC_J, "SDTV:NTSC_J"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10,8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_M, "SDTV:PAL_M"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10,8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_A, "SDTV:PAL_A"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10,8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_N, "SDTV:PAL_N"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10,8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_NC, "SDTV:PAL_NC"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,240, 0,10,6,262, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1407, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_480I, "HDTV(analog):480i"}},
{720, 0,15,8, 858, NVT_H_SYNC_NEGATIVE,480, 0,10,4,525, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,2700, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_480P, "HDTV(analog):480p"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10,8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_576I, "HDTV(analog):576i"}},
{720, 0,10,8, 864, NVT_H_SYNC_NEGATIVE,576, 0,5, 4,625, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,2700, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_576P, "HDTV(analog):576p"}},
{1280,0,70,80, 1650,NVT_H_SYNC_NEGATIVE,720,0,5, 5,750, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,7418, {0,60,59940,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_720P, "HDTV(analog):720p"}},
{1920,0,44,88,2200,NVT_H_SYNC_NEGATIVE,540, 0,2, 5,562, NVT_V_SYNC_NEGATIVE,NVT_INTERLACED, 7418, {0,60,59940,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080I, "HDTV(analog):1080i"}},
{1920,0,44,88,2200,NVT_H_SYNC_NEGATIVE,1080,0,4, 5,1125,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,14835,{0,60,59940,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080P, "HDTV(analog):1080p"}},
{1280,0,400,80,1980,NVT_H_SYNC_NEGATIVE,720,0,5, 5,750, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,7425, {0,50,50000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_720P50, "HDTV(analog):720p50"}},
{1920,0,594,88,2750,NVT_H_SYNC_NEGATIVE,1080,0,4, 5,1125,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,7425,{0,24,24000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080P24,"HDTV(analog):1080p24"}},
{1920,0,484,88,2640,NVT_H_SYNC_NEGATIVE,540, 0,4, 5,562, NVT_V_SYNC_NEGATIVE,NVT_INTERLACED, 7425,{0,50,50000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080I50,"HDTV(analog):1080i50"}},
{1920,0,484,88,2640,NVT_H_SYNC_NEGATIVE,1080,0,4, 5,1125,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,14850,{0,50,50000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080P50,"HDTV(analog):1080p50"}},
{0,0,0,0,0,NVT_H_SYNC_NEGATIVE,0,0,0,0,0,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,0,{0,0,0,0,0,{0},{0},{0},{0},0,""}}
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,240, 0,10, 6,262, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1407 , 14070, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_NTSC_M, "SDTV:NTSC_M"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,240, 0,10, 6,262, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1407 , 14070, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_NTSC_J, "SDTV:NTSC_J"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10, 8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397 , 13970, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_M, "SDTV:PAL_M"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10, 8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397 , 13970, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_A, "SDTV:PAL_A"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10, 8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397 , 13970, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_N, "SDTV:PAL_N"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10, 8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397 , 13970, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_SDTV_PAL_NC, "SDTV:PAL_NC"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,240, 0,10, 6,262, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1407 , 14070, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_480I, "HDTV(analog):480i"}},
{720, 0,15,8, 858, NVT_H_SYNC_NEGATIVE,480, 0,10, 4,525, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE, 2700 , 27000, {0,60,59940,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_480P, "HDTV(analog):480p"}},
{720, 0,21,66,894, NVT_H_SYNC_POSITIVE,288, 0,10, 8,312, NVT_V_SYNC_POSITIVE,NVT_INTERLACED, 1397 , 13970, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_576I, "HDTV(analog):576i"}},
{720, 0,10,8, 864, NVT_H_SYNC_NEGATIVE,576, 0, 5, 4,625, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE, 2700 , 27000, {0,50,50000,0x0403,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_576P, "HDTV(analog):576p"}},
{1280,0,70,80, 1650,NVT_H_SYNC_NEGATIVE,720, 0, 5, 5,750, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE, 7418 , 74180, {0,60,59940,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_720P, "HDTV(analog):720p"}},
{1920,0,44,88,2200, NVT_H_SYNC_NEGATIVE,540, 0, 2, 5,562, NVT_V_SYNC_NEGATIVE,NVT_INTERLACED, 7418 , 74180, {0,60,59940,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080I, "HDTV(analog):1080i"}},
{1920,0,44,88,2200, NVT_H_SYNC_NEGATIVE,1080,0, 4, 5,1125,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE, 14835,148350, {0,60,59940,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080P, "HDTV(analog):1080p"}},
{1280,0,400,80,1980,NVT_H_SYNC_NEGATIVE,720, 0, 5, 5,750, NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE, 7425 , 74250, {0,50,50000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_720P50, "HDTV(analog):720p50"}},
{1920,0,594,88,2750,NVT_H_SYNC_NEGATIVE,1080,0, 4, 5,1125,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE, 7425 , 74250, {0,24,24000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080P24,"HDTV(analog):1080p24"}},
{1920,0,484,88,2640,NVT_H_SYNC_NEGATIVE,540, 0, 4, 5,562, NVT_V_SYNC_NEGATIVE,NVT_INTERLACED, 7425 , 74250, {0,50,50000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080I50,"HDTV(analog):1080i50"}},
{1920,0,484,88,2640,NVT_H_SYNC_NEGATIVE,1080,0, 4, 5,1125,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,14850 ,148500, {0,50,50000,0x1009,0x1,{0},{0},{0},{0},NVT_STATUS_HDTV_1080P50,"HDTV(analog):1080p50"}},
{0,0,0,0,0,NVT_H_SYNC_NEGATIVE,0,0,0,0,0,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,0,0,{0,0,0,0,0,{0},{0},{0},{0},0,""}}
};
//***********************************************

6
src/common/modeset/timing/nvt_util.c
View File

@@ -343,9 +343,9 @@ NvU32 NvTiming_IsTimingRelaxedEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2
CODE_SEGMENT(NONPAGE_DD_CODE)
NvU32 RRx1kToPclk (NVT_TIMING *pT)
{
return axb_div_c(pT->HTotal * (pT->VTotal + ((pT->interlaced != 0) ? (pT->VTotal + 1) : 0)),
pT->etc.rrx1k,
1000 * ((pT->interlaced != 0) ? 20000 : 10000));
return (NvU32)axb_div_c_64(pT->HTotal * (pT->VTotal + ((pT->interlaced != 0) ? (pT->VTotal + 1) : 0)),
pT->etc.rrx1k,
1000 * ((pT->interlaced != 0) ? 20000 : 10000));
}
CODE_SEGMENT(PAGE_DD_CODE)

11
src/common/modeset/timing/nvtiming.h
View File

@@ -189,6 +189,7 @@ typedef struct tagNVT_TIMING
NvU16 interlaced; //1-interlaced, 0-progressive
NvU32 pclk; //pixel clock in 10KHz
NvU32 pclk1khz; //pixel clock in 1kHz for Type7, CVT RB2, CVT RB3
//other timing related extras
NVT_TIMINGEXT etc;
@@ -774,6 +775,7 @@ typedef enum NVT_TV_FORMAT
#define NVT_CTA861_RID_15360x8640p_16x9 26
#define NVT_CTA861_RID_15360x8640p_64x27 27
#define NVT_CTA861_RID_20480x8640p_64x27 28
#define NVT_CTA861_RID_EXCEED_RESOLUTION NVT_CTA861_RID_NONE
// Table 12 - AVI InfoFrame Video Format Frame Rate
#define NVT_CTA861_FR_NO_DATA NVT_INFOFRAME_CTRL_DONTCARE
@@ -3060,7 +3062,7 @@ typedef struct tagNVT_AUDIO_INFOFRAME_CTRL
typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL
{
NvU8 Enable;
NvU8 HDMIRevision;
NvU8 VSIFVersion;
NvU8 HDMIFormat;
NvU8 HDMI_VIC;
NvBool ALLMEnable;
@@ -3073,6 +3075,10 @@ typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL
} NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL;
#define NVT_3D_METADTATA_TYPE_PARALAX 0x00
#define NVT_3D_METADTATA_PARALAX_LEN 0x08
#define NVT_VSIF_VERSION_NONE 0
#define NVT_VSIF_VERSION_H14B_VSIF 14
#define NVT_VSIF_VERSION_HF_VSIF 20
#define NVT_EXTENDED_METADATA_PACKET_INFOFRAME_VER_HDMI21 0x0
#define NVT_EXTENDED_METADATA_PACKET_INFOFRAME_VER_HDMI21A 0x1
@@ -3210,6 +3216,7 @@ typedef struct tagNVT_VIDEO_INFOFRAME
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr444 2
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this line 4266
// CTA-861I new requirement
#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED 7
// CEA-861-F - Unix still used this one
#define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_MASK 0x60
@@ -4005,7 +4012,7 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK 0xff
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK 0x01
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK 0x03
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT 0
#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_MASK 0x1c

2
src/common/modeset/timing/nvtiming_pvt.h
View File

@@ -164,7 +164,7 @@ NvU32 axb_div_c_old(NvU32 a, NvU32 b, NvU32 c);
// Sentinel values for NVT_TIMING
#define NVT_TIMINGEXT_SENTINEL {0,0,0,0,0,{0},{0},{0},{0},0,""}
#define NVT_TIMING_SENTINEL {0,0,0,0,0,0,0,0,0,0,0,0,0,0,NVT_TIMINGEXT_SENTINEL}
#define NVT_TIMING_SENTINEL {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,NVT_TIMINGEXT_SENTINEL}
#endif //__NVTIMING_PVT_H_

26
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -121,10 +121,25 @@ typedef struct
#define NVLINK_INBAND_FM_CAPS_EGM_ENABLED NVBIT64(6)
#define NVLINK_INBAND_FM_CAPS_ATS_ENABLED NVBIT64(7)
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ROUTE_UPDATE 3:2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY 5:4
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_LINK_MASK_CHANGED 7:6
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_LINK_MASK_CHANGED_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_LINK_MASK_CHANGED_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_LINK_MASK_CHANGED_FALSE 2
typedef struct
{
@@ -156,7 +171,8 @@ typedef struct
NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */
NvU32 cliqueId; /* Fabric Clique Id*/
NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */
NvU8 reserved[32]; /* For future use. Must be initialized to zero */
NvU32 epoch; /* Epoch to be matched by RM when allowing P2P between GPUs */
NvU8 reserved[28]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_update_req_t;
typedef struct

7
src/common/nvswitch/common/inc/soe/soeifcmn.h
View File

@@ -175,11 +175,4 @@ enum
RM_SOE_DMAIDX_GUEST_PHYS_SYS_NCOH_BOUND = 7
};
/*!
* SOE Debug buffer size
* Creating a copy of SOE_DMESG_BUFFER_SIZE in memmap.h
* soe/memmap.h is conflicting with sec2/memmap.h and cannot be used in the driver
*/
#define SOE_DEBUG_BUFFER_SIZE 0x1000
#endif // _GSOEIFCMN_H_

44
src/common/nvswitch/common/inc/soe/soeifcore.h
View File

@@ -125,6 +125,11 @@ enum
* Issue Ingress stop
*/
RM_SOE_CORE_CMD_ISSUE_INGRESS_STOP = 0x10,
/*
* Enable ERROR reporting
*/
RM_SOE_CORE_CMD_UPDATE_INTR_REPORT_EN = 0x12,
};
// Timeout for SOE reset callback function
@@ -273,6 +278,44 @@ enum
RM_SOE_CORE_NPORT_REDUCTION_INTERRUPT
};
typedef enum
{
RM_SOE_CORE_ENGINE_ID_NPORT,
RM_SOE_CORE_ENGINE_ID_NVLIPT,
RM_SOE_CORE_ENGINE_ID_NVLIPT_LNK,
RM_SOE_CORE_ENGINE_ID_NVLTLC
}RM_SOE_CORE_ENGINE_ID;
typedef enum
{
RM_SOE_CORE_NPORT_ROUTE_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_ROUTE_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_INGRESS_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_INGRESS_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_INGRESS_ERR_NON_FATAL_REPORT_EN_1,
RM_SOE_CORE_NPORT_TSTATE_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_TSTATE_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_EGRESS_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_EGRESS_ERR_NON_FATAL_REPORT_EN_1,
RM_SOE_CORE_NPORT_EGRESS_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_EGRESS_ERR_FATAL_REPORT_EN_1,
RM_SOE_CORE_NPORT_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_SOURCETRACK_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0
}RM_SOE_CORE_NPORT_REPORT_EN_REGISTER;
typedef struct
{
NvU8 cmdType;
RM_SOE_CORE_ENGINE_ID engId;
NvU32 engInstance;
RM_SOE_CORE_NPORT_REPORT_EN_REGISTER reg;
NvU32 data;
} RM_SOE_CORE_CMD_ERROR_REPORT_EN;
typedef union
{
NvU8 cmdType;
@@ -292,6 +335,7 @@ typedef union
RM_SOE_CORE_CMD_PERFORM_ONBOARD_PHASE performOnboardPhase;
RM_SOE_CORE_CMD_NPORT_FATAL_INTR nportDisableIntr;
RM_SOE_CORE_CMD_INGRESS_STOP ingressStop;
RM_SOE_CORE_CMD_ERROR_REPORT_EN enableErrorReport;
} RM_SOE_CORE_CMD;
typedef struct

90
src/common/nvswitch/common/inc/soe/soeiftnvl.h
View File

@@ -34,6 +34,78 @@
* Command Messages between driver and TNVL unit of SOE
*/
#define RM_SOE_LIST_LS10_ONLY_ENGINES(_op) \
_op(GIN) \
_op(XAL) \
_op(XAL_FUNC) \
_op(XPL) \
_op(XTL) \
_op(XTL_CONFIG) \
_op(UXL) \
_op(GPU_PTOP) \
_op(PMC) \
_op(PBUS) \
_op(ROM2) \
_op(GPIO) \
_op(FSP) \
_op(SYSCTRL) \
_op(CLKS_SYS) \
_op(CLKS_SYSB) \
_op(CLKS_P0) \
_op(SAW_PM) \
_op(PCIE_PM) \
_op(PRT_PRI_HUB) \
_op(PRT_PRI_RS_CTRL) \
_op(SYS_PRI_HUB) \
_op(SYS_PRI_RS_CTRL) \
_op(SYSB_PRI_HUB) \
_op(SYSB_PRI_RS_CTRL) \
_op(PRI_MASTER_RS) \
_op(PTIMER) \
_op(CPR) \
_op(TILEOUT) \
#define RM_SOE_LIST_ALL_ENGINES(_op) \
_op(XVE) \
_op(SAW) \
_op(SOE) \
_op(SMR) \
\
_op(NPG) \
_op(NPORT) \
\
_op(NVLW) \
_op(MINION) \
_op(NVLIPT) \
_op(NVLIPT_LNK) \
_op(NVLTLC) \
_op(NVLDL) \
\
_op(NXBAR) \
_op(TILE) \
\
_op(NPG_PERFMON) \
_op(NPORT_PERFMON) \
\
_op(NVLW_PERFMON) \
#define RM_SOE_ENGINE_ID_LIST(_eng) \
RM_SOE_ENGINE_ID_##_eng,
//
// ENGINE_IDs are the complete list of all engines that are supported on
// LS10 architecture(s) that may support them. Any one architecture may or
// may not understand how to operate on any one specific engine.
// Architectures that share a common ENGINE_ID are not guaranteed to have
// compatible manuals.
//
typedef enum rm_soe_engine_id
{
RM_SOE_LIST_ALL_ENGINES(RM_SOE_ENGINE_ID_LIST)
RM_SOE_LIST_LS10_ONLY_ENGINES(RM_SOE_ENGINE_ID_LIST)
RM_SOE_ENGINE_ID_SIZE,
} RM_SOE_ENGINE_ID;
/*!
* Commands offered by the SOE Tnvl Interface.
*/
@@ -47,6 +119,10 @@ enum
* Issue pre-lock sequence
*/
RM_SOE_TNVL_CMD_ISSUE_PRE_LOCK_SEQUENCE = 0x1,
/*
* Issue engine write command
*/
RM_SOE_TNVL_CMD_ISSUE_ENGINE_WRITE = 0x2,
};
/*!
@@ -60,6 +136,17 @@ typedef struct
NvU32 data;
} RM_SOE_TNVL_CMD_REGISTER_WRITE;
typedef struct
{
NvU8 cmdType;
RM_SOE_ENGINE_ID eng_id;
NvU32 eng_bcast;
NvU32 eng_instance;
NvU32 base;
NvU32 offset;
NvU32 data;
} RM_SOE_TNVL_CMD_ENGINE_WRITE;
typedef struct
{
NvU8 cmdType;
@@ -69,8 +156,9 @@ typedef union
{
NvU8 cmdType;
RM_SOE_TNVL_CMD_REGISTER_WRITE registerWrite;
RM_SOE_TNVL_CMD_ENGINE_WRITE engineWrite;
RM_SOE_TNVL_CMD_PRE_LOCK_SEQUENCE preLockSequence;
} RM_SOE_TNVL_CMD;
#endif // _SOEIFTNVL_H_
#endif // _SOETNVL_H_

3
src/common/nvswitch/interface/ctrl_dev_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -831,6 +831,7 @@ typedef enum nvswitch_err_type
NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007,
NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008,
NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE = 10009,
NVSWITCH_ERR_HW_HOST_TNVL_ERROR = 10010,
NVSWITCH_ERR_HW_HOST_LAST,

1
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -213,6 +213,7 @@
_op(NvU32, nvswitch_get_eng_count, (nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast), _arch) \
_op(NvU32, nvswitch_eng_rd, (nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 offset), _arch) \
_op(void, nvswitch_eng_wr, (nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 offset, NvU32 data), _arch) \
_op(void, nvswitch_reg_write_32, (nvswitch_device *device, NvU32 offset, NvU32 data), _arch) \
_op(NvU32, nvswitch_get_link_eng_inst, (nvswitch_device *device, NvU32 link_id, NVSWITCH_ENGINE_ID eng_id), _arch) \
_op(void *, nvswitch_alloc_chipdevice, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_init_thermal, (nvswitch_device *device), _arch) \

9
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -189,8 +189,9 @@
#define SOE_VBIOS_VERSION_MASK 0xFF0000
#define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000
#define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x4C0000
#define SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE 0x580000
#define SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND 0x600000
#define SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND 0x590000
#define SOE_VBIOS_REVLOCK_SOE_PRI_CHECKS 0x610000
#define SOE_VBIOS_REVLOCK_REPORT_EN 0x700000
// LS10 Saved LED state
#define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED
@@ -1055,10 +1056,10 @@ NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_ls10(nvswitch_device *
NvlStatus nvswitch_tnvl_get_attestation_report_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_send_fsp_lock_config_ls10(nvswitch_device *device);
NvlStatus nvswitch_tnvl_get_status_ls10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
void nvswitch_tnvl_reg_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
void nvswitch_tnvl_eng_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
NvlStatus nvswitch_send_tnvl_prelock_cmd_ls10(nvswitch_device *device);
void nvswitch_tnvl_disable_interrupts_ls10(nvswitch_device *device);
void nvswitch_tnvl_reg_wr_32_ls10(nvswitch_device *device, NvU32 offset, NvU32 data);
NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p);
NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable);
NvlStatus nvswitch_cci_initialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber);

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