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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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51
src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h Normal file
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@@ -0,0 +1,51 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: alloc/alloc_access_counter_buffer.finn
//
#include "class/clc365.h"
/*
* NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS
*
* Allocation params for ACCESS_COUNTER_NOTIFY_BUFFER.
* This class provides an interface to access counter buffers.
* accessCounterIndex [IN]
* This parameter specifies index of access counter to which the object should be assigned
*
*/
#define NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS_MESSAGE_ID (0xC365U)
typedef struct NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS {
NvU32 accessCounterIndex;
} NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS;

23
src/common/sdk/nvidia/inc/alloc/alloc_channel.h
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@@ -28,7 +28,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: alloc/alloc_channel.finn
// Source file: alloc/alloc_channel.finn
//
#include "nvlimits.h"
@@ -83,6 +83,25 @@ typedef struct NV_MEMORY_DESC_PARAMS {
#define NVOS04_FLAGS_VPR_FALSE 0x00000000
#define NVOS04_FLAGS_VPR_TRUE 0x00000001
/*
* NVOS04_FLAGS_CC_SECURE:
* This flag specifies if channel is intended to be used for
* encryption/decryption of data between SYSMEM <-> VIDMEM. Only CE
* & SEC2 Channels are capable of handling encrypted content and this
* flag will be ignored when CC is disabled or for chips that are not CC
* Capable.
* Reusing VPR index since VPR & CC are mutually exclusive.
*
* NVOS04_FLAGS_CC_SECURE_TRUE:
* The channel will support CC Encryption/Decryption
*
* NVOS04_FLAGS_CC_SECURE_FALSE:
* The channel will not support CC Encryption/Decryption
*/
#define NVOS04_FLAGS_CC_SECURE 2:2
#define NVOS04_FLAGS_CC_SECURE_FALSE 0x00000000
#define NVOS04_FLAGS_CC_SECURE_TRUE 0x00000001
/*
@@ -300,8 +319,6 @@ typedef struct NV_CHANNEL_ALLOC_PARAMS {
NvU32 subDeviceId;
NvHandle hObjectEccError; // ECC error context DMA
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8);
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8);
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8);

85
src/common/sdk/nvidia/inc/cc_drv.h Normal file
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@@ -0,0 +1,85 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: cc_drv.finn
//
#include "nvtypes.h"
#include "nvcfg_sdk.h"
// CLASS NV_CONF_COMPUTE
#define CC_AES_256_GCM_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */
#define CC_AES_256_GCM_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(CC_AES_256_GCM_IV_SIZE_BYTES / 4)" */
#define CC_AES_256_GCM_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_AES_256_GCM_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_AES_256_GCM_KEY_SIZE_BYTES / 4)" */
#define CC_HMAC_NONCE_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_HMAC_NONCE_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_NONCE_SIZE_BYTES / 4)" */
#define CC_HMAC_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_HMAC_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_KEY_SIZE_BYTES / 4)" */
#define APM_AES_128_CTR_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */
#define APM_AES_128_CTR_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(APM_AES_128_CTR_IV_SIZE_BYTES / 4)" */
#define APM_AES_128_CTR_KEY_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */
#define APM_AES_128_CTR_KEY_SIZE_DWORD (0x4U) /* finn: Evaluated from "(APM_AES_128_CTR_KEY_SIZE_BYTES / 4)" */
// Type is shared between CC control calls and RMKeyStore
typedef enum ROTATE_IV_TYPE {
ROTATE_IV_ENCRYPT = 0, // Rotate the IV for encryptBundle
ROTATE_IV_DECRYPT = 1, // Rotate the IV for decryptBundle
ROTATE_IV_HMAC = 2, // Rotate the IV for hmacBundle
ROTATE_IV_ALL_VALID = 3, // Rotate the IV for all valid bundles in the KMB
} ROTATE_IV_TYPE;
typedef struct CC_AES_CRYPTOBUNDLE {
NvU32 iv[CC_AES_256_GCM_IV_SIZE_DWORD];
NvU32 key[CC_AES_256_GCM_KEY_SIZE_DWORD];
NvU32 ivMask[CC_AES_256_GCM_IV_SIZE_DWORD];
} CC_AES_CRYPTOBUNDLE;
typedef struct CC_AES_CRYPTOBUNDLE *PCC_AES_CRYPTOBUNDLE;
typedef struct CC_HMAC_CRYPTOBUNDLE {
NvU32 nonce[CC_HMAC_NONCE_SIZE_DWORD];
NvU32 key[CC_HMAC_KEY_SIZE_DWORD];
} CC_HMAC_CRYPTOBUNDLE;
typedef struct CC_HMAC_CRYPTOBUNDLE *PCC_HMAC_CRYPTOBUNDLE;
typedef struct CC_KMB {
CC_AES_CRYPTOBUNDLE encryptBundle; // Bundle of encyption material
union {
CC_HMAC_CRYPTOBUNDLE hmacBundle; // HMAC bundle used for method stream authenticity
CC_AES_CRYPTOBUNDLE decryptBundle; // Bundle of decryption material
};
NvBool bIsWorkLaunch; // False if decryption parameters are valid
} CC_KMB;
typedef struct CC_KMB *PCC_KMB;

2
src/common/sdk/nvidia/inc/class/cl0000.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0000.finn
// Source file: class/cl0000.finn
//
#include "nvlimits.h"

2
src/common/sdk/nvidia/inc/class/cl0005.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0005.finn
// Source file: class/cl0005.finn
//
#include "cl0005_notification.h"

2
src/common/sdk/nvidia/inc/class/cl000f.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl000f.finn
// Source file: class/cl000f.finn
//
#define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */

39
src/common/sdk/nvidia/inc/class/cl0042.h Normal file
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@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0042_h_
#define _cl0042_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV_MEMORY_EXTENDED_USER (0x00000042)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0042_h_ */

56
src/common/sdk/nvidia/inc/class/cl0050.h Normal file
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@@ -0,0 +1,56 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0050.finn
//
#define NV_CE_UTILS (0x50U) /* finn: Evaluated from "NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0050U)
typedef struct NV0050_ALLOCATION_PARAMETERS {
NvHandle hVaspace;
NV_DECLARE_ALIGNED(NvU64 flags, 8);
} NV0050_ALLOCATION_PARAMETERS;
// Whether the CeUtils will allocate everything with RM client or external client
#define NV0050_CEUTILS_FLAGS_EXTERNAL 0:0
#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001)
// Whether CeUtils will use virtual copy
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE 1:1
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001)
// Whether the CeUtils is using fifo lite mode. Has to be internal
#define NV0050_CEUTILS_FLAGS_FIFO_LITE 2:2
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)

2
src/common/sdk/nvidia/inc/class/cl0060.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0060.finn
// Source file: class/cl0060.finn
//
#define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl0070.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0070.finn
// Source file: class/cl0070.finn
//
#define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl0080.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0080.finn
// Source file: class/cl0080.finn
//
#include "nvlimits.h"

2
src/common/sdk/nvidia/inc/class/cl0092.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0092.finn
// Source file: class/cl0092.finn
//
#include "class/cl0092_callback.h"

2
src/common/sdk/nvidia/inc/class/cl00c1.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00c1.finn
// Source file: class/cl00c1.finn
//
#include "nvlimits.h"

2
src/common/sdk/nvidia/inc/class/cl00c2.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00c2.finn
// Source file: class/cl00c2.finn
//
#define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl00c3.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00c3.finn
// Source file: class/cl00c3.finn
//
#define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */

85
src/common/sdk/nvidia/inc/class/cl00da.h Normal file
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@@ -0,0 +1,85 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00da.finn
//
/*
* NV_SEMAPHORE_SURFACE
* A semaphore surface object contains a GPU-and-CPU-accessible memory region
* containing semaphores, associated monitored fence values, and any other
* related data necessary to implement a circular 32-bit or monotonic 64-bit
* incrementing semaphore primitive and associated event delivery.
*/
#define NV_SEMAPHORE_SURFACE (0xdaU) /* finn: Evaluated from "NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID" */
/*
* NV_SEMAPHORE_SURFACE_WAIT_VALUE
* The notification index used when registering events with the RM event
* subsystem. RM clients should not need to use this value, as they don't
* allocate events against this class themselves. Rather, they specify an
* OS event when registering a CPU waiter, and semaphore surface takes care
* of creating event objects internally as necessary, similar to the event
* buffer record notification OS event mechanism.
*/
#define NV_SEMAPHORE_SURFACE_WAIT_VALUE (0x00000000)
/*
* NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS
*
* hSemaphoreMem [IN]
* The handle to the memory used for the semaphore value and, when
* supported, the monitored fence/conditional interrupt value. Must be
* accessible by the GPU corresponding to the parent of the semaphore
* surface, as well as the CPU.
*
* hMaxSubmittedMem [IN]
* The handle to the memory used to track the maximum signal value
* submitted to the GPU for processing for a given semaphore slot in
* hSemaphoreMem. This memory is only accessed by the CPU, but must
* support a CPU mapping that allows the use of 64-bit atomic exchange
* operations. This may be the same memory object as hSemaphoreMem if it is
* possible to create one memory object that supports all the requirements
* for a given GPU and CPU. This handle may be omitted/set to zero on GPUs
* that do not require maximum submitted value tracking.
*
* flags [IN]
* Flags affecting the semaphore surface allocation. Currently, there are
* not valid flags, so this value must be set to zero.
*/
#define NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID (0x00DAU)
typedef struct NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS {
NvHandle hSemaphoreMem;
NvHandle hMaxSubmittedMem;
NV_DECLARE_ALIGNED(NvU64 flags, 8);
} NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS;

2
src/common/sdk/nvidia/inc/class/cl00db.h
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@@ -28,7 +28,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00db.finn
// Source file: class/cl00db.finn
//
#define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl00f3.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00f3.finn
// Source file: class/cl00f3.finn
//

9
src/common/sdk/nvidia/inc/class/cl00f8.h
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@@ -27,11 +27,14 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00f8.finn
// Source file: class/cl00f8.finn
//
#include "nvcfg_sdk.h"
/*
* Class definition for allocating a contiguous or discontiguous FLA.
*/
@@ -93,6 +96,8 @@
#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000
#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV00F8_ALLOC_FLAGS_DEFAULT 0
#define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0)
#define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1)
@@ -106,7 +111,7 @@ typedef struct NV00F8_ALLOCATION_PARAMETERS {
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
NvU32 pageSize;
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
NvU32 allocFlags;
struct {

2
src/common/sdk/nvidia/inc/class/cl00fd.h
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@@ -31,7 +31,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00fd.finn
// Source file: class/cl00fd.finn
//
#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl00fe.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00fe.finn
// Source file: class/cl00fe.finn
//
#define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl2080.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl2080.finn
// Source file: class/cl2080.finn
//
#include "nvlimits.h"

7
src/common/sdk/nvidia/inc/class/cl2080_notification.h
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@@ -202,7 +202,8 @@ extern "C" {
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176)
#define NV2080_NOTIFIERS_NVPCF_EVENTS (177)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178)
#define NV2080_NOTIFIERS_MAXCOUNT (179)
#define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179)
#define NV2080_NOTIFIERS_MAXCOUNT (180)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
@@ -497,6 +498,10 @@ typedef struct {
NvU32 linkId;
} Nv2080NvlinkLnkChangeNotification;
typedef struct {
NvU32 head;
} Nv2080VrrSetTimeoutNotification;
#ifdef __cplusplus
}; /* extern "C" */
#endif

2
src/common/sdk/nvidia/inc/class/cl2081.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl2081.finn
// Source file: class/cl2081.finn
//
#define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl2082.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl2082.finn
// Source file: class/cl2082.finn
//
#define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl30f1.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl30f1.finn
// Source file: class/cl30f1.finn
//
#include "cl30f1_notification.h"

21
src/common/sdk/nvidia/inc/class/cl503b.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,7 +28,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl503b.finn
// Source file: class/cl503b.finn
//
#define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */
@@ -37,6 +37,19 @@
#define NV503B_FLAGS_P2P_TYPE_GPA 0
#define NV503B_FLAGS_P2P_TYPE_SPA 1
/*
* NV503B_BAR1_P2P_DMA_INFO
*
* The DMA information for BAR1 P2P, it is only valid for BAR1 P2P.
* dma_address will be set to NV_U64_MAX and dma_size will be set to 0
* when the DMA info is not available.
*
*/
typedef struct NV503B_BAR1_P2P_DMA_INFO {
NV_DECLARE_ALIGNED(NvU64 dma_address, 8);
NV_DECLARE_ALIGNED(NvU64 dma_size, 8);
} NV503B_BAR1_P2P_DMA_INFO;
/* NvRmAlloc parameters */
#define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU)
@@ -54,4 +67,8 @@ typedef struct NV503B_ALLOC_PARAMETERS {
NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area
* Must have the same value across the GPUs */
NvU32 flags; /* Flag to indicate types/attib of p2p */
NvU32 subDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID of SubDevice */
NvU32 peerSubDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID for PeerSubDevice */
NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO l2pBar1P2PDmaInfo, 8); /* Bar1 DMA info from local GPU to peer GPU */
NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO p2lBar1P2PDmaInfo, 8); /* Bar1 DMA info from peer GPU to local GPU */
} NV503B_ALLOC_PARAMETERS;

2
src/common/sdk/nvidia/inc/class/cl503c.h
View File

@@ -28,7 +28,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl503c.finn
// Source file: class/cl503c.finn
//
#define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl5070.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl5070.finn
// Source file: class/cl5070.finn
//
#include "cl5070_notification.h"

2
src/common/sdk/nvidia/inc/class/cl5080.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl5080.finn
// Source file: class/cl5080.finn
//
#include "cl5080_notification.h"

2
src/common/sdk/nvidia/inc/class/cl83de.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl83de.finn
// Source file: class/cl83de.finn
//
#define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl84a0.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl84a0.finn
// Source file: class/cl84a0.finn
//
#include "cl84a0_deprecated.h"

2
src/common/sdk/nvidia/inc/class/cl85b5sw.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl85b5sw.finn
// Source file: class/cl85b5sw.finn
//
#define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U)

2
src/common/sdk/nvidia/inc/class/cl9010.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9010.finn
// Source file: class/cl9010.finn
//
#include "class/cl9010_callback.h"

2
src/common/sdk/nvidia/inc/class/cl9072.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9072.finn
// Source file: class/cl9072.finn
//
#include "cl9072_notification.h"

2
src/common/sdk/nvidia/inc/class/cl90cd.h
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@@ -33,7 +33,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl90cd.finn
// Source file: class/cl90cd.finn
//
#define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl9170.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9170.finn
// Source file: class/cl9170.finn
//
#define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl9270.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9270.finn
// Source file: class/cl9270.finn
//
#define NV9270_DISPLAY (0x9270U) /* finn: Evaluated from "NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl9470.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9470.finn
// Source file: class/cl9470.finn
//
#define NV9470_DISPLAY (0x9470U) /* finn: Evaluated from "NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl9570.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9570.finn
// Source file: class/cl9570.finn
//
#define NV9570_DISPLAY (0x9570U) /* finn: Evaluated from "NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl9770.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9770.finn
// Source file: class/cl9770.finn
//
#define NV9770_DISPLAY (0x9770U) /* finn: Evaluated from "NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/cl9870.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9870.finn
// Source file: class/cl9870.finn
//
#define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */

8
src/common/sdk/nvidia/inc/class/cla084.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cla084.finn
// Source file: class/cla084.finn
//
#include "nv_vgpu_types.h"
@@ -50,9 +50,10 @@
* save/restore will not be done in host-RM
* vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used
* for supporting multiple vGPUs per VM.
* numGuestFbHandles -> number of guest memory handles
* hPluginClient -> handle to the plugin client
* numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient
* guestFbHandleList -> handle list to guest memory
* hPluginHeapMemory -> plugin heap memory handle
* hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient
* bDeviceProfilingEnabled -> If set to true, profiling is allowed
*/
#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U)
@@ -69,6 +70,7 @@ typedef struct NVA084_ALLOC_PARAMETERS {
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
NvBool bDisableDefaultSmcExecPartRestore;
NvU32 vgpuDeviceInstanceId;
NvHandle hPluginClient;
NvU32 numGuestFbHandles;
NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS];
NvHandle hPluginHeapMemory;

2
src/common/sdk/nvidia/inc/class/clb069sw.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clb069sw.finn
// Source file: class/clb069sw.finn
//
#define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U)

2
src/common/sdk/nvidia/inc/class/clb0b5sw.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clb0b5sw.finn
// Source file: class/clb0b5sw.finn
//

2
src/common/sdk/nvidia/inc/class/clb2cc.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clb2cc.finn
// Source file: class/clb2cc.finn
//
#include "clb0cc.h"

2
src/common/sdk/nvidia/inc/class/clc0b5sw.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc0b5sw.finn
// Source file: class/clc0b5sw.finn
//

2
src/common/sdk/nvidia/inc/class/clc1b5sw.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc1b5sw.finn
// Source file: class/clc1b5sw.finn
//

2
src/common/sdk/nvidia/inc/class/clc370.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc370.finn
// Source file: class/clc370.finn
//
#include "clc370_notification.h"

3
src/common/sdk/nvidia/inc/class/clc370_notification.h
View File

@@ -32,8 +32,7 @@ extern "C" {
/* event values */
#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW
#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT
#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0)
#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1)
#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_BEGIN + (0)
#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)

2
src/common/sdk/nvidia/inc/class/clc3b5sw.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc3b5sw.finn
// Source file: class/clc3b5sw.finn
//

2
src/common/sdk/nvidia/inc/class/clc570.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc570.finn
// Source file: class/clc570.finn
//
#define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc574.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc574.finn
// Source file: class/clc574.finn
//
#define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc58b.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc58b.finn
// Source file: class/clc58b.finn
//
#define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc5b5sw.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc5b5sw.finn
// Source file: class/clc5b5sw.finn
//

2
src/common/sdk/nvidia/inc/class/clc637.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc637.finn
// Source file: class/clc637.finn
//
#define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc638.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc638.finn
// Source file: class/clc638.finn
//
#define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc639.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc639.finn
// Source file: class/clc639.finn
//
#define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc640.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc640.finn
// Source file: class/clc640.finn
//
#define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc670.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc670.finn
// Source file: class/clc670.finn
//
#define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/class/clc6b5sw.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc6b5sw.finn
// Source file: class/clc6b5sw.finn
//

2
src/common/sdk/nvidia/inc/class/clc770.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc770.finn
// Source file: class/clc770.finn
//
#define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */

35
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h → src/common/sdk/nvidia/inc/class/clcb33.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,35 +23,18 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080rc.finn
// Source file: class/clcb33.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
#define NV_CONFIDENTIAL_COMPUTE (0xcb33U) /* finn: Evaluated from "NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID" */
/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
#define NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID (0xcb33U)
/*
* NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK
*
* This command prevents RM from using callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
*/
#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */
typedef struct NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS {
NvHandle hClient;
} NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS;
/*
* NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK
*
* This command permits RM to use callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
*/
#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */
/* _ctrl0080rc_h_ */

140
src/common/sdk/nvidia/inc/class/clcba2.h Normal file
View File

@@ -0,0 +1,140 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _clcba2_h_
#define _clcba2_h_
#ifdef __cplusplus
extern "C" {
#endif
#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000CBA2)
typedef volatile struct _clcba2_tag0 {
NvV32 Reserved00[0x100];
NvV32 DecryptCopySrcAddrHi; // 0x00000400 - 0x00000403
NvV32 DecryptCopySrcAddrLo; // 0x00000404 - 0x00000407
NvV32 DecryptCopyDstAddrHi; // 0x00000408 - 0x0000040B
NvV32 DecryptCopyDstAddrLo; // 0x0000040c - 0x0000040F
NvU32 DecryptCopySize; // 0x00000410 - 0x00000413
NvU32 DecryptCopyAuthTagAddrHi; // 0x00000414 - 0x00000417
NvU32 DecryptCopyAuthTagAddrLo; // 0x00000418 - 0x0000041B
NvV32 DigestAddrHi; // 0x0000041C - 0x0000041F
NvV32 DigestAddrLo; // 0x00000420 - 0x00000423
NvV32 Reserved01[0x7];
NvV32 SemaphoreA; // 0x00000440 - 0x00000443
NvV32 SemaphoreB; // 0x00000444 - 0x00000447
NvV32 SemaphoreSetPayloadLower; // 0x00000448 - 0x0000044B
NvV32 SemaphoreSetPayloadUppper; // 0x0000044C - 0x0000044F
NvV32 SemaphoreD; // 0x00000450 - 0x00000453
NvU32 Reserved02[0x7];
NvV32 Execute; // 0x00000470 - 0x00000473
NvV32 Reserved03[0x23];
} NVCBA2_HOPPER_SEC2_WORK_LAUNCH_AControlPio;
#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI (0x00000400)
#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI_DATA 24:0
#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO (0x00000404)
#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO_DATA 31:4
#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI (0x00000408)
#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI_DATA 24:0
#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO (0x0000040c)
#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO_DATA 31:4
#define NVCBA2_DECRYPT_COPY_SIZE (0x00000410)
#define NVCBA2_DECRYPT_COPY_SIZE_DATA 31:2
#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI (0x00000414)
#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI_DATA 24:0
#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO (0x00000418)
#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO_DATA 31:4
#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI (0x0000041C)
#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI_DATA 24:0
#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO (0x00000420)
#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO_DATA 31:4
#define NVCBA2_SEMAPHORE_A (0x00000440)
#define NVCBA2_SEMAPHORE_A_UPPER 24:0
#define NVCBA2_SEMAPHORE_B (0x00000444)
#define NVCBA2_SEMAPHORE_B_LOWER 31:2
#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER (0x00000448)
#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER_DATA 31:0
#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000044C)
#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER_DATA 31:0
#define NVCBA2_SEMAPHORE_D (0x00000450)
#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR 0:0
#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_DISABLE (0x00000000)
#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_ENABLE (0x00000001)
#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE 1:1
#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_32_BIT (0x00000000)
#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_64_BIT (0x00000001)
#define NVCBA2_SEMAPHORE_D_TIMESTAMP 2:2
#define NVCBA2_SEMAPHORE_D_TIMESTAMP_DISABLE (0x00000000)
#define NVCBA2_SEMAPHORE_D_TIMESTAMP_ENABLE (0x00000001)
#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE 3:3
#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000)
#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001)
#define NVCBA2_EXECUTE (0x00000470)
#define NVCBA2_EXECUTE_NOTIFY 0:0
#define NVCBA2_EXECUTE_NOTIFY_DISABLE (0x00000000)
#define NVCBA2_EXECUTE_NOTIFY_ENABLE (0x00000001)
#define NVCBA2_EXECUTE_NOTIFY_ON 1:1
#define NVCBA2_EXECUTE_NOTIFY_ON_END (0x00000000)
#define NVCBA2_EXECUTE_NOTIFY_ON_BEGIN (0x00000001)
#define NVCBA2_EXECUTE_FLUSH_DISABLE 2:2
#define NVCBA2_EXECUTE_FLUSH_DISABLE_FALSE (0x00000000)
#define NVCBA2_EXECUTE_FLUSH_DISABLE_TRUE (0x00000001)
#define NVCBA2_EXECUTE_NOTIFY_INTR 3:3
#define NVCBA2_EXECUTE_NOTIFY_INTR_DISABLE (0x00000000)
#define NVCBA2_EXECUTE_NOTIFY_INTR_ENABLE (0x00000001)
#define NVCBA2_EXECUTE_PAYLOAD_SIZE 4:4
#define NVCBA2_EXECUTE_PAYLOAD_SIZE_32_BIT (0x00000000)
#define NVCBA2_EXECUTE_PAYLOAD_SIZE_64_BIT (0x00000001)
#define NVCBA2_EXECUTE_TIMESTAMP 5:5
#define NVCBA2_EXECUTE_TIMESTAMP_DISABLE (0x00000000)
#define NVCBA2_EXECUTE_TIMESTAMP_ENABLE (0x00000001)
// Class definitions
#define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024)
// Errors
#define NVCBA2_ERROR_NONE (0x00000000)
#define NVCBA2_ERROR_DECRYPT_COPY_SRC_ADDR_MISALIGNED_POINTER (0x00000001)
#define NVCBA2_ERROR_DECRYPT_COPY_DEST_ADDR_MISALIGNED_POINTER (0x00000002)
#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000003)
#define NVCBA2_ERROR_DECRYPT_COPY_DMA_NACK (0x00000004)
#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_MISMATCH (0x00000005)
#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000006)
#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_DMA_NACK (0x00000007)
#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_CHECK_FAILURE (0x00000008)
#define NVCBA2_ERROR_MISALIGNED_SIZE (0x00000009)
#define NVCBA2_ERROR_MISSING_METHODS (0x0000000A)
#define NVCBA2_ERROR_SEMAPHORE_RELEASE_DMA_NACK (0x0000000B)
#define NVCBA2_ERROR_DECRYPT_SIZE_MAX_EXCEEDED (0x0000000C)
#define NVCBA2_ERROR_OS_APPLICATION (0x0000000D)
#define NVCBA2_ERROR_INVALID_CTXSW_REQUEST (0x0000000E)
#define NVCBA2_ERROR_BUFFER_OVERFLOW (0x0000000F)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcba2_h

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000base.finn
// Source file: ctrl/ctrl0000/ctrl0000base.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000client.finn
// Source file: ctrl/ctrl0000/ctrl0000client.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000event.finn
// Source file: ctrl/ctrl0000/ctrl0000event.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
@@ -143,7 +143,8 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
* GPU instance numbers are assigned in bus-probe order beginning with
* zero and are limited to one less the number of GPUs in the system.
* [out] numaId
* This parameter returns the ID of NUMA node for the specified GPU.
* This parameter returns the ID of NUMA node for the specified GPU or
* the subscribed MIG partition when MIG is enabled.
* In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned.
*
* Possible status values returned are:

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

56
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000system.finn
// Source file: ctrl/ctrl0000/ctrl0000system.finn
//
#include "ctrl/ctrlxxxx.h"
@@ -296,8 +296,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
/* Generic types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U)
/* processor capabilities */
#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U)
@@ -322,47 +321,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U)
#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U)
/* feature mask (as opposed to bugs, requirements, etc.) */
#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CAPS
*
* This command returns the set of system capabilities in the
* form of an array of unsigned bytes. System capabilities include
* supported features and required workarounds for the system,
* each represented by a byte offset into the table and a bit
* position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the system caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */
typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01
/* size in bytes of system caps table */
#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO
*
@@ -419,13 +377,13 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
/* maximum name string length */
#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U)
#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U)
/* invalid id */
#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU)
#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU)
#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U)
@@ -1572,9 +1530,11 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS {
* Please note: as implied above, administrator privileges are
* required to modify security settings.
*/
#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */
#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */
#define GPS_MAX_COUNTERS_PER_BLOCK 32U
#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS {
NvU32 objHndl;
NvU32 blockId;

7
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
@@ -418,8 +418,7 @@ typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC 4
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0002.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0002.finn
// Source file: ctrl/ctrl0002.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0004.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0004.finn
// Source file: ctrl/ctrl0004.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl000f.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl000f.finn
// Source file: ctrl/ctrl000f.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0020.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0020.finn
// Source file: ctrl/ctrl0020.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl003e.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl003e.finn
// Source file: ctrl/ctrl003e.finn
//
#include "ctrl/ctrlxxxx.h"

4
src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0041.finn
// Source file: ctrl/ctrl0041.finn
//
#include "nvos.h"
@@ -378,7 +378,7 @@ typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS {
#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS {
NvU32 pageSize; /* [out] - page size */
NV_DECLARE_ALIGNED(NvU64 pageSize, 8); /* [out] - page size */
} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS;
/*

180
src/common/sdk/nvidia/inc/ctrl/ctrl0050.h Normal file
View File

@@ -0,0 +1,180 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0050.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV0050_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x0050, NV0050_CTRL_##cat, idx)
#define NV0050_CTRL_RESERVED (0x00U)
#define NV0050_CTRL_MEMORY (0x01U)
#define NV0050_CTRL_CMD_NULL (0x5000U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV0050_CTRL_CMD_MEMSET
*
* Memsets a memory allocation and releases a semaphore on completion.
*
* hMemory [IN]
* Memory handle of the memory descriptor that needs to be memset.
* This is only available for verification purposes.
*
* offset [IN]
* Offset into the memory descriptor.
*
* length [IN]
* Length of physical memory to be memset.
* Must be less than or equal to memory size.
*
* pattern [IN]
* The pattern to memset to
*
* flags [IN]
* Can be any of the NV0050_CTRL_MEMSET_FLAGS_*
* DEFAULT
* By default, the memcopy operation will be synchronous and using
* physical copies
* ASYNC
* This flag forces this memset to be asynchronous.
* VIRTUAL
* This flag forces the memset to use Virtual addresses which are
* identity mapped. To use this feature, users need to pass in the
* hVaspace with identity mapped addresses for the entire memory during
* construct.
*
* submittedWorkId [OUT]
* The work submission token users can poll on to wait for work
* completed by CE. Only valid in case of ASYNC mode.
*/
#define NV0050_CTRL_MEMSET_FLAGS_DEFAULT 0
#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0)
#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1)
#define NV0050_CTRL_CMD_MEMSET (0x500101U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8) | NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID" */
#define NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0050_CTRL_MEMSET_PARAMS {
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 length, 8);
NvU32 pattern;
NV_DECLARE_ALIGNED(NvU64 flags, 8);
NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8);
} NV0050_CTRL_MEMSET_PARAMS;
/*
* NV0050_CTRL_CMD_MEMCOPY
*
* Copies from a source memoryto ssdestination memory and releases a semaphore
* on completion
*
* hDstMemory [IN]
* Memory handle of the memory descriptor to which data will be copied.
* This is only available for verification purposes.
*
* hSrcMemory [IN]
* Memory handle of the memory descriptor from which data will be copied.
* This is only available for verification purposes.
*
* dstOfffset [IN]
* Offset into the destination memory descriptor.
*
* srcOffset [IN]
* Offset into the source memory descriptor.
*
* length [IN]
* Length of physical memory to be copied.
* Must be less than or equal to both destination and source memory size.
*
* flags [IN]
* Can be any of the NV0050_CTRL_MEMCOPY_FLAGS_*
* DEFAULT
* By default, the memcopy operation will be synchronous and using
* physical copies
* ASYNC
* This flag forces this memset to be asynchronous.
* VIRTUAL
* This flag forces the memset to use Virtual addresses which are
* identity mapped. To use this feature, users need to pass in the
* hVaspace with identity mapped addresses for the entire memory during
* construct.
*
* submittedWorkId [OUT]
* The work submission token users can poll on to wait for work
* completed by CE. Only valid in case of ASYNC mode.
*/
#define NV0050_CTRL_MEMCOPY_FLAGS_DEFAULT 0
#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(1)
#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(2)
#define NV0050_CTRL_CMD_MEMCOPY (0x500102U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID)" */
#define NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0050_CTRL_MEMCOPY_PARAMS {
NvHandle hDstMemory;
NvHandle hSrcMemory;
NV_DECLARE_ALIGNED(NvU64 dstOffset, 8);
NV_DECLARE_ALIGNED(NvU64 srcOffset, 8);
NV_DECLARE_ALIGNED(NvU64 length, 8);
NV_DECLARE_ALIGNED(NvU64 flags, 8);
NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8);
} NV0050_CTRL_MEMCOPY_PARAMS;
/*
* NV0050_CTRL_CMD_CHECK_PROGRESS
*
* Check if a previously submitted work item has been completed by HW.
*
* submittedWorkId [IN]
* The work submission token users can poll on to wait for work
* completed by CE.
*
*/
#define NV0050_CTRL_CHECK_PROGRESS_RESULT_DEFAULT 0
#define NV0050_CTRL_CHECK_PROGRESS_RESULT_FINISHED NVBIT(1)
#define NV0050_CTRL_CMD_CHECK_PROGRESS (0x500103U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID)" */
#define NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0050_CTRL_CHECK_PROGRESS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8);
NvU32 result;
} NV0050_CTRL_CHECK_PROGRESS_PARAMS;
/* _ctrl0050_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073.finn
// Source file: ctrl/ctrl0073.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073base.finn
// Source file: ctrl/ctrl0073/ctrl0073base.finn
//
#include "ctrl/ctrlxxxx.h"

40
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h
View File

@@ -23,11 +23,49 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073common.finn
// Source file: ctrl/ctrl0073/ctrl0073common.finn
//
/*
* DSC caps -
* bDscSupported
* If GPU supports DSC or not
*
* encoderColorFormatMask
* Mask of all color formats for which DSC
* encoding is supported by GPU
*
* lineBufferSizeKB
* Size of line buffer.
*
* rateBufferSizeKB
* Size of rate buffer per slice.
*
* bitsPerPixelPrecision
* Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp
*
* maxNumHztSlices
* Maximum number of horizontal slices supported by DSC encoder
*
* lineBufferBitDepth
* Bit depth used by the GPU to store the reconstructed pixels within
* the line buffer
*/
#define NV0073_CTRL_CMD_DSC_CAP_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} NV0073_CTRL_CMD_DSC_CAP_PARAMS;
/* _ctrl0073common_h_ */

168
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -27,10 +27,13 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dfp.finn
// Source file: ctrl/ctrl0073/ctrl0073dfp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073common.h"
#include "nvcfg_sdk.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -84,8 +87,7 @@
* This specifies whether the displayId is capable of sending
* YCBCR444 color format out from the board.
* NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH
* This specifies whether the displayId is capable of doing high
* bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is
* This specifies max link rate supported by the displayId, if the DFP is
* display port.
* NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED
* This specifies whether the DFP displayId is allowed to transmit HDMI
@@ -105,6 +107,8 @@
* This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode).
* NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE
* This indicates whether this DFP supports Dynamic MUX
* flags2
* This parameter returns the extra information specific to this dfp.
*
* Possible status values returned are:
* NV_OK
@@ -119,76 +123,77 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 flags;
NvU32 flags2;
} NV0073_CTRL_DFP_GET_INFO_PARAMS;
/* valid display types */
#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U)
#define NV0073_CTRL_DFP_FLAGS_LANE 5:3
#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6
#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_LINK 21:20
#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
@@ -569,7 +574,7 @@ typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO {
* _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable.
* _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'.
*
* Possible status values returned are:
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
@@ -1157,40 +1162,31 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS {
#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U)
typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
NvBool dscUseCustomPPS;
NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT];
struct {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} dscEncoderCaps;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
NvBool dscUseCustomPPS;
NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT];
NV0073_CTRL_CMD_DSC_CAP_PARAMS dscEncoderCaps;
} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS;

67
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
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@@ -27,10 +27,13 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dp.finn
// Source file: ctrl/ctrl0073/ctrl0073dp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073common.h"
#include "nvcfg_sdk.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -1766,29 +1769,7 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* bOverrideLinkBw
* Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE
*
* DSC caps -
* bDscSupported
* If GPU supports DSC or not
*
* encoderColorFormatMask
* Mask of all color formats for which DSC
* encoding is supported by GPU
*
* lineBufferSizeKB
* Size of line buffer.
*
* rateBufferSizeKB
* Size of rate buffer per slice.
*
* bitsPerPixelPrecision
* Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp
*
* maxNumHztSlices
* Maximum number of horizontal slices supported by DSC encoder
*
* lineBufferBitDepth
* Bit depth used by the GPU to store the reconstructed pixels within
* the line buffer
* DSC caps
*
* Possible status values returned are:
* NV_OK
@@ -1802,28 +1783,20 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U)
typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvU32 subDeviceInstance;
NvU32 sorIndex;
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
NvBool bIsPC2Disabled;
NvBool isSingleHeadMSTSupported;
NvBool bFECSupported;
NvBool bIsTrainPhyRepeater;
NvBool bOverrideLinkBw;
struct {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} DSC;
NvU32 subDeviceInstance;
NvU32 sorIndex;
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupported;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
NvBool bIsPC2Disabled;
NvBool isSingleHeadMSTSupported;
NvBool bFECSupported;
NvBool bIsTrainPhyRepeater;
NvBool bOverrideLinkBw;
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0
@@ -1834,7 +1807,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U)
@@ -1842,6 +1814,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dpu.finn
// Source file: ctrl/ctrl0073/ctrl0073dpu.finn
//

100
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
View File

@@ -27,6 +27,104 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073event.finn
// Source file: ctrl/ctrl0073/ctrl0073event.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON event-related control commands and parameters */
/*
* NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the associated display
* object. This command requires that an instance of NV01_EVENT has been
* previously bound to the associated display object.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* hEvent
* This parameter specifies the handle of the NV01_EVENT instance
* to be bound to the given subDeviceInstance.
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NV0073_NOTIFIERS value (see cl0073.h for more details) and should
* not exceed one less NV0073_NOTIFIERS_MAXCOUNT.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV0073_CTRL_SET_EVENT_NOTIFICATION_DISABLE
* This action disables event notification for the specified
* event for the associated subdevice object.
* NV0073_CTRL_SET_EVENT_NOTIFICATION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated subdevice object.
* NV0073_CTRL_SET_EVENT_NOTIFICATION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated system controller object.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION (0x730301U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 subDeviceInstance;
NvHandle hEvent;
NvU32 event;
NvU32 action;
} NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U)
/*
* NV0073_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
*
* hMemory
* This parameter specifies the handle of the memory object
* that identifies the memory address translation for this
* subdevice instance's notification(s). The beginning of the
* translation points to an array of notification data structures.
* The size of the translation must be at least large enough to hold the
* maximum number of notification data structures identified by
* the NV0073_MAX_NOTIFIERS value.
* Legal argument values must be instances of the following classes:
* NV01_NULL
* NV04_MEMORY
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
* memory translation connection is cleared. There must not be any
* pending notifications when this command is issued.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x730303U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
NvU32 subDeviceInstance;
NvHandle hMemory;
} NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2U
/* _ctrl0073event_h_ */

8
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
@@ -37,4 +37,10 @@
typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE (0x730402U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x2U)
typedef NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS;
/* ctrl0073internal_h */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073psr.finn
// Source file: ctrl/ctrl0073/ctrl0073psr.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"

14
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073specific.finn
// Source file: ctrl/ctrl0073/ctrl0073specific.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
@@ -1274,6 +1274,10 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS {
* powerState
* This parameter should be one of the valid
* NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values.
* headIdx
* The head id on which power operation needs to be done.
* bForceMonitorState
* Monitor power state that client wants to force in RM.
*
* Possible status values returned are:
* NV_OK
@@ -1285,9 +1289,11 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS {
#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U)
typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 powerState;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 powerState;
NvU32 headIdx;
NvBool bForceMonitorState;
} NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS;
#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF (0x00000000U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073svp.finn
// Source file: ctrl/ctrl0073/ctrl0073svp.finn
//

123
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073system.finn
// Source file: ctrl/ctrl0073/ctrl0073system.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
@@ -809,6 +809,42 @@ typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS {
NvU32 availableInternalDisplaysMask;
} NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED
*
* This command is used to notify RM that all subdevices are ready for ACPI
* calls. The caller must make sure that the OS is ready to handle the ACPI
* calls for each ACPI ID. So, this call must be done after the OS has
* initialized all the display ACPI IDs to this subdevice.
* Besides, the ACPI spec provides a function for the display drivers to read
* the EDID directly from the SBIOS for each display's ACPI ID. This function
* is used to override the EDID found from a I2C or DPAux based transaction.
* This command will also attempt to call the ACPI _DDC function to read the
* EDID from the SBIOS for all displayIDs. If an EDID is found from this call,
* the RM will store that new EDID in the EDID buffer of that OD.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID (0x5CU)
typedef struct NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS {
NvU32 subDeviceInstance;
} NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS;
#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x73015cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_SYSTEM_CONNECTOR_INFO
@@ -1229,6 +1265,36 @@ typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
/*
* NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS
*
* This command is used to update information about VRR capable monitors
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.This parameter must specify a value between zero and the
* total number of subdevices within the parent device.This parameter
* should be set to zero for default behavior.
*
* displayId
* DisplayId of the panel for which client wants to add or remove from VRR
* capable monitor list
*
* bAddition
* When set to NV_TRUE, signifies that the vrr monitor is to be added.
* When set to NV_FALSE, signifies that the vrr monitor is to be removed.
*
*/
#define NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO (0x730185U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bAddition;
} NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE
*
@@ -1670,5 +1736,60 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS {
NvBool bIsSidebandSrSupported;
} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE
*
* This command is used by client like nvkms to set up the VRR specific
* memory operation in RM such as mapping the client created shared memory
* into RM and reserving a RGline for processing of self-refresh timeout
* related calculations.
*
* Also the expectation is that the client which calls this command with parameter
* bEnable = TRUE, should also call this command with bEnable = FALSE on the
* same head when VRR needs to be disabled.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_GENERIC
*/
/*
* This is the shared structure that will be used to communicate between
* Physical RM and clients. As of now the access relies on single source of
* truth operation, i.e. only Physical RM writes into the shared location
* and client (nvkms) reads from the same location.
*
* "dataTimeStamp" field is added to capture the timestamp before and after
* updating the flip delay related data fields(all fields except "timeout").
* This timestamp will be used by clients to determine if the data got updated
* in between by RM while clients were reading it.
* As of now "timeout" field does not have such protection, as access to
* this field is only in response to notification from RM.
*/
typedef struct NV0073_CTRL_RM_VRR_SHARED_DATA {
NvU32 expectedFrameNum;
NvU32 timeout;
NV_DECLARE_ALIGNED(NvU64 flipTimeStamp, 8);
NvBool bCheckFlipTime;
NvBool bFlipTimeAdjustment;
NV_DECLARE_ALIGNED(NvU64 dataTimeStamp, 8);
} NV0073_CTRL_RM_VRR_SHARED_DATA;
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE (0x73019eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x9EU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
NvU32 subDeviceInstance;
NvBool bEnable;
NvU32 head;
NvU32 height;
NvU32 maxFrameTime;
NvU32 minFrameTime;
NvHandle hMemory;
} NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS;
/* _ctrl0073system_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080.finn
// Source file: ctrl/ctrl0080.finn
//
@@ -45,7 +45,6 @@
#include "ctrl0080/ctrl0080perf.h"
#include "ctrl0080/ctrl0080msenc.h"
#include "ctrl0080/ctrl0080bsp.h"
#include "ctrl0080/ctrl0080rc.h"
#include "ctrl0080/ctrl0080nvjpg.h"
#include "ctrl0080/ctrl0080unix.h"
#include "ctrl0080/ctrl0080internal.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080base.finn
// Source file: ctrl/ctrl0080/ctrl0080base.finn
//
#include "ctrl/ctrlxxxx.h"

7
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080bif.finn
// Source file: ctrl/ctrl0080/ctrl0080bif.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
@@ -69,6 +69,7 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE 0x4
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7
/*
* NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR
@@ -138,7 +139,7 @@ typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS {
} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS;
/*
* NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK
* NV0080_CTRL_BIF_ASPM_FEATURE
*
* pciePowerControlMask
* pciePowerControlIdentifiedKeyOrder

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